1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "AArch64TargetMachine.h"
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Support/TargetRegistry.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/Transforms/Scalar.h"
24 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
25 cl::init(true), cl::Hidden);
27 static cl::opt<bool> EnableMCR("aarch64-mcr",
28 cl::desc("Enable the machine combiner pass"),
29 cl::init(true), cl::Hidden);
32 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
33 cl::init(true), cl::Hidden);
36 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
37 " integer instructions"), cl::init(false), cl::Hidden);
40 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
41 "constant pass"), cl::init(true), cl::Hidden);
44 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
45 " linker optimization hints (LOH)"), cl::init(true),
49 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
50 cl::desc("Enable the pass that removes dead"
51 " definitons and replaces stores to"
52 " them with stores to the zero"
57 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
58 " optimization pass"), cl::init(true), cl::Hidden);
61 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
62 cl::desc("Run SimplifyCFG after expanding atomic operations"
63 " to make use of cmpxchg flow-based information"),
67 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
68 cl::desc("Run early if-conversion"),
72 EnableCondOpt("aarch64-condopt",
73 cl::desc("Enable the condition optimizer pass"),
74 cl::init(true), cl::Hidden);
77 extern "C" void LLVMInitializeAArch64Target() {
78 // Register the target.
79 RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
80 RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
81 RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
84 /// TargetMachine ctor - Create an AArch64 architecture model.
86 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
87 StringRef CPU, StringRef FS,
88 const TargetOptions &Options,
89 Reloc::Model RM, CodeModel::Model CM,
92 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
93 Subtarget(TT, CPU, FS, *this, LittleEndian) {
97 void AArch64leTargetMachine::anchor() { }
99 AArch64leTargetMachine::
100 AArch64leTargetMachine(const Target &T, StringRef TT,
101 StringRef CPU, StringRef FS, const TargetOptions &Options,
102 Reloc::Model RM, CodeModel::Model CM,
103 CodeGenOpt::Level OL)
104 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
106 void AArch64beTargetMachine::anchor() { }
108 AArch64beTargetMachine::
109 AArch64beTargetMachine(const Target &T, StringRef TT,
110 StringRef CPU, StringRef FS, const TargetOptions &Options,
111 Reloc::Model RM, CodeModel::Model CM,
112 CodeGenOpt::Level OL)
113 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
116 /// AArch64 Code Generator Pass Configuration Options.
117 class AArch64PassConfig : public TargetPassConfig {
119 AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
120 : TargetPassConfig(TM, PM) {}
122 AArch64TargetMachine &getAArch64TargetMachine() const {
123 return getTM<AArch64TargetMachine>();
126 void addIRPasses() override;
127 bool addPreISel() override;
128 bool addInstSelector() override;
129 bool addILPOpts() override;
130 bool addPreRegAlloc() override;
131 bool addPostRegAlloc() override;
132 bool addPreSched2() override;
133 bool addPreEmitPass() override;
137 void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
138 // Add first the target-independent BasicTTI pass, then our AArch64 pass. This
139 // allows the AArch64 pass to delegate to the target independent layer when
141 PM.add(createBasicTargetTransformInfoPass(this));
142 PM.add(createAArch64TargetTransformInfoPass(this));
145 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
146 return new AArch64PassConfig(this, PM);
149 void AArch64PassConfig::addIRPasses() {
150 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
152 addPass(createAtomicExpandPass(TM));
154 // Cmpxchg instructions are often used with a subsequent comparison to
155 // determine whether it succeeded. We can exploit existing control-flow in
156 // ldrex/strex loops to simplify this, but it needs tidying up.
157 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
158 addPass(createCFGSimplificationPass());
160 TargetPassConfig::addIRPasses();
163 // Pass Pipeline Configuration
164 bool AArch64PassConfig::addPreISel() {
165 // Run promote constant before global merge, so that the promoted constants
166 // get a chance to be merged
167 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
168 addPass(createAArch64PromoteConstantPass());
169 if (TM->getOptLevel() != CodeGenOpt::None)
170 addPass(createGlobalMergePass(TM));
171 if (TM->getOptLevel() != CodeGenOpt::None)
172 addPass(createAArch64AddressTypePromotionPass());
177 bool AArch64PassConfig::addInstSelector() {
178 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
180 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
181 // references to _TLS_MODULE_BASE_ as possible.
182 if (TM->getSubtarget<AArch64Subtarget>().isTargetELF() &&
183 getOptLevel() != CodeGenOpt::None)
184 addPass(createAArch64CleanupLocalDynamicTLSPass());
189 bool AArch64PassConfig::addILPOpts() {
191 addPass(createAArch64ConditionOptimizerPass());
193 addPass(createAArch64ConditionalCompares());
195 addPass(&MachineCombinerID);
196 if (EnableEarlyIfConversion)
197 addPass(&EarlyIfConverterID);
198 if (EnableStPairSuppress)
199 addPass(createAArch64StorePairSuppressPass());
203 bool AArch64PassConfig::addPreRegAlloc() {
204 // Use AdvSIMD scalar instructions whenever profitable.
205 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
206 addPass(createAArch64AdvSIMDScalar());
207 // The AdvSIMD pass may produce copies that can be rewritten to
208 // be register coaleascer friendly.
209 addPass(&PeepholeOptimizerID);
214 bool AArch64PassConfig::addPostRegAlloc() {
215 // Change dead register definitions to refer to the zero register.
216 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
217 addPass(createAArch64DeadRegisterDefinitions());
218 if (TM->getOptLevel() != CodeGenOpt::None &&
219 TM->getSubtarget<AArch64Subtarget>().isCortexA57())
220 // Improve performance for some FP/SIMD code for A57.
221 addPass(createAArch64A57FPLoadBalancing());
225 bool AArch64PassConfig::addPreSched2() {
226 // Expand some pseudo instructions to allow proper scheduling.
227 addPass(createAArch64ExpandPseudoPass());
228 // Use load/store pair instructions when possible.
229 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
230 addPass(createAArch64LoadStoreOptimizationPass());
234 bool AArch64PassConfig::addPreEmitPass() {
235 // Relax conditional branch instructions if they're otherwise out of
236 // range of their destination.
237 addPass(createAArch64BranchRelaxation());
238 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
239 TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
240 addPass(createAArch64CollectLOHPass());