1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "AArch64TargetMachine.h"
15 #include "AArch64TargetObjectFile.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/CodeGen/RegAllocRegistry.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/PassManager.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/Transforms/Scalar.h"
27 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
28 cl::init(true), cl::Hidden);
30 static cl::opt<bool> EnableMCR("aarch64-mcr",
31 cl::desc("Enable the machine combiner pass"),
32 cl::init(true), cl::Hidden);
35 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
36 cl::init(true), cl::Hidden);
39 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
40 " integer instructions"), cl::init(false), cl::Hidden);
43 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
44 "constant pass"), cl::init(true), cl::Hidden);
47 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
48 " linker optimization hints (LOH)"), cl::init(true),
52 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
53 cl::desc("Enable the pass that removes dead"
54 " definitons and replaces stores to"
55 " them with stores to the zero"
60 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
61 " optimization pass"), cl::init(true), cl::Hidden);
64 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
65 cl::desc("Run SimplifyCFG after expanding atomic operations"
66 " to make use of cmpxchg flow-based information"),
70 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
71 cl::desc("Run early if-conversion"),
75 EnableCondOpt("aarch64-condopt",
76 cl::desc("Enable the condition optimizer pass"),
77 cl::init(true), cl::Hidden);
80 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
81 cl::desc("Work around Cortex-A53 erratum 835769"),
84 extern "C" void LLVMInitializeAArch64Target() {
85 // Register the target.
86 RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
87 RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
88 RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
91 //===----------------------------------------------------------------------===//
92 // AArch64 Lowering public interface.
93 //===----------------------------------------------------------------------===//
94 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
95 if (TT.isOSBinFormatMachO())
96 return make_unique<AArch64_MachoTargetObjectFile>();
98 return make_unique<AArch64_ELFTargetObjectFile>();
101 /// TargetMachine ctor - Create an AArch64 architecture model.
103 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
104 StringRef CPU, StringRef FS,
105 const TargetOptions &Options,
106 Reloc::Model RM, CodeModel::Model CM,
107 CodeGenOpt::Level OL,
109 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
110 TLOF(createTLOF(Triple(getTargetTriple()))),
111 Subtarget(TT, CPU, FS, *this, LittleEndian), isLittle(LittleEndian) {
115 const AArch64Subtarget *
116 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
117 AttributeSet FnAttrs = F.getAttributes();
119 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
121 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
123 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
124 ? CPUAttr.getValueAsString().str()
126 std::string FS = !FSAttr.hasAttribute(Attribute::None)
127 ? FSAttr.getValueAsString().str()
130 auto &I = SubtargetMap[CPU + FS];
132 // This needs to be done before we create a new subtarget since any
133 // creation will depend on the TM and the code generation flags on the
134 // function that reside in TargetOptions.
135 resetTargetOptions(F);
136 I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this, isLittle);
141 void AArch64leTargetMachine::anchor() { }
143 AArch64leTargetMachine::
144 AArch64leTargetMachine(const Target &T, StringRef TT,
145 StringRef CPU, StringRef FS, const TargetOptions &Options,
146 Reloc::Model RM, CodeModel::Model CM,
147 CodeGenOpt::Level OL)
148 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
150 void AArch64beTargetMachine::anchor() { }
152 AArch64beTargetMachine::
153 AArch64beTargetMachine(const Target &T, StringRef TT,
154 StringRef CPU, StringRef FS, const TargetOptions &Options,
155 Reloc::Model RM, CodeModel::Model CM,
156 CodeGenOpt::Level OL)
157 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
160 /// AArch64 Code Generator Pass Configuration Options.
161 class AArch64PassConfig : public TargetPassConfig {
163 AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
164 : TargetPassConfig(TM, PM) {
165 if (TM->getOptLevel() != CodeGenOpt::None)
166 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
169 AArch64TargetMachine &getAArch64TargetMachine() const {
170 return getTM<AArch64TargetMachine>();
173 void addIRPasses() override;
174 bool addPreISel() override;
175 bool addInstSelector() override;
176 bool addILPOpts() override;
177 bool addPreRegAlloc() override;
178 bool addPostRegAlloc() override;
179 bool addPreSched2() override;
180 bool addPreEmitPass() override;
184 void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
185 // Add first the target-independent BasicTTI pass, then our AArch64 pass. This
186 // allows the AArch64 pass to delegate to the target independent layer when
188 PM.add(createBasicTargetTransformInfoPass(this));
189 PM.add(createAArch64TargetTransformInfoPass(this));
192 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
193 return new AArch64PassConfig(this, PM);
196 void AArch64PassConfig::addIRPasses() {
197 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
199 addPass(createAtomicExpandPass(TM));
201 // Cmpxchg instructions are often used with a subsequent comparison to
202 // determine whether it succeeded. We can exploit existing control-flow in
203 // ldrex/strex loops to simplify this, but it needs tidying up.
204 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
205 addPass(createCFGSimplificationPass());
207 TargetPassConfig::addIRPasses();
210 // Pass Pipeline Configuration
211 bool AArch64PassConfig::addPreISel() {
212 // Run promote constant before global merge, so that the promoted constants
213 // get a chance to be merged
214 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
215 addPass(createAArch64PromoteConstantPass());
216 if (TM->getOptLevel() != CodeGenOpt::None)
217 addPass(createGlobalMergePass(TM));
218 if (TM->getOptLevel() != CodeGenOpt::None)
219 addPass(createAArch64AddressTypePromotionPass());
224 bool AArch64PassConfig::addInstSelector() {
225 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
227 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
228 // references to _TLS_MODULE_BASE_ as possible.
229 if (TM->getSubtarget<AArch64Subtarget>().isTargetELF() &&
230 getOptLevel() != CodeGenOpt::None)
231 addPass(createAArch64CleanupLocalDynamicTLSPass());
236 bool AArch64PassConfig::addILPOpts() {
238 addPass(createAArch64ConditionOptimizerPass());
240 addPass(createAArch64ConditionalCompares());
242 addPass(&MachineCombinerID);
243 if (EnableEarlyIfConversion)
244 addPass(&EarlyIfConverterID);
245 if (EnableStPairSuppress)
246 addPass(createAArch64StorePairSuppressPass());
250 bool AArch64PassConfig::addPreRegAlloc() {
251 // Use AdvSIMD scalar instructions whenever profitable.
252 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
253 addPass(createAArch64AdvSIMDScalar());
254 // The AdvSIMD pass may produce copies that can be rewritten to
255 // be register coaleascer friendly.
256 addPass(&PeepholeOptimizerID);
261 bool AArch64PassConfig::addPostRegAlloc() {
262 // Change dead register definitions to refer to the zero register.
263 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
264 addPass(createAArch64DeadRegisterDefinitions());
265 if (TM->getOptLevel() != CodeGenOpt::None &&
266 (TM->getSubtarget<AArch64Subtarget>().isCortexA53() ||
267 TM->getSubtarget<AArch64Subtarget>().isCortexA57()) &&
268 usingDefaultRegAlloc())
269 // Improve performance for some FP/SIMD code for A57.
270 addPass(createAArch64A57FPLoadBalancing());
274 bool AArch64PassConfig::addPreSched2() {
275 // Expand some pseudo instructions to allow proper scheduling.
276 addPass(createAArch64ExpandPseudoPass());
277 // Use load/store pair instructions when possible.
278 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
279 addPass(createAArch64LoadStoreOptimizationPass());
283 bool AArch64PassConfig::addPreEmitPass() {
284 if (EnableA53Fix835769)
285 addPass(createAArch64A53Fix835769());
286 // Relax conditional branch instructions if they're otherwise out of
287 // range of their destination.
288 addPass(createAArch64BranchRelaxation());
289 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
290 TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
291 addPass(createAArch64CollectLOHPass());