1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "AArch64TargetMachine.h"
15 #include "AArch64TargetObjectFile.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/CodeGen/RegAllocRegistry.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/PassManager.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/Transforms/Scalar.h"
27 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
28 cl::init(true), cl::Hidden);
30 static cl::opt<bool> EnableMCR("aarch64-mcr",
31 cl::desc("Enable the machine combiner pass"),
32 cl::init(true), cl::Hidden);
35 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
36 cl::init(true), cl::Hidden);
39 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
40 " integer instructions"), cl::init(false), cl::Hidden);
43 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
44 "constant pass"), cl::init(true), cl::Hidden);
47 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
48 " linker optimization hints (LOH)"), cl::init(true),
52 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
53 cl::desc("Enable the pass that removes dead"
54 " definitons and replaces stores to"
55 " them with stores to the zero"
60 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
61 " optimization pass"), cl::init(true), cl::Hidden);
64 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
65 cl::desc("Run SimplifyCFG after expanding atomic operations"
66 " to make use of cmpxchg flow-based information"),
70 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
71 cl::desc("Run early if-conversion"),
75 EnableCondOpt("aarch64-condopt",
76 cl::desc("Enable the condition optimizer pass"),
77 cl::init(true), cl::Hidden);
80 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
81 cl::desc("Work around Cortex-A53 erratum 835769"),
85 EnableGEPOpt("aarch64-gep-opt", cl::Hidden,
86 cl::desc("Enable optimizations on complex GEPs"),
89 extern "C" void LLVMInitializeAArch64Target() {
90 // Register the target.
91 RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
92 RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
93 RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
96 //===----------------------------------------------------------------------===//
97 // AArch64 Lowering public interface.
98 //===----------------------------------------------------------------------===//
99 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
100 if (TT.isOSBinFormatMachO())
101 return make_unique<AArch64_MachoTargetObjectFile>();
103 return make_unique<AArch64_ELFTargetObjectFile>();
106 /// TargetMachine ctor - Create an AArch64 architecture model.
108 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
109 StringRef CPU, StringRef FS,
110 const TargetOptions &Options,
111 Reloc::Model RM, CodeModel::Model CM,
112 CodeGenOpt::Level OL,
114 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
115 // This nested ternary is horrible, but DL needs to be properly
117 // before TLInfo is constructed.
118 DL(Triple(TT).isOSBinFormatMachO()
119 ? "e-m:o-i64:64-i128:128-n32:64-S128"
120 : (LittleEndian ? "e-m:e-i64:64-i128:128-n32:64-S128"
121 : "E-m:e-i64:64-i128:128-n32:64-S128")),
122 TLOF(createTLOF(Triple(getTargetTriple()))),
123 Subtarget(TT, CPU, FS, *this, LittleEndian), isLittle(LittleEndian) {
127 AArch64TargetMachine::~AArch64TargetMachine() {}
129 const AArch64Subtarget *
130 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
131 AttributeSet FnAttrs = F.getAttributes();
133 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
135 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
137 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
138 ? CPUAttr.getValueAsString().str()
140 std::string FS = !FSAttr.hasAttribute(Attribute::None)
141 ? FSAttr.getValueAsString().str()
144 auto &I = SubtargetMap[CPU + FS];
146 // This needs to be done before we create a new subtarget since any
147 // creation will depend on the TM and the code generation flags on the
148 // function that reside in TargetOptions.
149 resetTargetOptions(F);
150 I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this, isLittle);
155 void AArch64leTargetMachine::anchor() { }
157 AArch64leTargetMachine::
158 AArch64leTargetMachine(const Target &T, StringRef TT,
159 StringRef CPU, StringRef FS, const TargetOptions &Options,
160 Reloc::Model RM, CodeModel::Model CM,
161 CodeGenOpt::Level OL)
162 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
164 void AArch64beTargetMachine::anchor() { }
166 AArch64beTargetMachine::
167 AArch64beTargetMachine(const Target &T, StringRef TT,
168 StringRef CPU, StringRef FS, const TargetOptions &Options,
169 Reloc::Model RM, CodeModel::Model CM,
170 CodeGenOpt::Level OL)
171 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
174 /// AArch64 Code Generator Pass Configuration Options.
175 class AArch64PassConfig : public TargetPassConfig {
177 AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
178 : TargetPassConfig(TM, PM) {
179 if (TM->getOptLevel() != CodeGenOpt::None)
180 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
183 AArch64TargetMachine &getAArch64TargetMachine() const {
184 return getTM<AArch64TargetMachine>();
187 void addIRPasses() override;
188 bool addPreISel() override;
189 bool addInstSelector() override;
190 bool addILPOpts() override;
191 void addPreRegAlloc() override;
192 void addPostRegAlloc() override;
193 void addPreSched2() override;
194 void addPreEmitPass() override;
198 void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
199 // Add first the target-independent BasicTTI pass, then our AArch64 pass. This
200 // allows the AArch64 pass to delegate to the target independent layer when
202 PM.add(createBasicTargetTransformInfoPass(this));
203 PM.add(createAArch64TargetTransformInfoPass(this));
206 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
207 return new AArch64PassConfig(this, PM);
210 void AArch64PassConfig::addIRPasses() {
211 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
213 addPass(createAtomicExpandPass(TM));
215 // Cmpxchg instructions are often used with a subsequent comparison to
216 // determine whether it succeeded. We can exploit existing control-flow in
217 // ldrex/strex loops to simplify this, but it needs tidying up.
218 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
219 addPass(createCFGSimplificationPass());
221 TargetPassConfig::addIRPasses();
223 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
224 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
225 // and lower a GEP with multiple indices to either arithmetic operations or
226 // multiple GEPs with single index.
227 addPass(createSeparateConstOffsetFromGEPPass(TM, true));
228 // Call EarlyCSE pass to find and remove subexpressions in the lowered
230 addPass(createEarlyCSEPass());
231 // Do loop invariant code motion in case part of the lowered result is
233 addPass(createLICMPass());
237 // Pass Pipeline Configuration
238 bool AArch64PassConfig::addPreISel() {
239 // Run promote constant before global merge, so that the promoted constants
240 // get a chance to be merged
241 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
242 addPass(createAArch64PromoteConstantPass());
243 if (TM->getOptLevel() != CodeGenOpt::None)
244 addPass(createGlobalMergePass(TM));
245 if (TM->getOptLevel() != CodeGenOpt::None)
246 addPass(createAArch64AddressTypePromotionPass());
251 bool AArch64PassConfig::addInstSelector() {
252 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
254 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
255 // references to _TLS_MODULE_BASE_ as possible.
256 if (Triple(TM->getTargetTriple()).isOSBinFormatELF() &&
257 getOptLevel() != CodeGenOpt::None)
258 addPass(createAArch64CleanupLocalDynamicTLSPass());
263 bool AArch64PassConfig::addILPOpts() {
265 addPass(createAArch64ConditionOptimizerPass());
267 addPass(createAArch64ConditionalCompares());
269 addPass(&MachineCombinerID);
270 if (EnableEarlyIfConversion)
271 addPass(&EarlyIfConverterID);
272 if (EnableStPairSuppress)
273 addPass(createAArch64StorePairSuppressPass());
277 void AArch64PassConfig::addPreRegAlloc() {
278 // Use AdvSIMD scalar instructions whenever profitable.
279 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
280 addPass(createAArch64AdvSIMDScalar());
281 // The AdvSIMD pass may produce copies that can be rewritten to
282 // be register coaleascer friendly.
283 addPass(&PeepholeOptimizerID);
287 void AArch64PassConfig::addPostRegAlloc() {
288 // Change dead register definitions to refer to the zero register.
289 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
290 addPass(createAArch64DeadRegisterDefinitions());
291 if (TM->getOptLevel() != CodeGenOpt::None &&
292 (TM->getSubtarget<AArch64Subtarget>().isCortexA53() ||
293 TM->getSubtarget<AArch64Subtarget>().isCortexA57()) &&
294 usingDefaultRegAlloc())
295 // Improve performance for some FP/SIMD code for A57.
296 addPass(createAArch64A57FPLoadBalancing());
299 void AArch64PassConfig::addPreSched2() {
300 // Expand some pseudo instructions to allow proper scheduling.
301 addPass(createAArch64ExpandPseudoPass());
302 // Use load/store pair instructions when possible.
303 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
304 addPass(createAArch64LoadStoreOptimizationPass());
307 void AArch64PassConfig::addPreEmitPass() {
308 if (EnableA53Fix835769)
309 addPass(createAArch64A53Fix835769());
310 // Relax conditional branch instructions if they're otherwise out of
311 // range of their destination.
312 addPass(createAArch64BranchRelaxation());
313 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
314 Triple(TM->getTargetTriple()).isOSBinFormatMachO())
315 addPass(createAArch64CollectLOHPass());