1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "AArch64TargetMachine.h"
15 #include "AArch64TargetObjectFile.h"
16 #include "AArch64TargetTransformInfo.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/RegAllocRegistry.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/TargetRegistry.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/Transforms/Scalar.h"
28 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
29 cl::init(true), cl::Hidden);
31 static cl::opt<bool> EnableMCR("aarch64-mcr",
32 cl::desc("Enable the machine combiner pass"),
33 cl::init(true), cl::Hidden);
36 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
37 cl::init(true), cl::Hidden);
40 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
41 " integer instructions"), cl::init(false), cl::Hidden);
44 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
45 "constant pass"), cl::init(true), cl::Hidden);
48 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
49 " linker optimization hints (LOH)"), cl::init(true),
53 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
54 cl::desc("Enable the pass that removes dead"
55 " definitons and replaces stores to"
56 " them with stores to the zero"
61 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
62 " optimization pass"), cl::init(true), cl::Hidden);
65 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
66 cl::desc("Run SimplifyCFG after expanding atomic operations"
67 " to make use of cmpxchg flow-based information"),
71 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
72 cl::desc("Run early if-conversion"),
76 EnableCondOpt("aarch64-condopt",
77 cl::desc("Enable the condition optimizer pass"),
78 cl::init(true), cl::Hidden);
81 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
82 cl::desc("Work around Cortex-A53 erratum 835769"),
86 EnableGEPOpt("aarch64-gep-opt", cl::Hidden,
87 cl::desc("Enable optimizations on complex GEPs"),
90 extern "C" void LLVMInitializeAArch64Target() {
91 // Register the target.
92 RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
93 RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
94 RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
97 //===----------------------------------------------------------------------===//
98 // AArch64 Lowering public interface.
99 //===----------------------------------------------------------------------===//
100 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
101 if (TT.isOSBinFormatMachO())
102 return make_unique<AArch64_MachoTargetObjectFile>();
104 return make_unique<AArch64_ELFTargetObjectFile>();
107 /// TargetMachine ctor - Create an AArch64 architecture model.
109 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
110 StringRef CPU, StringRef FS,
111 const TargetOptions &Options,
112 Reloc::Model RM, CodeModel::Model CM,
113 CodeGenOpt::Level OL,
115 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
116 // This nested ternary is horrible, but DL needs to be properly
118 // before TLInfo is constructed.
119 DL(Triple(TT).isOSBinFormatMachO()
120 ? "e-m:o-i64:64-i128:128-n32:64-S128"
121 : (LittleEndian ? "e-m:e-i64:64-i128:128-n32:64-S128"
122 : "E-m:e-i64:64-i128:128-n32:64-S128")),
123 TLOF(createTLOF(Triple(getTargetTriple()))),
124 Subtarget(TT, CPU, FS, *this, LittleEndian), isLittle(LittleEndian) {
128 AArch64TargetMachine::~AArch64TargetMachine() {}
130 const AArch64Subtarget *
131 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
132 Attribute CPUAttr = F.getFnAttribute("target-cpu");
133 Attribute FSAttr = F.getFnAttribute("target-features");
135 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
136 ? CPUAttr.getValueAsString().str()
138 std::string FS = !FSAttr.hasAttribute(Attribute::None)
139 ? FSAttr.getValueAsString().str()
142 auto &I = SubtargetMap[CPU + FS];
144 // This needs to be done before we create a new subtarget since any
145 // creation will depend on the TM and the code generation flags on the
146 // function that reside in TargetOptions.
147 resetTargetOptions(F);
148 I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this, isLittle);
153 void AArch64leTargetMachine::anchor() { }
155 AArch64leTargetMachine::
156 AArch64leTargetMachine(const Target &T, StringRef TT,
157 StringRef CPU, StringRef FS, const TargetOptions &Options,
158 Reloc::Model RM, CodeModel::Model CM,
159 CodeGenOpt::Level OL)
160 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
162 void AArch64beTargetMachine::anchor() { }
164 AArch64beTargetMachine::
165 AArch64beTargetMachine(const Target &T, StringRef TT,
166 StringRef CPU, StringRef FS, const TargetOptions &Options,
167 Reloc::Model RM, CodeModel::Model CM,
168 CodeGenOpt::Level OL)
169 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
172 /// AArch64 Code Generator Pass Configuration Options.
173 class AArch64PassConfig : public TargetPassConfig {
175 AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
176 : TargetPassConfig(TM, PM) {
177 if (TM->getOptLevel() != CodeGenOpt::None)
178 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
181 AArch64TargetMachine &getAArch64TargetMachine() const {
182 return getTM<AArch64TargetMachine>();
185 void addIRPasses() override;
186 bool addPreISel() override;
187 bool addInstSelector() override;
188 bool addILPOpts() override;
189 void addPreRegAlloc() override;
190 void addPostRegAlloc() override;
191 void addPreSched2() override;
192 void addPreEmitPass() override;
196 TargetIRAnalysis AArch64TargetMachine::getTargetIRAnalysis() {
197 return TargetIRAnalysis([this](Function &F) {
198 return TargetTransformInfo(AArch64TTIImpl(this, F));
202 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
203 return new AArch64PassConfig(this, PM);
206 void AArch64PassConfig::addIRPasses() {
207 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
209 addPass(createAtomicExpandPass(TM));
211 // Cmpxchg instructions are often used with a subsequent comparison to
212 // determine whether it succeeded. We can exploit existing control-flow in
213 // ldrex/strex loops to simplify this, but it needs tidying up.
214 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
215 addPass(createCFGSimplificationPass());
217 TargetPassConfig::addIRPasses();
219 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
220 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
221 // and lower a GEP with multiple indices to either arithmetic operations or
222 // multiple GEPs with single index.
223 addPass(createSeparateConstOffsetFromGEPPass(TM, true));
224 // Call EarlyCSE pass to find and remove subexpressions in the lowered
226 addPass(createEarlyCSEPass());
227 // Do loop invariant code motion in case part of the lowered result is
229 addPass(createLICMPass());
233 // Pass Pipeline Configuration
234 bool AArch64PassConfig::addPreISel() {
235 // Run promote constant before global merge, so that the promoted constants
236 // get a chance to be merged
237 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
238 addPass(createAArch64PromoteConstantPass());
239 if (TM->getOptLevel() != CodeGenOpt::None)
240 addPass(createGlobalMergePass(TM));
241 if (TM->getOptLevel() != CodeGenOpt::None)
242 addPass(createAArch64AddressTypePromotionPass());
247 bool AArch64PassConfig::addInstSelector() {
248 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
250 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
251 // references to _TLS_MODULE_BASE_ as possible.
252 if (Triple(TM->getTargetTriple()).isOSBinFormatELF() &&
253 getOptLevel() != CodeGenOpt::None)
254 addPass(createAArch64CleanupLocalDynamicTLSPass());
259 bool AArch64PassConfig::addILPOpts() {
261 addPass(createAArch64ConditionOptimizerPass());
263 addPass(createAArch64ConditionalCompares());
265 addPass(&MachineCombinerID);
266 if (EnableEarlyIfConversion)
267 addPass(&EarlyIfConverterID);
268 if (EnableStPairSuppress)
269 addPass(createAArch64StorePairSuppressPass());
273 void AArch64PassConfig::addPreRegAlloc() {
274 // Use AdvSIMD scalar instructions whenever profitable.
275 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
276 addPass(createAArch64AdvSIMDScalar());
277 // The AdvSIMD pass may produce copies that can be rewritten to
278 // be register coaleascer friendly.
279 addPass(&PeepholeOptimizerID);
283 void AArch64PassConfig::addPostRegAlloc() {
284 // Change dead register definitions to refer to the zero register.
285 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
286 addPass(createAArch64DeadRegisterDefinitions());
287 if (TM->getOptLevel() != CodeGenOpt::None &&
288 (TM->getSubtarget<AArch64Subtarget>().isCortexA53() ||
289 TM->getSubtarget<AArch64Subtarget>().isCortexA57()) &&
290 usingDefaultRegAlloc())
291 // Improve performance for some FP/SIMD code for A57.
292 addPass(createAArch64A57FPLoadBalancing());
295 void AArch64PassConfig::addPreSched2() {
296 // Expand some pseudo instructions to allow proper scheduling.
297 addPass(createAArch64ExpandPseudoPass());
298 // Use load/store pair instructions when possible.
299 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
300 addPass(createAArch64LoadStoreOptimizationPass());
303 void AArch64PassConfig::addPreEmitPass() {
304 if (EnableA53Fix835769)
305 addPass(createAArch64A53Fix835769());
306 // Relax conditional branch instructions if they're otherwise out of
307 // range of their destination.
308 addPass(createAArch64BranchRelaxation());
309 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
310 Triple(TM->getTargetTriple()).isOSBinFormatMachO())
311 addPass(createAArch64CollectLOHPass());