1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "AArch64TargetMachine.h"
15 #include "AArch64TargetObjectFile.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/CodeGen/RegAllocRegistry.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/PassManager.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/Transforms/Scalar.h"
27 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
28 cl::init(true), cl::Hidden);
30 static cl::opt<bool> EnableMCR("aarch64-mcr",
31 cl::desc("Enable the machine combiner pass"),
32 cl::init(true), cl::Hidden);
35 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
36 cl::init(true), cl::Hidden);
39 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
40 " integer instructions"), cl::init(false), cl::Hidden);
43 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
44 "constant pass"), cl::init(true), cl::Hidden);
47 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
48 " linker optimization hints (LOH)"), cl::init(true),
52 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
53 cl::desc("Enable the pass that removes dead"
54 " definitons and replaces stores to"
55 " them with stores to the zero"
60 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
61 " optimization pass"), cl::init(true), cl::Hidden);
64 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
65 cl::desc("Run SimplifyCFG after expanding atomic operations"
66 " to make use of cmpxchg flow-based information"),
70 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
71 cl::desc("Run early if-conversion"),
75 EnableCondOpt("aarch64-condopt",
76 cl::desc("Enable the condition optimizer pass"),
77 cl::init(true), cl::Hidden);
80 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
81 cl::desc("Work around Cortex-A53 erratum 835769"),
85 EnableGEPOpt("aarch64-gep-opt", cl::Hidden,
86 cl::desc("Enable optimizations on complex GEPs"),
89 extern "C" void LLVMInitializeAArch64Target() {
90 // Register the target.
91 RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
92 RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
93 RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
96 //===----------------------------------------------------------------------===//
97 // AArch64 Lowering public interface.
98 //===----------------------------------------------------------------------===//
99 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
100 if (TT.isOSBinFormatMachO())
101 return make_unique<AArch64_MachoTargetObjectFile>();
103 return make_unique<AArch64_ELFTargetObjectFile>();
106 /// TargetMachine ctor - Create an AArch64 architecture model.
108 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
109 StringRef CPU, StringRef FS,
110 const TargetOptions &Options,
111 Reloc::Model RM, CodeModel::Model CM,
112 CodeGenOpt::Level OL,
114 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
115 TLOF(createTLOF(Triple(getTargetTriple()))),
116 Subtarget(TT, CPU, FS, *this, LittleEndian), isLittle(LittleEndian) {
120 const AArch64Subtarget *
121 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
122 AttributeSet FnAttrs = F.getAttributes();
124 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
126 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
128 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
129 ? CPUAttr.getValueAsString().str()
131 std::string FS = !FSAttr.hasAttribute(Attribute::None)
132 ? FSAttr.getValueAsString().str()
135 auto &I = SubtargetMap[CPU + FS];
137 // This needs to be done before we create a new subtarget since any
138 // creation will depend on the TM and the code generation flags on the
139 // function that reside in TargetOptions.
140 resetTargetOptions(F);
141 I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this, isLittle);
146 void AArch64leTargetMachine::anchor() { }
148 AArch64leTargetMachine::
149 AArch64leTargetMachine(const Target &T, StringRef TT,
150 StringRef CPU, StringRef FS, const TargetOptions &Options,
151 Reloc::Model RM, CodeModel::Model CM,
152 CodeGenOpt::Level OL)
153 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
155 void AArch64beTargetMachine::anchor() { }
157 AArch64beTargetMachine::
158 AArch64beTargetMachine(const Target &T, StringRef TT,
159 StringRef CPU, StringRef FS, const TargetOptions &Options,
160 Reloc::Model RM, CodeModel::Model CM,
161 CodeGenOpt::Level OL)
162 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
165 /// AArch64 Code Generator Pass Configuration Options.
166 class AArch64PassConfig : public TargetPassConfig {
168 AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
169 : TargetPassConfig(TM, PM) {
170 if (TM->getOptLevel() != CodeGenOpt::None)
171 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
174 AArch64TargetMachine &getAArch64TargetMachine() const {
175 return getTM<AArch64TargetMachine>();
178 void addIRPasses() override;
179 bool addPreISel() override;
180 bool addInstSelector() override;
181 bool addILPOpts() override;
182 bool addPreRegAlloc() override;
183 bool addPostRegAlloc() override;
184 bool addPreSched2() override;
185 bool addPreEmitPass() override;
189 void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
190 // Add first the target-independent BasicTTI pass, then our AArch64 pass. This
191 // allows the AArch64 pass to delegate to the target independent layer when
193 PM.add(createBasicTargetTransformInfoPass(this));
194 PM.add(createAArch64TargetTransformInfoPass(this));
197 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
198 return new AArch64PassConfig(this, PM);
201 void AArch64PassConfig::addIRPasses() {
202 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
204 addPass(createAtomicExpandPass(TM));
206 // Cmpxchg instructions are often used with a subsequent comparison to
207 // determine whether it succeeded. We can exploit existing control-flow in
208 // ldrex/strex loops to simplify this, but it needs tidying up.
209 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
210 addPass(createCFGSimplificationPass());
212 TargetPassConfig::addIRPasses();
214 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
215 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
216 // and lower a GEP with multiple indices to either arithmetic operations or
217 // multiple GEPs with single index.
218 addPass(createSeparateConstOffsetFromGEPPass(TM, true));
219 // Call EarlyCSE pass to find and remove subexpressions in the lowered
221 addPass(createEarlyCSEPass());
222 // Do loop invariant code motion in case part of the lowered result is
224 addPass(createLICMPass());
228 // Pass Pipeline Configuration
229 bool AArch64PassConfig::addPreISel() {
230 // Run promote constant before global merge, so that the promoted constants
231 // get a chance to be merged
232 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
233 addPass(createAArch64PromoteConstantPass());
234 if (TM->getOptLevel() != CodeGenOpt::None)
235 addPass(createGlobalMergePass(TM));
236 if (TM->getOptLevel() != CodeGenOpt::None)
237 addPass(createAArch64AddressTypePromotionPass());
242 bool AArch64PassConfig::addInstSelector() {
243 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
245 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
246 // references to _TLS_MODULE_BASE_ as possible.
247 if (TM->getSubtarget<AArch64Subtarget>().isTargetELF() &&
248 getOptLevel() != CodeGenOpt::None)
249 addPass(createAArch64CleanupLocalDynamicTLSPass());
254 bool AArch64PassConfig::addILPOpts() {
256 addPass(createAArch64ConditionOptimizerPass());
258 addPass(createAArch64ConditionalCompares());
260 addPass(&MachineCombinerID);
261 if (EnableEarlyIfConversion)
262 addPass(&EarlyIfConverterID);
263 if (EnableStPairSuppress)
264 addPass(createAArch64StorePairSuppressPass());
268 bool AArch64PassConfig::addPreRegAlloc() {
269 // Use AdvSIMD scalar instructions whenever profitable.
270 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
271 addPass(createAArch64AdvSIMDScalar());
272 // The AdvSIMD pass may produce copies that can be rewritten to
273 // be register coaleascer friendly.
274 addPass(&PeepholeOptimizerID);
279 bool AArch64PassConfig::addPostRegAlloc() {
280 // Change dead register definitions to refer to the zero register.
281 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
282 addPass(createAArch64DeadRegisterDefinitions());
283 if (TM->getOptLevel() != CodeGenOpt::None &&
284 (TM->getSubtarget<AArch64Subtarget>().isCortexA53() ||
285 TM->getSubtarget<AArch64Subtarget>().isCortexA57()) &&
286 usingDefaultRegAlloc())
287 // Improve performance for some FP/SIMD code for A57.
288 addPass(createAArch64A57FPLoadBalancing());
292 bool AArch64PassConfig::addPreSched2() {
293 // Expand some pseudo instructions to allow proper scheduling.
294 addPass(createAArch64ExpandPseudoPass());
295 // Use load/store pair instructions when possible.
296 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
297 addPass(createAArch64LoadStoreOptimizationPass());
301 bool AArch64PassConfig::addPreEmitPass() {
302 if (EnableA53Fix835769)
303 addPass(createAArch64A53Fix835769());
304 // Relax conditional branch instructions if they're otherwise out of
305 // range of their destination.
306 addPass(createAArch64BranchRelaxation());
307 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
308 TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
309 addPass(createAArch64CollectLOHPass());