1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "AArch64TargetMachine.h"
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Support/TargetRegistry.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/Transforms/Scalar.h"
24 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
25 cl::init(true), cl::Hidden);
27 static cl::opt<bool> EnableMCR("aarch64-mcr",
28 cl::desc("Enable the machine combiner pass"),
29 cl::init(true), cl::Hidden);
32 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
33 cl::init(true), cl::Hidden);
36 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
37 " integer instructions"), cl::init(false), cl::Hidden);
40 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
41 "constant pass"), cl::init(true), cl::Hidden);
44 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
45 " linker optimization hints (LOH)"), cl::init(true),
49 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
50 cl::desc("Enable the pass that removes dead"
51 " definitons and replaces stores to"
52 " them with stores to the zero"
57 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
58 " optimization pass"), cl::init(true), cl::Hidden);
61 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
62 cl::desc("Run SimplifyCFG after expanding atomic operations"
63 " to make use of cmpxchg flow-based information"),
66 extern "C" void LLVMInitializeAArch64Target() {
67 // Register the target.
68 RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
69 RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
70 RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
73 /// TargetMachine ctor - Create an AArch64 architecture model.
75 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
76 StringRef CPU, StringRef FS,
77 const TargetOptions &Options,
78 Reloc::Model RM, CodeModel::Model CM,
81 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
82 Subtarget(TT, CPU, FS, *this, LittleEndian) {
86 void AArch64leTargetMachine::anchor() { }
88 AArch64leTargetMachine::
89 AArch64leTargetMachine(const Target &T, StringRef TT,
90 StringRef CPU, StringRef FS, const TargetOptions &Options,
91 Reloc::Model RM, CodeModel::Model CM,
93 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
95 void AArch64beTargetMachine::anchor() { }
97 AArch64beTargetMachine::
98 AArch64beTargetMachine(const Target &T, StringRef TT,
99 StringRef CPU, StringRef FS, const TargetOptions &Options,
100 Reloc::Model RM, CodeModel::Model CM,
101 CodeGenOpt::Level OL)
102 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
105 /// AArch64 Code Generator Pass Configuration Options.
106 class AArch64PassConfig : public TargetPassConfig {
108 AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
109 : TargetPassConfig(TM, PM) {}
111 AArch64TargetMachine &getAArch64TargetMachine() const {
112 return getTM<AArch64TargetMachine>();
115 void addIRPasses() override;
116 bool addPreISel() override;
117 bool addInstSelector() override;
118 bool addILPOpts() override;
119 bool addPreRegAlloc() override;
120 bool addPostRegAlloc() override;
121 bool addPreSched2() override;
122 bool addPreEmitPass() override;
126 void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
127 // Add first the target-independent BasicTTI pass, then our AArch64 pass. This
128 // allows the AArch64 pass to delegate to the target independent layer when
130 PM.add(createBasicTargetTransformInfoPass(this));
131 PM.add(createAArch64TargetTransformInfoPass(this));
134 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
135 return new AArch64PassConfig(this, PM);
138 void AArch64PassConfig::addIRPasses() {
139 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
141 addPass(createAtomicExpandLoadLinkedPass(TM));
143 // Cmpxchg instructions are often used with a subsequent comparison to
144 // determine whether it succeeded. We can exploit existing control-flow in
145 // ldrex/strex loops to simplify this, but it needs tidying up.
146 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
147 addPass(createCFGSimplificationPass());
149 TargetPassConfig::addIRPasses();
152 // Pass Pipeline Configuration
153 bool AArch64PassConfig::addPreISel() {
154 // Run promote constant before global merge, so that the promoted constants
155 // get a chance to be merged
156 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
157 addPass(createAArch64PromoteConstantPass());
158 if (TM->getOptLevel() != CodeGenOpt::None)
159 addPass(createGlobalMergePass(TM));
160 if (TM->getOptLevel() != CodeGenOpt::None)
161 addPass(createAArch64AddressTypePromotionPass());
166 bool AArch64PassConfig::addInstSelector() {
167 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
169 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
170 // references to _TLS_MODULE_BASE_ as possible.
171 if (TM->getSubtarget<AArch64Subtarget>().isTargetELF() &&
172 getOptLevel() != CodeGenOpt::None)
173 addPass(createAArch64CleanupLocalDynamicTLSPass());
178 bool AArch64PassConfig::addILPOpts() {
180 addPass(createAArch64ConditionalCompares());
182 addPass(&MachineCombinerID);
183 addPass(&EarlyIfConverterID);
184 if (EnableStPairSuppress)
185 addPass(createAArch64StorePairSuppressPass());
189 bool AArch64PassConfig::addPreRegAlloc() {
190 // Use AdvSIMD scalar instructions whenever profitable.
191 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar)
192 addPass(createAArch64AdvSIMDScalar());
196 bool AArch64PassConfig::addPostRegAlloc() {
197 // Change dead register definitions to refer to the zero register.
198 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
199 addPass(createAArch64DeadRegisterDefinitions());
203 bool AArch64PassConfig::addPreSched2() {
204 // Expand some pseudo instructions to allow proper scheduling.
205 addPass(createAArch64ExpandPseudoPass());
206 // Use load/store pair instructions when possible.
207 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
208 addPass(createAArch64LoadStoreOptimizationPass());
212 bool AArch64PassConfig::addPreEmitPass() {
213 // Relax conditional branch instructions if they're otherwise out of
214 // range of their destination.
215 addPass(createAArch64BranchRelaxation());
216 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
217 TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
218 addPass(createAArch64CollectLOHPass());