1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "AArch64TargetMachine.h"
15 #include "AArch64TargetObjectFile.h"
16 #include "AArch64TargetTransformInfo.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/RegAllocRegistry.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/TargetRegistry.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/Transforms/Scalar.h"
28 EnableCCMP("aarch64-ccmp", cl::desc("Enable the CCMP formation pass"),
29 cl::init(true), cl::Hidden);
31 static cl::opt<bool> EnableMCR("aarch64-mcr",
32 cl::desc("Enable the machine combiner pass"),
33 cl::init(true), cl::Hidden);
36 EnableStPairSuppress("aarch64-stp-suppress", cl::desc("Suppress STP for AArch64"),
37 cl::init(true), cl::Hidden);
40 EnableAdvSIMDScalar("aarch64-simd-scalar", cl::desc("Enable use of AdvSIMD scalar"
41 " integer instructions"), cl::init(false), cl::Hidden);
44 EnablePromoteConstant("aarch64-promote-const", cl::desc("Enable the promote "
45 "constant pass"), cl::init(true), cl::Hidden);
48 EnableCollectLOH("aarch64-collect-loh", cl::desc("Enable the pass that emits the"
49 " linker optimization hints (LOH)"), cl::init(true),
53 EnableDeadRegisterElimination("aarch64-dead-def-elimination", cl::Hidden,
54 cl::desc("Enable the pass that removes dead"
55 " definitons and replaces stores to"
56 " them with stores to the zero"
61 EnableLoadStoreOpt("aarch64-load-store-opt", cl::desc("Enable the load/store pair"
62 " optimization pass"), cl::init(true), cl::Hidden);
65 EnableAtomicTidy("aarch64-atomic-cfg-tidy", cl::Hidden,
66 cl::desc("Run SimplifyCFG after expanding atomic operations"
67 " to make use of cmpxchg flow-based information"),
71 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
72 cl::desc("Run early if-conversion"),
76 EnableCondOpt("aarch64-condopt",
77 cl::desc("Enable the condition optimizer pass"),
78 cl::init(true), cl::Hidden);
81 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
82 cl::desc("Work around Cortex-A53 erratum 835769"),
86 EnableGEPOpt("aarch64-gep-opt", cl::Hidden,
87 cl::desc("Enable optimizations on complex GEPs"),
90 extern "C" void LLVMInitializeAArch64Target() {
91 // Register the target.
92 RegisterTargetMachine<AArch64leTargetMachine> X(TheAArch64leTarget);
93 RegisterTargetMachine<AArch64beTargetMachine> Y(TheAArch64beTarget);
94 RegisterTargetMachine<AArch64leTargetMachine> Z(TheARM64Target);
97 //===----------------------------------------------------------------------===//
98 // AArch64 Lowering public interface.
99 //===----------------------------------------------------------------------===//
100 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
101 if (TT.isOSBinFormatMachO())
102 return make_unique<AArch64_MachoTargetObjectFile>();
104 return make_unique<AArch64_ELFTargetObjectFile>();
107 // Helper function to build a DataLayout string
108 static std::string computeDataLayout(StringRef TT, bool LittleEndian) {
110 if (Triple.isOSBinFormatMachO())
111 return "e-m:o-i64:64-i128:128-n32:64-S128";
113 return "e-m:e-i64:64-i128:128-n32:64-S128";
114 return "E-m:e-i64:64-i128:128-n32:64-S128";
117 /// TargetMachine ctor - Create an AArch64 architecture model.
119 AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
120 StringRef CPU, StringRef FS,
121 const TargetOptions &Options,
122 Reloc::Model RM, CodeModel::Model CM,
123 CodeGenOpt::Level OL,
125 // This nested ternary is horrible, but DL needs to be properly
127 // before TLInfo is constructed.
128 : LLVMTargetMachine(T, computeDataLayout(TT, LittleEndian), TT, CPU, FS,
129 Options, RM, CM, OL),
130 TLOF(createTLOF(Triple(getTargetTriple()))),
131 Subtarget(TT, CPU, FS, *this, LittleEndian),
132 isLittle(LittleEndian) {
136 AArch64TargetMachine::~AArch64TargetMachine() {}
138 const AArch64Subtarget *
139 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
140 Attribute CPUAttr = F.getFnAttribute("target-cpu");
141 Attribute FSAttr = F.getFnAttribute("target-features");
143 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
144 ? CPUAttr.getValueAsString().str()
146 std::string FS = !FSAttr.hasAttribute(Attribute::None)
147 ? FSAttr.getValueAsString().str()
150 auto &I = SubtargetMap[CPU + FS];
152 // This needs to be done before we create a new subtarget since any
153 // creation will depend on the TM and the code generation flags on the
154 // function that reside in TargetOptions.
155 resetTargetOptions(F);
156 I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this, isLittle);
161 void AArch64leTargetMachine::anchor() { }
163 AArch64leTargetMachine::
164 AArch64leTargetMachine(const Target &T, StringRef TT,
165 StringRef CPU, StringRef FS, const TargetOptions &Options,
166 Reloc::Model RM, CodeModel::Model CM,
167 CodeGenOpt::Level OL)
168 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
170 void AArch64beTargetMachine::anchor() { }
172 AArch64beTargetMachine::
173 AArch64beTargetMachine(const Target &T, StringRef TT,
174 StringRef CPU, StringRef FS, const TargetOptions &Options,
175 Reloc::Model RM, CodeModel::Model CM,
176 CodeGenOpt::Level OL)
177 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
180 /// AArch64 Code Generator Pass Configuration Options.
181 class AArch64PassConfig : public TargetPassConfig {
183 AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
184 : TargetPassConfig(TM, PM) {
185 if (TM->getOptLevel() != CodeGenOpt::None)
186 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
189 AArch64TargetMachine &getAArch64TargetMachine() const {
190 return getTM<AArch64TargetMachine>();
193 void addIRPasses() override;
194 bool addPreISel() override;
195 bool addInstSelector() override;
196 bool addILPOpts() override;
197 void addPreRegAlloc() override;
198 void addPostRegAlloc() override;
199 void addPreSched2() override;
200 void addPreEmitPass() override;
204 TargetIRAnalysis AArch64TargetMachine::getTargetIRAnalysis() {
205 return TargetIRAnalysis([this](Function &F) {
206 return TargetTransformInfo(AArch64TTIImpl(this, F));
210 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
211 return new AArch64PassConfig(this, PM);
214 void AArch64PassConfig::addIRPasses() {
215 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
217 addPass(createAtomicExpandPass(TM));
219 // Cmpxchg instructions are often used with a subsequent comparison to
220 // determine whether it succeeded. We can exploit existing control-flow in
221 // ldrex/strex loops to simplify this, but it needs tidying up.
222 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
223 addPass(createCFGSimplificationPass());
225 TargetPassConfig::addIRPasses();
227 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
228 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
229 // and lower a GEP with multiple indices to either arithmetic operations or
230 // multiple GEPs with single index.
231 addPass(createSeparateConstOffsetFromGEPPass(TM, true));
232 // Call EarlyCSE pass to find and remove subexpressions in the lowered
234 addPass(createEarlyCSEPass());
235 // Do loop invariant code motion in case part of the lowered result is
237 addPass(createLICMPass());
241 // Pass Pipeline Configuration
242 bool AArch64PassConfig::addPreISel() {
243 // Run promote constant before global merge, so that the promoted constants
244 // get a chance to be merged
245 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
246 addPass(createAArch64PromoteConstantPass());
247 // FIXME: On AArch64, this depends on the type.
248 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
249 // and the offset has to be a multiple of the related size in bytes.
250 if (TM->getOptLevel() != CodeGenOpt::None)
251 addPass(createGlobalMergePass(TM, 4095));
252 if (TM->getOptLevel() != CodeGenOpt::None)
253 addPass(createAArch64AddressTypePromotionPass());
258 bool AArch64PassConfig::addInstSelector() {
259 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
261 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
262 // references to _TLS_MODULE_BASE_ as possible.
263 if (Triple(TM->getTargetTriple()).isOSBinFormatELF() &&
264 getOptLevel() != CodeGenOpt::None)
265 addPass(createAArch64CleanupLocalDynamicTLSPass());
270 bool AArch64PassConfig::addILPOpts() {
272 addPass(createAArch64ConditionOptimizerPass());
274 addPass(createAArch64ConditionalCompares());
276 addPass(&MachineCombinerID);
277 if (EnableEarlyIfConversion)
278 addPass(&EarlyIfConverterID);
279 if (EnableStPairSuppress)
280 addPass(createAArch64StorePairSuppressPass());
284 void AArch64PassConfig::addPreRegAlloc() {
285 // Use AdvSIMD scalar instructions whenever profitable.
286 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
287 addPass(createAArch64AdvSIMDScalar());
288 // The AdvSIMD pass may produce copies that can be rewritten to
289 // be register coaleascer friendly.
290 addPass(&PeepholeOptimizerID);
294 void AArch64PassConfig::addPostRegAlloc() {
295 // Change dead register definitions to refer to the zero register.
296 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
297 addPass(createAArch64DeadRegisterDefinitions());
298 if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
299 // Improve performance for some FP/SIMD code for A57.
300 addPass(createAArch64A57FPLoadBalancing());
303 void AArch64PassConfig::addPreSched2() {
304 // Expand some pseudo instructions to allow proper scheduling.
305 addPass(createAArch64ExpandPseudoPass());
306 // Use load/store pair instructions when possible.
307 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
308 addPass(createAArch64LoadStoreOptimizationPass());
311 void AArch64PassConfig::addPreEmitPass() {
312 if (EnableA53Fix835769)
313 addPass(createAArch64A53Fix835769());
314 // Relax conditional branch instructions if they're otherwise out of
315 // range of their destination.
316 addPass(createAArch64BranchRelaxation());
317 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
318 Triple(TM->getTargetTriple()).isOSBinFormatMachO())
319 addPass(createAArch64CollectLOHPass());