lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

   1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the functions necessary to decode AArch64 instruction
  11 // bitpatterns into MCInsts (with the help of TableGenerated information from
  12 // the instruction definitions).
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #define DEBUG_TYPE "arm-disassembler"
  17
  18 #include "AArch64.h"
  19 #include "AArch64RegisterInfo.h"
  20 #include "AArch64Subtarget.h"
  21 #include "Utils/AArch64BaseInfo.h"
  22 #include "llvm/MC/MCInst.h"
  23 #include "llvm/MC/MCInstrDesc.h"
  24 #include "llvm/MC/MCExpr.h"
  25 #include "llvm/MC/MCContext.h"
  26 #include "llvm/MC/MCDisassembler.h"
  27 #include "llvm/MC/MCFixedLenDisassembler.h"
  28 #include "llvm/Support/Debug.h"
  29 #include "llvm/Support/MemoryObject.h"
  30 #include "llvm/Support/ErrorHandling.h"
  31 #include "llvm/Support/TargetRegistry.h"
  32 #include "llvm/Support/raw_ostream.h"
  33
  34 using namespace llvm;
  35
  36 typedef MCDisassembler::DecodeStatus DecodeStatus;
  37
  38 namespace {
  39 /// AArch64 disassembler for all AArch64 platforms.
  40 class AArch64Disassembler : public MCDisassembler {
  41   OwningPtr<const MCRegisterInfo> RegInfo;
  42 public:
  43   /// Initializes the disassembler.
  44   ///
  45   AArch64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info)
  46     : MCDisassembler(STI), RegInfo(Info) {
  47   }
  48
  49   ~AArch64Disassembler() {}
  50
  51   /// See MCDisassembler.
  52   DecodeStatus getInstruction(MCInst &instr,
  53                               uint64_t &size,
  54                               const MemoryObject &region,
  55                               uint64_t address,
  56                               raw_ostream &vStream,
  57                               raw_ostream &cStream) const;
  58
  59   const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
  60 };
  61
  62 }
  63
  64 // Forward-declarations used in the auto-generated files.
  65 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  66                                          uint64_t Address, const void *Decoder);
  67 static DecodeStatus
  68 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  69                             uint64_t Address, const void *Decoder);
  70
  71 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  72                                          uint64_t Address, const void *Decoder);
  73 static DecodeStatus
  74 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  75                             uint64_t Address, const void *Decoder);
  76
  77 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  78                                          uint64_t Address, const void *Decoder);
  79 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  80                                          uint64_t Address, const void *Decoder);
  81 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  82                                          uint64_t Address, const void *Decoder);
  83 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  84                                          uint64_t Address, const void *Decoder);
  85 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
  86                                               unsigned RegNo, uint64_t Address,
  87                                               const void *Decoder);
  88 static DecodeStatus DecodeFPR128LoRegisterClass(llvm::MCInst &Inst,
  89                                                 unsigned RegNo, uint64_t Address,
  90                                                 const void *Decoder);
  91
  92 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
  93                                                unsigned OptionHiS,
  94                                                uint64_t Address,
  95                                                const void *Decoder);
  96
  97
  98 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
  99                                                unsigned Imm6Bits,
 100                                                uint64_t Address,
 101                                                const void *Decoder);
 102
 103 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
 104                                                unsigned Imm6Bits,
 105                                                uint64_t Address,
 106                                                const void *Decoder);
 107
 108 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
 109                                         unsigned RmBits,
 110                                         uint64_t Address,
 111                                         const void *Decoder);
 112
 113 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val,
 114                                          uint64_t Address, const void *Decoder);
 115 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val,
 116                                           uint64_t Address,
 117                                           const void *Decoder);
 118 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val,
 119                                           uint64_t Address,
 120                                           const void *Decoder);
 121 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val,
 122                                           uint64_t Address,
 123                                           const void *Decoder);
 124
 125 template<int RegWidth>
 126 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
 127                                              unsigned FullImm,
 128                                              uint64_t Address,
 129                                              const void *Decoder);
 130
 131 template<int RegWidth>
 132 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
 133                                             unsigned Bits,
 134                                             uint64_t Address,
 135                                             const void *Decoder);
 136
 137 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
 138                                            unsigned ShiftAmount,
 139                                            uint64_t Address,
 140                                            const void *Decoder);
 141 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
 142 static DecodeStatus
 143 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
 144                              uint64_t Address, const void *Decoder);
 145
 146 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
 147                                             unsigned ShiftAmount,
 148                                             uint64_t Address,
 149                                             const void *Decoder);
 150 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
 151                                               uint64_t Address,
 152                                               const void *Decoder);
 153
 154 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 155                                               uint64_t Address,
 156                                               const void *Decoder);
 157
 158 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
 159                                               unsigned Insn,
 160                                               uint64_t Address,
 161                                               const void *Decoder);
 162
 163 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
 164                                                        unsigned Val,
 165                                                        uint64_t Address,
 166                                                        const void *Decoder);
 167
 168 template<typename SomeNamedImmMapper>
 169 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
 170                                           unsigned Val,
 171                                           uint64_t Address,
 172                                           const void *Decoder);
 173
 174 static DecodeStatus
 175 DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper,
 176                     llvm::MCInst &Inst, unsigned Val,
 177                     uint64_t Address, const void *Decoder);
 178
 179 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
 180                                      unsigned Val,
 181                                      uint64_t Address,
 182                                      const void *Decoder);
 183
 184 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
 185                                      unsigned Val,
 186                                      uint64_t Address,
 187                                      const void *Decoder);
 188
 189
 190 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
 191                                                    unsigned Val,
 192                                                    uint64_t Address,
 193                                                    const void *Decoder);
 194
 195
 196 static bool Check(DecodeStatus &Out, DecodeStatus In);
 197
 198 #include "AArch64GenDisassemblerTables.inc"
 199 #include "AArch64GenInstrInfo.inc"
 200
 201 static bool Check(DecodeStatus &Out, DecodeStatus In) {
 202   switch (In) {
 203     case MCDisassembler::Success:
 204       // Out stays the same.
 205       return true;
 206     case MCDisassembler::SoftFail:
 207       Out = In;
 208       return true;
 209     case MCDisassembler::Fail:
 210       Out = In;
 211       return false;
 212   }
 213   llvm_unreachable("Invalid DecodeStatus!");
 214 }
 215
 216 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
 217                                                  const MemoryObject &Region,
 218                                                  uint64_t Address,
 219                                                  raw_ostream &os,
 220                                                  raw_ostream &cs) const {
 221   CommentStream = &cs;
 222
 223   uint8_t bytes[4];
 224
 225   // We want to read exactly 4 bytes of data.
 226   if (Region.readBytes(Address, 4, bytes) == -1) {
 227     Size = 0;
 228     return MCDisassembler::Fail;
 229   }
 230
 231   // Encoded as a small-endian 32-bit word in the stream.
 232   uint32_t insn = (bytes[3] << 24) |
 233     (bytes[2] << 16) |
 234     (bytes[1] <<  8) |
 235     (bytes[0] <<  0);
 236
 237   // Calling the auto-generated decoder function.
 238   DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address,
 239                                           this, STI);
 240   if (result != MCDisassembler::Fail) {
 241     Size = 4;
 242     return result;
 243   }
 244
 245   MI.clear();
 246   Size = 0;
 247   return MCDisassembler::Fail;
 248 }
 249
 250 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 251   const AArch64Disassembler *Dis = static_cast<const AArch64Disassembler*>(D);
 252   return Dis->getRegInfo()->getRegClass(RC).getRegister(RegNo);
 253 }
 254
 255 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 256                                         uint64_t Address, const void *Decoder) {
 257   if (RegNo > 31)
 258     return MCDisassembler::Fail;
 259
 260   uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo);
 261   Inst.addOperand(MCOperand::CreateReg(Register));
 262   return MCDisassembler::Success;
 263 }
 264
 265 static DecodeStatus
 266 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 267                             uint64_t Address, const void *Decoder) {
 268   if (RegNo > 31)
 269     return MCDisassembler::Fail;
 270
 271   uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo);
 272   Inst.addOperand(MCOperand::CreateReg(Register));
 273   return MCDisassembler::Success;
 274 }
 275
 276 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 277                                              uint64_t Address,
 278                                              const void *Decoder) {
 279   if (RegNo > 31)
 280     return MCDisassembler::Fail;
 281
 282   uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo);
 283   Inst.addOperand(MCOperand::CreateReg(Register));
 284   return MCDisassembler::Success;
 285 }
 286
 287 static DecodeStatus
 288 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 289                             uint64_t Address, const void *Decoder) {
 290   if (RegNo > 31)
 291     return MCDisassembler::Fail;
 292
 293   uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo);
 294   Inst.addOperand(MCOperand::CreateReg(Register));
 295   return MCDisassembler::Success;
 296 }
 297
 298 static DecodeStatus
 299 DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 300                             uint64_t Address, const void *Decoder) {
 301   if (RegNo > 31)
 302     return MCDisassembler::Fail;
 303
 304   uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo);
 305   Inst.addOperand(MCOperand::CreateReg(Register));
 306   return MCDisassembler::Success;
 307 }
 308
 309 static DecodeStatus
 310 DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 311                             uint64_t Address, const void *Decoder) {
 312   if (RegNo > 31)
 313     return MCDisassembler::Fail;
 314
 315   uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo);
 316   Inst.addOperand(MCOperand::CreateReg(Register));
 317   return MCDisassembler::Success;
 318 }
 319
 320
 321 static DecodeStatus
 322 DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 323                             uint64_t Address, const void *Decoder) {
 324   if (RegNo > 31)
 325     return MCDisassembler::Fail;
 326
 327   uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo);
 328   Inst.addOperand(MCOperand::CreateReg(Register));
 329   return MCDisassembler::Success;
 330 }
 331
 332 static DecodeStatus
 333 DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 334                             uint64_t Address, const void *Decoder) {
 335   if (RegNo > 31)
 336     return MCDisassembler::Fail;
 337
 338   uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo);
 339   Inst.addOperand(MCOperand::CreateReg(Register));
 340   return MCDisassembler::Success;
 341 }
 342
 343
 344 static DecodeStatus
 345 DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 346                             uint64_t Address, const void *Decoder) {
 347   if (RegNo > 31)
 348     return MCDisassembler::Fail;
 349
 350   uint16_t Register = getReg(Decoder, AArch64::FPR128RegClassID, RegNo);
 351   Inst.addOperand(MCOperand::CreateReg(Register));
 352   return MCDisassembler::Success;
 353 }
 354
 355 static DecodeStatus
 356 DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 357                             uint64_t Address, const void *Decoder) {
 358   if (RegNo > 15)
 359     return MCDisassembler::Fail;
 360
 361   return DecodeFPR128RegisterClass(Inst, RegNo, Address, Decoder);
 362 }
 363
 364 static DecodeStatus DecodeRegisterClassByID(llvm::MCInst &Inst, unsigned RegNo,
 365                                             unsigned RegID,
 366                                             const void *Decoder) {
 367   if (RegNo > 31)
 368     return MCDisassembler::Fail;
 369
 370   uint16_t Register = getReg(Decoder, RegID, RegNo);
 371   Inst.addOperand(MCOperand::CreateReg(Register));
 372   return MCDisassembler::Success;
 373 }
 374
 375 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 376                                              uint64_t Address,
 377                                              const void *Decoder) {
 378   return DecodeRegisterClassByID(Inst, RegNo, AArch64::DPairRegClassID,
 379                                  Decoder);
 380 }
 381
 382 static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 383                                              uint64_t Address,
 384                                              const void *Decoder) {
 385   return DecodeRegisterClassByID(Inst, RegNo, AArch64::QPairRegClassID,
 386                                  Decoder);
 387 }
 388
 389 static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst,
 390                                                unsigned RegNo, uint64_t Address,
 391                                                const void *Decoder) {
 392   return DecodeRegisterClassByID(Inst, RegNo, AArch64::DTripleRegClassID,
 393                                  Decoder);
 394 }
 395
 396 static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst,
 397                                                unsigned RegNo, uint64_t Address,
 398                                                const void *Decoder) {
 399   return DecodeRegisterClassByID(Inst, RegNo, AArch64::QTripleRegClassID,
 400                                  Decoder);
 401 }
 402
 403 static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 404                                              uint64_t Address,
 405                                              const void *Decoder) {
 406   return DecodeRegisterClassByID(Inst, RegNo, AArch64::DQuadRegClassID,
 407                                  Decoder);
 408 }
 409
 410 static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 411                                              uint64_t Address,
 412                                              const void *Decoder) {
 413   return DecodeRegisterClassByID(Inst, RegNo, AArch64::QQuadRegClassID,
 414                                  Decoder);
 415 }
 416
 417 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
 418                                                unsigned OptionHiS,
 419                                                uint64_t Address,
 420                                                const void *Decoder) {
 421   // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1},
 422   // S}. Hence we want to check bit 1.
 423   if (!(OptionHiS & 2))
 424     return MCDisassembler::Fail;
 425
 426   Inst.addOperand(MCOperand::CreateImm(OptionHiS));
 427   return MCDisassembler::Success;
 428 }
 429
 430 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
 431                                                unsigned Imm6Bits,
 432                                                uint64_t Address,
 433                                                const void *Decoder) {
 434   // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be
 435   // between 0 and 31.
 436   if (Imm6Bits > 31)
 437     return MCDisassembler::Fail;
 438
 439   Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
 440   return MCDisassembler::Success;
 441 }
 442
 443 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
 444                                                unsigned Imm6Bits,
 445                                                uint64_t Address,
 446                                                const void *Decoder) {
 447   // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32.
 448   if (Imm6Bits < 32)
 449     return MCDisassembler::Fail;
 450
 451   Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
 452   return MCDisassembler::Success;
 453 }
 454
 455 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
 456                                         unsigned RmBits,
 457                                         uint64_t Address,
 458                                         const void *Decoder) {
 459   // Any bits are valid in the instruction (they're architecturally ignored),
 460   // but a code generator should insert 0.
 461   Inst.addOperand(MCOperand::CreateImm(0));
 462   return MCDisassembler::Success;
 463 }
 464
 465 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val,
 466                                          uint64_t Address,
 467                                          const void *Decoder) {
 468   Inst.addOperand(MCOperand::CreateImm(8 - Val));
 469   return MCDisassembler::Success;
 470 }
 471
 472 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val,
 473                                           uint64_t Address,
 474                                           const void *Decoder) {
 475   Inst.addOperand(MCOperand::CreateImm(16 - Val));
 476   return MCDisassembler::Success;
 477 }
 478
 479 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val,
 480                                           uint64_t Address,
 481                                           const void *Decoder) {
 482   Inst.addOperand(MCOperand::CreateImm(32 - Val));
 483   return MCDisassembler::Success;
 484 }
 485
 486 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val,
 487                                           uint64_t Address,
 488                                           const void *Decoder) {
 489   Inst.addOperand(MCOperand::CreateImm(64 - Val));
 490   return MCDisassembler::Success;
 491 }
 492
 493 template<int RegWidth>
 494 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
 495                                              unsigned FullImm,
 496                                              uint64_t Address,
 497                                              const void *Decoder) {
 498   unsigned Imm16 = FullImm & 0xffff;
 499   unsigned Shift = FullImm >> 16;
 500
 501   if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail;
 502
 503   Inst.addOperand(MCOperand::CreateImm(Imm16));
 504   Inst.addOperand(MCOperand::CreateImm(Shift));
 505   return MCDisassembler::Success;
 506 }
 507
 508 template<int RegWidth>
 509 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
 510                                             unsigned Bits,
 511                                             uint64_t Address,
 512                                             const void *Decoder) {
 513   uint64_t Imm;
 514   if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm))
 515     return MCDisassembler::Fail;
 516
 517   Inst.addOperand(MCOperand::CreateImm(Bits));
 518   return MCDisassembler::Success;
 519 }
 520
 521
 522 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
 523                                            unsigned ShiftAmount,
 524                                            uint64_t Address,
 525                                            const void *Decoder) {
 526   // Only values 0-4 are valid for this 3-bit field
 527   if (ShiftAmount > 4)
 528     return MCDisassembler::Fail;
 529
 530   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 531   return MCDisassembler::Success;
 532 }
 533
 534 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
 535                                             unsigned ShiftAmount,
 536                                             uint64_t Address,
 537                                             const void *Decoder) {
 538   // Only values below 32 are valid for a 32-bit register
 539   if (ShiftAmount > 31)
 540     return MCDisassembler::Fail;
 541
 542   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 543   return MCDisassembler::Success;
 544 }
 545
 546 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
 547                                               uint64_t Address,
 548                                               const void *Decoder) {
 549   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 550   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 551   unsigned ImmS = fieldFromInstruction(Insn, 10, 6);
 552   unsigned ImmR = fieldFromInstruction(Insn, 16, 6);
 553   unsigned SF = fieldFromInstruction(Insn, 31, 1);
 554
 555   // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise
 556   // out assertions that it thinks should never be hit.
 557   enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc;
 558   Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2);
 559
 560   if (!SF) {
 561     // ImmR and ImmS must be between 0 and 31 for 32-bit instructions.
 562     if (ImmR > 31 || ImmS > 31)
 563       return MCDisassembler::Fail;
 564   }
 565
 566   if (SF) {
 567     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 568     // BFM MCInsts use Rd as a source too.
 569     if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 570     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 571   } else {
 572     DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
 573     // BFM MCInsts use Rd as a source too.
 574     if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
 575     DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
 576   }
 577
 578   // ASR and LSR have more specific patterns so they won't get here:
 579   assert(!(ImmS == 31 && !SF && Opc != BFM)
 580          && "shift should have used auto decode");
 581   assert(!(ImmS == 63 && SF && Opc != BFM)
 582          && "shift should have used auto decode");
 583
 584   // Extension instructions similarly:
 585   if (Opc == SBFM && ImmR == 0) {
 586     assert((ImmS != 7 && ImmS != 15) && "extension got here");
 587     assert((ImmS != 31 || SF == 0) && "extension got here");
 588   } else if (Opc == UBFM && ImmR == 0) {
 589     assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here");
 590   }
 591
 592   if (Opc == UBFM) {
 593     // It might be a LSL instruction, which actually takes the shift amount
 594     // itself as an MCInst operand.
 595     if (SF && (ImmS + 1) % 64 == ImmR) {
 596       Inst.setOpcode(AArch64::LSLxxi);
 597       Inst.addOperand(MCOperand::CreateImm(63 - ImmS));
 598       return MCDisassembler::Success;
 599     } else if (!SF && (ImmS + 1) % 32 == ImmR) {
 600       Inst.setOpcode(AArch64::LSLwwi);
 601       Inst.addOperand(MCOperand::CreateImm(31 - ImmS));
 602       return MCDisassembler::Success;
 603     }
 604   }
 605
 606   // Otherwise it's definitely either an extract or an insert depending on which
 607   // of ImmR or ImmS is larger.
 608   unsigned ExtractOp, InsertOp;
 609   switch (Opc) {
 610   default: llvm_unreachable("unexpected instruction trying to decode bitfield");
 611   case SBFM:
 612     ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii;
 613     InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii;
 614     break;
 615   case BFM:
 616     ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii;
 617     InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii;
 618     break;
 619   case UBFM:
 620     ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii;
 621     InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii;
 622     break;
 623   }
 624
 625   // Otherwise it's a boring insert or extract
 626   Inst.addOperand(MCOperand::CreateImm(ImmR));
 627   Inst.addOperand(MCOperand::CreateImm(ImmS));
 628
 629
 630   if (ImmS < ImmR)
 631     Inst.setOpcode(InsertOp);
 632   else
 633     Inst.setOpcode(ExtractOp);
 634
 635   return MCDisassembler::Success;
 636 }
 637
 638 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 639                                               uint64_t Address,
 640                                               const void *Decoder) {
 641   // This decoder exists to add the dummy Lane operand to the MCInst, which must
 642   // be 1 in assembly but has no other real manifestation.
 643   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 644   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 645   unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
 646
 647   if (IsToVec) {
 648     DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
 649     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 650   } else {
 651     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 652     DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
 653   }
 654
 655   // Add the lane
 656   Inst.addOperand(MCOperand::CreateImm(1));
 657
 658   return MCDisassembler::Success;
 659 }
 660
 661
 662 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
 663                                               unsigned Insn,
 664                                               uint64_t Address,
 665                                               const void *Decoder) {
 666   DecodeStatus Result = MCDisassembler::Success;
 667   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
 668   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 669   unsigned Rt2 = fieldFromInstruction(Insn, 10, 5);
 670   unsigned SImm7 = fieldFromInstruction(Insn, 15, 7);
 671   unsigned L = fieldFromInstruction(Insn, 22, 1);
 672   unsigned V = fieldFromInstruction(Insn, 26, 1);
 673   unsigned Opc = fieldFromInstruction(Insn, 30, 2);
 674
 675   // Not an official name, but it turns out that bit 23 distinguishes indexed
 676   // from non-indexed operations.
 677   unsigned Indexed = fieldFromInstruction(Insn, 23, 1);
 678
 679   if (Indexed && L == 0) {
 680     // The MCInst for an indexed store has an out operand and 4 ins:
 681     //    Rn_wb, Rt, Rt2, Rn, Imm
 682     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 683   }
 684
 685   // You shouldn't load to the same register twice in an instruction...
 686   if (L && Rt == Rt2)
 687     Result = MCDisassembler::SoftFail;
 688
 689   // ... or do any operation that writes-back to a transfer register. But note
 690   // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
 691   if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn))
 692     Result = MCDisassembler::SoftFail;
 693
 694   // Exactly how we decode the MCInst's registers depends on the Opc and V
 695   // fields of the instruction. These also obviously determine the size of the
 696   // operation so we can fill in that information while we're at it.
 697   if (V) {
 698     // The instruction operates on the FP/SIMD registers
 699     switch (Opc) {
 700     default: return MCDisassembler::Fail;
 701     case 0:
 702       DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
 703       DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder);
 704       break;
 705     case 1:
 706       DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
 707       DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder);
 708       break;
 709     case 2:
 710       DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
 711       DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder);
 712       break;
 713     }
 714   } else {
 715     switch (Opc) {
 716     default: return MCDisassembler::Fail;
 717     case 0:
 718       DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
 719       DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder);
 720       break;
 721     case 1:
 722       assert(L && "unexpected \"store signed\" attempt");
 723       DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 724       DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
 725       break;
 726     case 2:
 727       DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 728       DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
 729       break;
 730     }
 731   }
 732
 733   if (Indexed && L == 1) {
 734     // The MCInst for an indexed load has 3 out operands and an 3 ins:
 735     //    Rt, Rt2, Rn_wb, Rt2, Rn, Imm
 736     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 737   }
 738
 739
 740   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 741   Inst.addOperand(MCOperand::CreateImm(SImm7));
 742
 743   return Result;
 744 }
 745
 746 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
 747                                                        uint32_t Val,
 748                                                        uint64_t Address,
 749                                                        const void *Decoder) {
 750   unsigned Rt = fieldFromInstruction(Val, 0, 5);
 751   unsigned Rn = fieldFromInstruction(Val, 5, 5);
 752   unsigned Rt2 = fieldFromInstruction(Val, 10, 5);
 753   unsigned MemSize = fieldFromInstruction(Val, 30, 2);
 754
 755   DecodeStatus S = MCDisassembler::Success;
 756   if (Rt == Rt2) S = MCDisassembler::SoftFail;
 757
 758   switch (MemSize) {
 759     case 2:
 760       if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder)))
 761         return MCDisassembler::Fail;
 762       if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder)))
 763         return MCDisassembler::Fail;
 764       break;
 765     case 3:
 766       if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder)))
 767         return MCDisassembler::Fail;
 768       if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder)))
 769         return MCDisassembler::Fail;
 770       break;
 771     default:
 772       llvm_unreachable("Invalid MemSize in DecodeLoadPairExclusiveInstruction");
 773   }
 774
 775   if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder)))
 776     return MCDisassembler::Fail;
 777
 778   return S;
 779 }
 780
 781 template<typename SomeNamedImmMapper>
 782 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
 783                                           unsigned Val,
 784                                           uint64_t Address,
 785                                           const void *Decoder) {
 786   SomeNamedImmMapper Mapper;
 787   bool ValidNamed;
 788   Mapper.toString(Val, ValidNamed);
 789   if (ValidNamed || Mapper.validImm(Val)) {
 790     Inst.addOperand(MCOperand::CreateImm(Val));
 791     return MCDisassembler::Success;
 792   }
 793
 794   return MCDisassembler::Fail;
 795 }
 796
 797 static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
 798                                         llvm::MCInst &Inst,
 799                                         unsigned Val,
 800                                         uint64_t Address,
 801                                         const void *Decoder) {
 802   bool ValidNamed;
 803   Mapper.toString(Val, ValidNamed);
 804
 805   Inst.addOperand(MCOperand::CreateImm(Val));
 806
 807   return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail;
 808 }
 809
 810 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
 811                                      unsigned Val,
 812                                      uint64_t Address,
 813                                      const void *Decoder) {
 814   return DecodeSysRegOperand(A64SysReg::MRSMapper(), Inst, Val, Address,
 815                              Decoder);
 816 }
 817
 818 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
 819                                      unsigned Val,
 820                                      uint64_t Address,
 821                                      const void *Decoder) {
 822   return DecodeSysRegOperand(A64SysReg::MSRMapper(), Inst, Val, Address,
 823                              Decoder);
 824 }
 825
 826 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
 827                                                    unsigned Insn,
 828                                                    uint64_t Address,
 829                                                    const void *Decoder) {
 830   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
 831   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 832   unsigned Imm9 = fieldFromInstruction(Insn, 12, 9);
 833
 834   unsigned Opc = fieldFromInstruction(Insn, 22, 2);
 835   unsigned V = fieldFromInstruction(Insn, 26, 1);
 836   unsigned Size = fieldFromInstruction(Insn, 30, 2);
 837
 838   if (Opc == 0 || (V == 1 && Opc == 2)) {
 839     // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm
 840     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 841   }
 842
 843   if (V == 0 && (Opc == 2 || Size == 3)) {
 844     DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 845   } else if (V == 0) {
 846     DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
 847   } else if (V == 1 && (Opc & 2)) {
 848     DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
 849   } else {
 850     switch (Size) {
 851     case 0:
 852       DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder);
 853       break;
 854     case 1:
 855       DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder);
 856       break;
 857     case 2:
 858       DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
 859       break;
 860     case 3:
 861       DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
 862       break;
 863     }
 864   }
 865
 866   if (Opc != 0 && (V != 1 || Opc != 2)) {
 867     // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm
 868     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 869   }
 870
 871   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 872
 873   Inst.addOperand(MCOperand::CreateImm(Imm9));
 874
 875   // N.b. The official documentation says undpredictable if Rt == Rn, but this
 876   // takes place at the architectural rather than encoding level:
 877   //
 878   // "STR xzr, [sp], #4" is perfectly valid.
 879   if (V == 0 && Rt == Rn && Rn != 31)
 880     return MCDisassembler::SoftFail;
 881   else
 882     return MCDisassembler::Success;
 883 }
 884
 885 static MCDisassembler *createAArch64Disassembler(const Target &T,
 886                                                  const MCSubtargetInfo &STI) {
 887   return new AArch64Disassembler(STI, T.createMCRegInfo(""));
 888 }
 889
 890 extern "C" void LLVMInitializeAArch64Disassembler() {
 891   TargetRegistry::RegisterMCDisassembler(TheAArch64Target,
 892                                          createAArch64Disassembler);
 893 }
 894
 895 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
 896 static DecodeStatus
 897 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
 898                              uint64_t Address, const void *Decoder) {
 899   bool IsLSL = false;
 900   if (Ext == A64SE::LSL)
 901     IsLSL = true;
 902   else if (Ext != A64SE::MSL)
 903     return MCDisassembler::Fail;
 904
 905   // MSL and LSLH accepts encoded shift amount 0 or 1.
 906   if ((!IsLSL || (IsLSL && IsHalf)) && ShiftAmount != 0 && ShiftAmount != 1)
 907     return MCDisassembler::Fail;
 908
 909   // LSL  accepts encoded shift amount 0, 1, 2 or 3.
 910   if (IsLSL && ShiftAmount > 3)
 911     return MCDisassembler::Fail;
 912
 913   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 914   return MCDisassembler::Success;
 915 }