lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

   1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the functions necessary to decode AArch64 instruction
  11 // bitpatterns into MCInsts (with the help of TableGenerated information from
  12 // the instruction definitions).
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #define DEBUG_TYPE "arm-disassembler"
  17
  18 #include "AArch64.h"
  19 #include "AArch64RegisterInfo.h"
  20 #include "AArch64Subtarget.h"
  21 #include "Utils/AArch64BaseInfo.h"
  22 #include "llvm/MC/MCInst.h"
  23 #include "llvm/MC/MCInstrDesc.h"
  24 #include "llvm/MC/MCExpr.h"
  25 #include "llvm/MC/MCContext.h"
  26 #include "llvm/MC/MCDisassembler.h"
  27 #include "llvm/MC/MCFixedLenDisassembler.h"
  28 #include "llvm/Support/Debug.h"
  29 #include "llvm/Support/MemoryObject.h"
  30 #include "llvm/Support/ErrorHandling.h"
  31 #include "llvm/Support/TargetRegistry.h"
  32 #include "llvm/Support/raw_ostream.h"
  33
  34 using namespace llvm;
  35
  36 typedef MCDisassembler::DecodeStatus DecodeStatus;
  37
  38 namespace {
  39 /// AArch64 disassembler for all AArch64 platforms.
  40 class AArch64Disassembler : public MCDisassembler {
  41   OwningPtr<const MCRegisterInfo> RegInfo;
  42 public:
  43   /// Initializes the disassembler.
  44   ///
  45   AArch64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info)
  46     : MCDisassembler(STI), RegInfo(Info) {
  47   }
  48
  49   ~AArch64Disassembler() {}
  50
  51   /// See MCDisassembler.
  52   DecodeStatus getInstruction(MCInst &instr,
  53                               uint64_t &size,
  54                               const MemoryObject &region,
  55                               uint64_t address,
  56                               raw_ostream &vStream,
  57                               raw_ostream &cStream) const;
  58
  59   const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
  60 };
  61
  62 }
  63
  64 // Forward-declarations used in the auto-generated files.
  65 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  66                                          uint64_t Address, const void *Decoder);
  67 static DecodeStatus
  68 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  69                             uint64_t Address, const void *Decoder);
  70
  71 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  72                                          uint64_t Address, const void *Decoder);
  73 static DecodeStatus
  74 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  75                             uint64_t Address, const void *Decoder);
  76
  77 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  78                                          uint64_t Address, const void *Decoder);
  79 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  80                                          uint64_t Address, const void *Decoder);
  81 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  82                                          uint64_t Address, const void *Decoder);
  83 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  84                                          uint64_t Address, const void *Decoder);
  85 static DecodeStatus DecodeFPR64LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  86                                          uint64_t Address, const void *Decoder);
  87 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
  88                                               unsigned RegNo, uint64_t Address,
  89                                               const void *Decoder);
  90 static DecodeStatus DecodeFPR128LoRegisterClass(llvm::MCInst &Inst,
  91                                                 unsigned RegNo, uint64_t Address,
  92                                                 const void *Decoder);
  93
  94 static DecodeStatus DecodeGPR64noxzrRegisterClass(llvm::MCInst &Inst,
  95                                                   unsigned RegNo,
  96                                                   uint64_t Address,
  97                                                   const void *Decoder);
  98
  99 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 100                                              uint64_t Address,
 101                                              const void *Decoder);
 102 static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 103                                              uint64_t Address,
 104                                              const void *Decoder);
 105 static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst,
 106                                                unsigned RegNo, uint64_t Address,
 107                                                const void *Decoder);
 108 static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst,
 109                                                unsigned RegNo, uint64_t Address,
 110                                                const void *Decoder);
 111 static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 112                                              uint64_t Address,
 113                                              const void *Decoder);
 114 static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 115                                              uint64_t Address,
 116                                              const void *Decoder);
 117
 118 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
 119                                                unsigned OptionHiS,
 120                                                uint64_t Address,
 121                                                const void *Decoder);
 122
 123
 124 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
 125                                                unsigned Imm6Bits,
 126                                                uint64_t Address,
 127                                                const void *Decoder);
 128
 129 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
 130                                                unsigned Imm6Bits,
 131                                                uint64_t Address,
 132                                                const void *Decoder);
 133
 134 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
 135                                         unsigned RmBits,
 136                                         uint64_t Address,
 137                                         const void *Decoder);
 138
 139 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val,
 140                                          uint64_t Address, const void *Decoder);
 141 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val,
 142                                           uint64_t Address,
 143                                           const void *Decoder);
 144 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val,
 145                                           uint64_t Address,
 146                                           const void *Decoder);
 147 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val,
 148                                           uint64_t Address,
 149                                           const void *Decoder);
 150
 151 static DecodeStatus DecodeShiftLeftImm8(MCInst &Inst, unsigned Val,
 152                                         uint64_t Address, const void *Decoder);
 153 static DecodeStatus DecodeShiftLeftImm16(MCInst &Inst, unsigned Val,
 154                                          uint64_t Address,
 155                                          const void *Decoder);
 156 static DecodeStatus DecodeShiftLeftImm32(MCInst &Inst, unsigned Val,
 157                                          uint64_t Address,
 158                                          const void *Decoder);
 159 static DecodeStatus DecodeShiftLeftImm64(MCInst &Inst, unsigned Val,
 160                                          uint64_t Address,
 161                                          const void *Decoder);
 162
 163 template<int RegWidth>
 164 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
 165                                              unsigned FullImm,
 166                                              uint64_t Address,
 167                                              const void *Decoder);
 168
 169 template<int RegWidth>
 170 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
 171                                             unsigned Bits,
 172                                             uint64_t Address,
 173                                             const void *Decoder);
 174
 175 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
 176                                            unsigned ShiftAmount,
 177                                            uint64_t Address,
 178                                            const void *Decoder);
 179 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
 180 static DecodeStatus
 181 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
 182                              uint64_t Address, const void *Decoder);
 183
 184 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
 185                                             unsigned ShiftAmount,
 186                                             uint64_t Address,
 187                                             const void *Decoder);
 188 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
 189                                               uint64_t Address,
 190                                               const void *Decoder);
 191
 192 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 193                                               uint64_t Address,
 194                                               const void *Decoder);
 195
 196 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
 197                                               unsigned Insn,
 198                                               uint64_t Address,
 199                                               const void *Decoder);
 200
 201 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
 202                                                        unsigned Val,
 203                                                        uint64_t Address,
 204                                                        const void *Decoder);
 205
 206 template<typename SomeNamedImmMapper>
 207 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
 208                                           unsigned Val,
 209                                           uint64_t Address,
 210                                           const void *Decoder);
 211
 212 static DecodeStatus
 213 DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper,
 214                     llvm::MCInst &Inst, unsigned Val,
 215                     uint64_t Address, const void *Decoder);
 216
 217 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
 218                                      unsigned Val,
 219                                      uint64_t Address,
 220                                      const void *Decoder);
 221
 222 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
 223                                      unsigned Val,
 224                                      uint64_t Address,
 225                                      const void *Decoder);
 226
 227
 228 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
 229                                                    unsigned Val,
 230                                                    uint64_t Address,
 231                                                    const void *Decoder);
 232
 233 static DecodeStatus DecodeVLDSTPostInstruction(MCInst &Inst, unsigned Val,
 234                                                uint64_t Address,
 235                                                const void *Decoder);
 236
 237 static bool Check(DecodeStatus &Out, DecodeStatus In);
 238
 239 #include "AArch64GenDisassemblerTables.inc"
 240 #include "AArch64GenInstrInfo.inc"
 241
 242 static bool Check(DecodeStatus &Out, DecodeStatus In) {
 243   switch (In) {
 244     case MCDisassembler::Success:
 245       // Out stays the same.
 246       return true;
 247     case MCDisassembler::SoftFail:
 248       Out = In;
 249       return true;
 250     case MCDisassembler::Fail:
 251       Out = In;
 252       return false;
 253   }
 254   llvm_unreachable("Invalid DecodeStatus!");
 255 }
 256
 257 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
 258                                                  const MemoryObject &Region,
 259                                                  uint64_t Address,
 260                                                  raw_ostream &os,
 261                                                  raw_ostream &cs) const {
 262   CommentStream = &cs;
 263
 264   uint8_t bytes[4];
 265
 266   // We want to read exactly 4 bytes of data.
 267   if (Region.readBytes(Address, 4, bytes) == -1) {
 268     Size = 0;
 269     return MCDisassembler::Fail;
 270   }
 271
 272   // Encoded as a small-endian 32-bit word in the stream.
 273   uint32_t insn = (bytes[3] << 24) |
 274     (bytes[2] << 16) |
 275     (bytes[1] <<  8) |
 276     (bytes[0] <<  0);
 277
 278   // Calling the auto-generated decoder function.
 279   DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address,
 280                                           this, STI);
 281   if (result != MCDisassembler::Fail) {
 282     Size = 4;
 283     return result;
 284   }
 285
 286   MI.clear();
 287   Size = 0;
 288   return MCDisassembler::Fail;
 289 }
 290
 291 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 292   const AArch64Disassembler *Dis = static_cast<const AArch64Disassembler*>(D);
 293   return Dis->getRegInfo()->getRegClass(RC).getRegister(RegNo);
 294 }
 295
 296 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 297                                         uint64_t Address, const void *Decoder) {
 298   if (RegNo > 31)
 299     return MCDisassembler::Fail;
 300
 301   uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo);
 302   Inst.addOperand(MCOperand::CreateReg(Register));
 303   return MCDisassembler::Success;
 304 }
 305
 306 static DecodeStatus
 307 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 308                             uint64_t Address, const void *Decoder) {
 309   if (RegNo > 31)
 310     return MCDisassembler::Fail;
 311
 312   uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo);
 313   Inst.addOperand(MCOperand::CreateReg(Register));
 314   return MCDisassembler::Success;
 315 }
 316
 317 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 318                                              uint64_t Address,
 319                                              const void *Decoder) {
 320   if (RegNo > 31)
 321     return MCDisassembler::Fail;
 322
 323   uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo);
 324   Inst.addOperand(MCOperand::CreateReg(Register));
 325   return MCDisassembler::Success;
 326 }
 327
 328 static DecodeStatus
 329 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 330                             uint64_t Address, const void *Decoder) {
 331   if (RegNo > 31)
 332     return MCDisassembler::Fail;
 333
 334   uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo);
 335   Inst.addOperand(MCOperand::CreateReg(Register));
 336   return MCDisassembler::Success;
 337 }
 338
 339 static DecodeStatus
 340 DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 341                             uint64_t Address, const void *Decoder) {
 342   if (RegNo > 31)
 343     return MCDisassembler::Fail;
 344
 345   uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo);
 346   Inst.addOperand(MCOperand::CreateReg(Register));
 347   return MCDisassembler::Success;
 348 }
 349
 350 static DecodeStatus
 351 DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 352                             uint64_t Address, const void *Decoder) {
 353   if (RegNo > 31)
 354     return MCDisassembler::Fail;
 355
 356   uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo);
 357   Inst.addOperand(MCOperand::CreateReg(Register));
 358   return MCDisassembler::Success;
 359 }
 360
 361
 362 static DecodeStatus
 363 DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 364                             uint64_t Address, const void *Decoder) {
 365   if (RegNo > 31)
 366     return MCDisassembler::Fail;
 367
 368   uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo);
 369   Inst.addOperand(MCOperand::CreateReg(Register));
 370   return MCDisassembler::Success;
 371 }
 372
 373 static DecodeStatus
 374 DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 375                             uint64_t Address, const void *Decoder) {
 376   if (RegNo > 31)
 377     return MCDisassembler::Fail;
 378
 379   uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo);
 380   Inst.addOperand(MCOperand::CreateReg(Register));
 381   return MCDisassembler::Success;
 382 }
 383
 384 static DecodeStatus
 385 DecodeFPR64LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 386                             uint64_t Address, const void *Decoder) {
 387   if (RegNo > 15)
 388     return MCDisassembler::Fail;
 389
 390   return DecodeFPR64RegisterClass(Inst, RegNo, Address, Decoder);
 391 }
 392
 393 static DecodeStatus
 394 DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 395                             uint64_t Address, const void *Decoder) {
 396   if (RegNo > 31)
 397     return MCDisassembler::Fail;
 398
 399   uint16_t Register = getReg(Decoder, AArch64::FPR128RegClassID, RegNo);
 400   Inst.addOperand(MCOperand::CreateReg(Register));
 401   return MCDisassembler::Success;
 402 }
 403
 404 static DecodeStatus
 405 DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 406                             uint64_t Address, const void *Decoder) {
 407   if (RegNo > 15)
 408     return MCDisassembler::Fail;
 409
 410   return DecodeFPR128RegisterClass(Inst, RegNo, Address, Decoder);
 411 }
 412
 413 static DecodeStatus DecodeGPR64noxzrRegisterClass(llvm::MCInst &Inst,
 414                                                   unsigned RegNo,
 415                                                   uint64_t Address,
 416                                                   const void *Decoder) {
 417   if (RegNo >= 30)
 418     return MCDisassembler::Fail;
 419
 420   uint16_t Register = getReg(Decoder, AArch64::GPR64noxzrRegClassID, RegNo);
 421   Inst.addOperand(MCOperand::CreateReg(Register));
 422   return MCDisassembler::Success;
 423 }
 424
 425 static DecodeStatus DecodeRegisterClassByID(llvm::MCInst &Inst, unsigned RegNo,
 426                                             unsigned RegID,
 427                                             const void *Decoder) {
 428   if (RegNo > 31)
 429     return MCDisassembler::Fail;
 430
 431   uint16_t Register = getReg(Decoder, RegID, RegNo);
 432   Inst.addOperand(MCOperand::CreateReg(Register));
 433   return MCDisassembler::Success;
 434 }
 435
 436 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 437                                              uint64_t Address,
 438                                              const void *Decoder) {
 439   return DecodeRegisterClassByID(Inst, RegNo, AArch64::DPairRegClassID,
 440                                  Decoder);
 441 }
 442
 443 static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 444                                              uint64_t Address,
 445                                              const void *Decoder) {
 446   return DecodeRegisterClassByID(Inst, RegNo, AArch64::QPairRegClassID,
 447                                  Decoder);
 448 }
 449
 450 static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst,
 451                                                unsigned RegNo, uint64_t Address,
 452                                                const void *Decoder) {
 453   return DecodeRegisterClassByID(Inst, RegNo, AArch64::DTripleRegClassID,
 454                                  Decoder);
 455 }
 456
 457 static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst,
 458                                                unsigned RegNo, uint64_t Address,
 459                                                const void *Decoder) {
 460   return DecodeRegisterClassByID(Inst, RegNo, AArch64::QTripleRegClassID,
 461                                  Decoder);
 462 }
 463
 464 static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 465                                              uint64_t Address,
 466                                              const void *Decoder) {
 467   return DecodeRegisterClassByID(Inst, RegNo, AArch64::DQuadRegClassID,
 468                                  Decoder);
 469 }
 470
 471 static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 472                                              uint64_t Address,
 473                                              const void *Decoder) {
 474   return DecodeRegisterClassByID(Inst, RegNo, AArch64::QQuadRegClassID,
 475                                  Decoder);
 476 }
 477
 478 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
 479                                                unsigned OptionHiS,
 480                                                uint64_t Address,
 481                                                const void *Decoder) {
 482   // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1},
 483   // S}. Hence we want to check bit 1.
 484   if (!(OptionHiS & 2))
 485     return MCDisassembler::Fail;
 486
 487   Inst.addOperand(MCOperand::CreateImm(OptionHiS));
 488   return MCDisassembler::Success;
 489 }
 490
 491 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
 492                                                unsigned Imm6Bits,
 493                                                uint64_t Address,
 494                                                const void *Decoder) {
 495   // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be
 496   // between 0 and 31.
 497   if (Imm6Bits > 31)
 498     return MCDisassembler::Fail;
 499
 500   Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
 501   return MCDisassembler::Success;
 502 }
 503
 504 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
 505                                                unsigned Imm6Bits,
 506                                                uint64_t Address,
 507                                                const void *Decoder) {
 508   // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32.
 509   if (Imm6Bits < 32)
 510     return MCDisassembler::Fail;
 511
 512   Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
 513   return MCDisassembler::Success;
 514 }
 515
 516 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
 517                                         unsigned RmBits,
 518                                         uint64_t Address,
 519                                         const void *Decoder) {
 520   // Any bits are valid in the instruction (they're architecturally ignored),
 521   // but a code generator should insert 0.
 522   Inst.addOperand(MCOperand::CreateImm(0));
 523   return MCDisassembler::Success;
 524 }
 525
 526 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val,
 527                                          uint64_t Address,
 528                                          const void *Decoder) {
 529   Inst.addOperand(MCOperand::CreateImm(8 - Val));
 530   return MCDisassembler::Success;
 531 }
 532
 533 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val,
 534                                           uint64_t Address,
 535                                           const void *Decoder) {
 536   Inst.addOperand(MCOperand::CreateImm(16 - Val));
 537   return MCDisassembler::Success;
 538 }
 539
 540 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val,
 541                                           uint64_t Address,
 542                                           const void *Decoder) {
 543   Inst.addOperand(MCOperand::CreateImm(32 - Val));
 544   return MCDisassembler::Success;
 545 }
 546
 547 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val,
 548                                           uint64_t Address,
 549                                           const void *Decoder) {
 550   Inst.addOperand(MCOperand::CreateImm(64 - Val));
 551   return MCDisassembler::Success;
 552 }
 553
 554 static DecodeStatus DecodeShiftLeftImm8(MCInst &Inst, unsigned Val,
 555                                         uint64_t Address,
 556                                         const void *Decoder) {
 557   if (Val > 7)
 558     return MCDisassembler::Fail;
 559
 560   Inst.addOperand(MCOperand::CreateImm(Val));
 561   return MCDisassembler::Success;
 562 }
 563
 564 static DecodeStatus DecodeShiftLeftImm16(MCInst &Inst, unsigned Val,
 565                                          uint64_t Address,
 566                                          const void *Decoder) {
 567   if (Val > 15)
 568     return MCDisassembler::Fail;
 569
 570   Inst.addOperand(MCOperand::CreateImm(Val));
 571   return MCDisassembler::Success;
 572 }
 573
 574 static DecodeStatus DecodeShiftLeftImm32(MCInst &Inst, unsigned Val,
 575                                          uint64_t Address,
 576                                          const void *Decoder) {
 577   if (Val > 31)
 578     return MCDisassembler::Fail;
 579
 580   Inst.addOperand(MCOperand::CreateImm(Val));
 581   return MCDisassembler::Success;
 582 }
 583
 584 static DecodeStatus DecodeShiftLeftImm64(MCInst &Inst, unsigned Val,
 585                                          uint64_t Address,
 586                                          const void *Decoder) {
 587   if (Val > 63)
 588     return MCDisassembler::Fail;
 589
 590   Inst.addOperand(MCOperand::CreateImm(Val));
 591   return MCDisassembler::Success;
 592 }
 593
 594 template<int RegWidth>
 595 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
 596                                              unsigned FullImm,
 597                                              uint64_t Address,
 598                                              const void *Decoder) {
 599   unsigned Imm16 = FullImm & 0xffff;
 600   unsigned Shift = FullImm >> 16;
 601
 602   if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail;
 603
 604   Inst.addOperand(MCOperand::CreateImm(Imm16));
 605   Inst.addOperand(MCOperand::CreateImm(Shift));
 606   return MCDisassembler::Success;
 607 }
 608
 609 template<int RegWidth>
 610 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
 611                                             unsigned Bits,
 612                                             uint64_t Address,
 613                                             const void *Decoder) {
 614   uint64_t Imm;
 615   if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm))
 616     return MCDisassembler::Fail;
 617
 618   Inst.addOperand(MCOperand::CreateImm(Bits));
 619   return MCDisassembler::Success;
 620 }
 621
 622
 623 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
 624                                            unsigned ShiftAmount,
 625                                            uint64_t Address,
 626                                            const void *Decoder) {
 627   // Only values 0-4 are valid for this 3-bit field
 628   if (ShiftAmount > 4)
 629     return MCDisassembler::Fail;
 630
 631   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 632   return MCDisassembler::Success;
 633 }
 634
 635 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
 636                                             unsigned ShiftAmount,
 637                                             uint64_t Address,
 638                                             const void *Decoder) {
 639   // Only values below 32 are valid for a 32-bit register
 640   if (ShiftAmount > 31)
 641     return MCDisassembler::Fail;
 642
 643   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 644   return MCDisassembler::Success;
 645 }
 646
 647 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
 648                                               uint64_t Address,
 649                                               const void *Decoder) {
 650   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 651   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 652   unsigned ImmS = fieldFromInstruction(Insn, 10, 6);
 653   unsigned ImmR = fieldFromInstruction(Insn, 16, 6);
 654   unsigned SF = fieldFromInstruction(Insn, 31, 1);
 655
 656   // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise
 657   // out assertions that it thinks should never be hit.
 658   enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc;
 659   Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2);
 660
 661   if (!SF) {
 662     // ImmR and ImmS must be between 0 and 31 for 32-bit instructions.
 663     if (ImmR > 31 || ImmS > 31)
 664       return MCDisassembler::Fail;
 665   }
 666
 667   if (SF) {
 668     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 669     // BFM MCInsts use Rd as a source too.
 670     if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 671     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 672   } else {
 673     DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
 674     // BFM MCInsts use Rd as a source too.
 675     if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
 676     DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
 677   }
 678
 679   // ASR and LSR have more specific patterns so they won't get here:
 680   assert(!(ImmS == 31 && !SF && Opc != BFM)
 681          && "shift should have used auto decode");
 682   assert(!(ImmS == 63 && SF && Opc != BFM)
 683          && "shift should have used auto decode");
 684
 685   // Extension instructions similarly:
 686   if (Opc == SBFM && ImmR == 0) {
 687     assert((ImmS != 7 && ImmS != 15) && "extension got here");
 688     assert((ImmS != 31 || SF == 0) && "extension got here");
 689   } else if (Opc == UBFM && ImmR == 0) {
 690     assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here");
 691   }
 692
 693   if (Opc == UBFM) {
 694     // It might be a LSL instruction, which actually takes the shift amount
 695     // itself as an MCInst operand.
 696     if (SF && (ImmS + 1) % 64 == ImmR) {
 697       Inst.setOpcode(AArch64::LSLxxi);
 698       Inst.addOperand(MCOperand::CreateImm(63 - ImmS));
 699       return MCDisassembler::Success;
 700     } else if (!SF && (ImmS + 1) % 32 == ImmR) {
 701       Inst.setOpcode(AArch64::LSLwwi);
 702       Inst.addOperand(MCOperand::CreateImm(31 - ImmS));
 703       return MCDisassembler::Success;
 704     }
 705   }
 706
 707   // Otherwise it's definitely either an extract or an insert depending on which
 708   // of ImmR or ImmS is larger.
 709   unsigned ExtractOp, InsertOp;
 710   switch (Opc) {
 711   default: llvm_unreachable("unexpected instruction trying to decode bitfield");
 712   case SBFM:
 713     ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii;
 714     InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii;
 715     break;
 716   case BFM:
 717     ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii;
 718     InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii;
 719     break;
 720   case UBFM:
 721     ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii;
 722     InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii;
 723     break;
 724   }
 725
 726   // Otherwise it's a boring insert or extract
 727   Inst.addOperand(MCOperand::CreateImm(ImmR));
 728   Inst.addOperand(MCOperand::CreateImm(ImmS));
 729
 730
 731   if (ImmS < ImmR)
 732     Inst.setOpcode(InsertOp);
 733   else
 734     Inst.setOpcode(ExtractOp);
 735
 736   return MCDisassembler::Success;
 737 }
 738
 739 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 740                                               uint64_t Address,
 741                                               const void *Decoder) {
 742   // This decoder exists to add the dummy Lane operand to the MCInst, which must
 743   // be 1 in assembly but has no other real manifestation.
 744   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 745   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 746   unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
 747
 748   if (IsToVec) {
 749     DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
 750     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 751   } else {
 752     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 753     DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
 754   }
 755
 756   // Add the lane
 757   Inst.addOperand(MCOperand::CreateImm(1));
 758
 759   return MCDisassembler::Success;
 760 }
 761
 762
 763 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
 764                                               unsigned Insn,
 765                                               uint64_t Address,
 766                                               const void *Decoder) {
 767   DecodeStatus Result = MCDisassembler::Success;
 768   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
 769   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 770   unsigned Rt2 = fieldFromInstruction(Insn, 10, 5);
 771   unsigned SImm7 = fieldFromInstruction(Insn, 15, 7);
 772   unsigned L = fieldFromInstruction(Insn, 22, 1);
 773   unsigned V = fieldFromInstruction(Insn, 26, 1);
 774   unsigned Opc = fieldFromInstruction(Insn, 30, 2);
 775
 776   // Not an official name, but it turns out that bit 23 distinguishes indexed
 777   // from non-indexed operations.
 778   unsigned Indexed = fieldFromInstruction(Insn, 23, 1);
 779
 780   if (Indexed && L == 0) {
 781     // The MCInst for an indexed store has an out operand and 4 ins:
 782     //    Rn_wb, Rt, Rt2, Rn, Imm
 783     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 784   }
 785
 786   // You shouldn't load to the same register twice in an instruction...
 787   if (L && Rt == Rt2)
 788     Result = MCDisassembler::SoftFail;
 789
 790   // ... or do any operation that writes-back to a transfer register. But note
 791   // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
 792   if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn))
 793     Result = MCDisassembler::SoftFail;
 794
 795   // Exactly how we decode the MCInst's registers depends on the Opc and V
 796   // fields of the instruction. These also obviously determine the size of the
 797   // operation so we can fill in that information while we're at it.
 798   if (V) {
 799     // The instruction operates on the FP/SIMD registers
 800     switch (Opc) {
 801     default: return MCDisassembler::Fail;
 802     case 0:
 803       DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
 804       DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder);
 805       break;
 806     case 1:
 807       DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
 808       DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder);
 809       break;
 810     case 2:
 811       DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
 812       DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder);
 813       break;
 814     }
 815   } else {
 816     switch (Opc) {
 817     default: return MCDisassembler::Fail;
 818     case 0:
 819       DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
 820       DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder);
 821       break;
 822     case 1:
 823       assert(L && "unexpected \"store signed\" attempt");
 824       DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 825       DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
 826       break;
 827     case 2:
 828       DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 829       DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
 830       break;
 831     }
 832   }
 833
 834   if (Indexed && L == 1) {
 835     // The MCInst for an indexed load has 3 out operands and an 3 ins:
 836     //    Rt, Rt2, Rn_wb, Rt2, Rn, Imm
 837     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 838   }
 839
 840
 841   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 842   Inst.addOperand(MCOperand::CreateImm(SImm7));
 843
 844   return Result;
 845 }
 846
 847 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
 848                                                        uint32_t Val,
 849                                                        uint64_t Address,
 850                                                        const void *Decoder) {
 851   unsigned Rt = fieldFromInstruction(Val, 0, 5);
 852   unsigned Rn = fieldFromInstruction(Val, 5, 5);
 853   unsigned Rt2 = fieldFromInstruction(Val, 10, 5);
 854   unsigned MemSize = fieldFromInstruction(Val, 30, 2);
 855
 856   DecodeStatus S = MCDisassembler::Success;
 857   if (Rt == Rt2) S = MCDisassembler::SoftFail;
 858
 859   switch (MemSize) {
 860     case 2:
 861       if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder)))
 862         return MCDisassembler::Fail;
 863       if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder)))
 864         return MCDisassembler::Fail;
 865       break;
 866     case 3:
 867       if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder)))
 868         return MCDisassembler::Fail;
 869       if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder)))
 870         return MCDisassembler::Fail;
 871       break;
 872     default:
 873       llvm_unreachable("Invalid MemSize in DecodeLoadPairExclusiveInstruction");
 874   }
 875
 876   if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder)))
 877     return MCDisassembler::Fail;
 878
 879   return S;
 880 }
 881
 882 template<typename SomeNamedImmMapper>
 883 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
 884                                           unsigned Val,
 885                                           uint64_t Address,
 886                                           const void *Decoder) {
 887   SomeNamedImmMapper Mapper;
 888   bool ValidNamed;
 889   Mapper.toString(Val, ValidNamed);
 890   if (ValidNamed || Mapper.validImm(Val)) {
 891     Inst.addOperand(MCOperand::CreateImm(Val));
 892     return MCDisassembler::Success;
 893   }
 894
 895   return MCDisassembler::Fail;
 896 }
 897
 898 static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
 899                                         llvm::MCInst &Inst,
 900                                         unsigned Val,
 901                                         uint64_t Address,
 902                                         const void *Decoder) {
 903   bool ValidNamed;
 904   Mapper.toString(Val, ValidNamed);
 905
 906   Inst.addOperand(MCOperand::CreateImm(Val));
 907
 908   return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail;
 909 }
 910
 911 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
 912                                      unsigned Val,
 913                                      uint64_t Address,
 914                                      const void *Decoder) {
 915   return DecodeSysRegOperand(A64SysReg::MRSMapper(), Inst, Val, Address,
 916                              Decoder);
 917 }
 918
 919 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
 920                                      unsigned Val,
 921                                      uint64_t Address,
 922                                      const void *Decoder) {
 923   return DecodeSysRegOperand(A64SysReg::MSRMapper(), Inst, Val, Address,
 924                              Decoder);
 925 }
 926
 927 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
 928                                                    unsigned Insn,
 929                                                    uint64_t Address,
 930                                                    const void *Decoder) {
 931   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
 932   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 933   unsigned Imm9 = fieldFromInstruction(Insn, 12, 9);
 934
 935   unsigned Opc = fieldFromInstruction(Insn, 22, 2);
 936   unsigned V = fieldFromInstruction(Insn, 26, 1);
 937   unsigned Size = fieldFromInstruction(Insn, 30, 2);
 938
 939   if (Opc == 0 || (V == 1 && Opc == 2)) {
 940     // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm
 941     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 942   }
 943
 944   if (V == 0 && (Opc == 2 || Size == 3)) {
 945     DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 946   } else if (V == 0) {
 947     DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
 948   } else if (V == 1 && (Opc & 2)) {
 949     DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
 950   } else {
 951     switch (Size) {
 952     case 0:
 953       DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder);
 954       break;
 955     case 1:
 956       DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder);
 957       break;
 958     case 2:
 959       DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
 960       break;
 961     case 3:
 962       DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
 963       break;
 964     }
 965   }
 966
 967   if (Opc != 0 && (V != 1 || Opc != 2)) {
 968     // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm
 969     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 970   }
 971
 972   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 973
 974   Inst.addOperand(MCOperand::CreateImm(Imm9));
 975
 976   // N.b. The official documentation says undpredictable if Rt == Rn, but this
 977   // takes place at the architectural rather than encoding level:
 978   //
 979   // "STR xzr, [sp], #4" is perfectly valid.
 980   if (V == 0 && Rt == Rn && Rn != 31)
 981     return MCDisassembler::SoftFail;
 982   else
 983     return MCDisassembler::Success;
 984 }
 985
 986 static MCDisassembler *createAArch64Disassembler(const Target &T,
 987                                                  const MCSubtargetInfo &STI) {
 988   return new AArch64Disassembler(STI, T.createMCRegInfo(""));
 989 }
 990
 991 extern "C" void LLVMInitializeAArch64Disassembler() {
 992   TargetRegistry::RegisterMCDisassembler(TheAArch64Target,
 993                                          createAArch64Disassembler);
 994 }
 995
 996 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
 997 static DecodeStatus
 998 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
 999                              uint64_t Address, const void *Decoder) {
1000   bool IsLSL = false;
1001   if (Ext == A64SE::LSL)
1002     IsLSL = true;
1003   else if (Ext != A64SE::MSL)
1004     return MCDisassembler::Fail;
1005
1006   // MSL and LSLH accepts encoded shift amount 0 or 1.
1007   if ((!IsLSL || (IsLSL && IsHalf)) && ShiftAmount != 0 && ShiftAmount != 1)
1008     return MCDisassembler::Fail;
1009
1010   // LSL  accepts encoded shift amount 0, 1, 2 or 3.
1011   if (IsLSL && ShiftAmount > 3)
1012     return MCDisassembler::Fail;
1013
1014   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
1015   return MCDisassembler::Success;
1016 }
1017
1018 // Decode post-index vector load/store instructions.
1019 // This is necessary as we need to decode Rm: if Rm == 0b11111, the last
1020 // operand is an immediate equal the the length of vector list in bytes,
1021 // or Rm is decoded to a GPR64noxzr register.
1022 static DecodeStatus DecodeVLDSTPostInstruction(MCInst &Inst, unsigned Insn,
1023                                                uint64_t Address,
1024                                                const void *Decoder) {
1025   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
1026   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
1027   unsigned Rm = fieldFromInstruction(Insn, 16, 5);
1028   unsigned Opcode = fieldFromInstruction(Insn, 12, 4);
1029   unsigned IsLoad = fieldFromInstruction(Insn, 22, 1);
1030   // 0 for 64bit vector list, 1 for 128bit vector list
1031   unsigned Is128BitVec = fieldFromInstruction(Insn, 30, 1);
1032
1033   unsigned NumVecs;
1034   switch (Opcode) {
1035   case 0: // ld4/st4
1036   case 2: // ld1/st1 with 4 vectors
1037     NumVecs = 4; break;
1038   case 4: // ld3/st3
1039   case 6: // ld1/st1 with 3 vectors
1040     NumVecs = 3; break;
1041   case 7: // ld1/st1 with 1 vector
1042     NumVecs = 1; break;
1043   case 8:  // ld2/st2
1044   case 10: // ld1/st1 with 2 vectors
1045     NumVecs = 2; break;
1046   default:
1047     llvm_unreachable("Invalid opcode for post-index load/store instructions");
1048   }
1049
1050   // Decode vector list of 1/2/3/4 vectors for load instructions.
1051   if (IsLoad) {
1052     switch (NumVecs) {
1053     case 1:
1054       Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder)
1055                   : DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
1056       break;
1057     case 2:
1058       Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder)
1059                   : DecodeDPairRegisterClass(Inst, Rt, Address, Decoder);
1060       break;
1061     case 3:
1062       Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder)
1063                   : DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder);
1064       break;
1065     case 4:
1066       Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder)
1067                   : DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder);
1068       break;
1069     }
1070   }
1071
1072   // Decode write back register, which is equal to Rn.
1073   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1074   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1075
1076   if (Rm == 31) // If Rm is 0x11111, add the vector list length in byte
1077     Inst.addOperand(MCOperand::CreateImm(NumVecs * (Is128BitVec ? 16 : 8)));
1078   else // Decode Rm
1079     DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder);
1080
1081   // Decode vector list of 1/2/3/4 vectors for load instructions.
1082   if (!IsLoad) {
1083     switch (NumVecs) {
1084     case 1:
1085       Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder)
1086                   : DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
1087       break;
1088     case 2:
1089       Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder)
1090                   : DecodeDPairRegisterClass(Inst, Rt, Address, Decoder);
1091       break;
1092     case 3:
1093       Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder)
1094                   : DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder);
1095       break;
1096     case 4:
1097       Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder)
1098                   : DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder);
1099       break;
1100     }
1101   }
1102
1103   return MCDisassembler::Success;
1104 }