lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

   1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the functions necessary to decode AArch64 instruction
  11 // bitpatterns into MCInsts (with the help of TableGenerated information from
  12 // the instruction definitions).
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #define DEBUG_TYPE "arm-disassembler"
  17
  18 #include "AArch64.h"
  19 #include "AArch64RegisterInfo.h"
  20 #include "AArch64Subtarget.h"
  21 #include "Utils/AArch64BaseInfo.h"
  22 #include "llvm/MC/MCInst.h"
  23 #include "llvm/MC/MCInstrDesc.h"
  24 #include "llvm/MC/MCExpr.h"
  25 #include "llvm/MC/MCContext.h"
  26 #include "llvm/MC/MCDisassembler.h"
  27 #include "llvm/MC/MCFixedLenDisassembler.h"
  28 #include "llvm/Support/Debug.h"
  29 #include "llvm/Support/MemoryObject.h"
  30 #include "llvm/Support/ErrorHandling.h"
  31 #include "llvm/Support/TargetRegistry.h"
  32 #include "llvm/Support/raw_ostream.h"
  33
  34 using namespace llvm;
  35
  36 typedef MCDisassembler::DecodeStatus DecodeStatus;
  37
  38 namespace {
  39 /// AArch64 disassembler for all AArch64 platforms.
  40 class AArch64Disassembler : public MCDisassembler {
  41   OwningPtr<const MCRegisterInfo> RegInfo;
  42 public:
  43   /// Initializes the disassembler.
  44   ///
  45   AArch64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info)
  46     : MCDisassembler(STI), RegInfo(Info) {
  47   }
  48
  49   ~AArch64Disassembler() {}
  50
  51   /// See MCDisassembler.
  52   DecodeStatus getInstruction(MCInst &instr,
  53                               uint64_t &size,
  54                               const MemoryObject &region,
  55                               uint64_t address,
  56                               raw_ostream &vStream,
  57                               raw_ostream &cStream) const;
  58
  59   const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
  60 };
  61
  62 }
  63
  64 // Forward-declarations used in the auto-generated files.
  65 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  66                                          uint64_t Address, const void *Decoder);
  67 static DecodeStatus
  68 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  69                             uint64_t Address, const void *Decoder);
  70
  71 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  72                                          uint64_t Address, const void *Decoder);
  73 static DecodeStatus
  74 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  75                             uint64_t Address, const void *Decoder);
  76
  77 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  78                                          uint64_t Address, const void *Decoder);
  79 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  80                                          uint64_t Address, const void *Decoder);
  81 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  82                                          uint64_t Address, const void *Decoder);
  83 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  84                                          uint64_t Address, const void *Decoder);
  85 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
  86                                               unsigned RegNo, uint64_t Address,
  87                                               const void *Decoder);
  88 static DecodeStatus DecodeVPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  89                                              uint64_t Address,
  90                                              const void *Decoder);
  91 static DecodeStatus DecodeVPR128RegisterClass(llvm::MCInst &Inst,
  92                                               unsigned RegNo, uint64_t Address,
  93                                               const void *Decoder);
  94
  95 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
  96                                                unsigned OptionHiS,
  97                                                uint64_t Address,
  98                                                const void *Decoder);
  99
 100
 101 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
 102                                                unsigned Imm6Bits,
 103                                                uint64_t Address,
 104                                                const void *Decoder);
 105
 106 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
 107                                                unsigned Imm6Bits,
 108                                                uint64_t Address,
 109                                                const void *Decoder);
 110
 111 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
 112                                         unsigned RmBits,
 113                                         uint64_t Address,
 114                                         const void *Decoder);
 115
 116 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val,
 117                                          uint64_t Address, const void *Decoder);
 118 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val,
 119                                           uint64_t Address,
 120                                           const void *Decoder);
 121 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val,
 122                                           uint64_t Address,
 123                                           const void *Decoder);
 124 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val,
 125                                           uint64_t Address,
 126                                           const void *Decoder);
 127
 128 template<int RegWidth>
 129 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
 130                                              unsigned FullImm,
 131                                              uint64_t Address,
 132                                              const void *Decoder);
 133
 134 template<int RegWidth>
 135 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
 136                                             unsigned Bits,
 137                                             uint64_t Address,
 138                                             const void *Decoder);
 139
 140 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
 141                                            unsigned ShiftAmount,
 142                                            uint64_t Address,
 143                                            const void *Decoder);
 144 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
 145 static DecodeStatus
 146 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
 147                              uint64_t Address, const void *Decoder);
 148
 149 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
 150                                             unsigned ShiftAmount,
 151                                             uint64_t Address,
 152                                             const void *Decoder);
 153 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
 154                                               uint64_t Address,
 155                                               const void *Decoder);
 156
 157 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 158                                               uint64_t Address,
 159                                               const void *Decoder);
 160
 161 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
 162                                               unsigned Insn,
 163                                               uint64_t Address,
 164                                               const void *Decoder);
 165
 166 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
 167                                                        unsigned Val,
 168                                                        uint64_t Address,
 169                                                        const void *Decoder);
 170
 171 template<typename SomeNamedImmMapper>
 172 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
 173                                           unsigned Val,
 174                                           uint64_t Address,
 175                                           const void *Decoder);
 176
 177 static DecodeStatus
 178 DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper,
 179                     llvm::MCInst &Inst, unsigned Val,
 180                     uint64_t Address, const void *Decoder);
 181
 182 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
 183                                      unsigned Val,
 184                                      uint64_t Address,
 185                                      const void *Decoder);
 186
 187 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
 188                                      unsigned Val,
 189                                      uint64_t Address,
 190                                      const void *Decoder);
 191
 192
 193 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
 194                                                    unsigned Val,
 195                                                    uint64_t Address,
 196                                                    const void *Decoder);
 197
 198
 199 static bool Check(DecodeStatus &Out, DecodeStatus In);
 200
 201 #include "AArch64GenDisassemblerTables.inc"
 202 #include "AArch64GenInstrInfo.inc"
 203
 204 static bool Check(DecodeStatus &Out, DecodeStatus In) {
 205   switch (In) {
 206     case MCDisassembler::Success:
 207       // Out stays the same.
 208       return true;
 209     case MCDisassembler::SoftFail:
 210       Out = In;
 211       return true;
 212     case MCDisassembler::Fail:
 213       Out = In;
 214       return false;
 215   }
 216   llvm_unreachable("Invalid DecodeStatus!");
 217 }
 218
 219 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
 220                                                  const MemoryObject &Region,
 221                                                  uint64_t Address,
 222                                                  raw_ostream &os,
 223                                                  raw_ostream &cs) const {
 224   CommentStream = &cs;
 225
 226   uint8_t bytes[4];
 227
 228   // We want to read exactly 4 bytes of data.
 229   if (Region.readBytes(Address, 4, bytes) == -1) {
 230     Size = 0;
 231     return MCDisassembler::Fail;
 232   }
 233
 234   // Encoded as a small-endian 32-bit word in the stream.
 235   uint32_t insn = (bytes[3] << 24) |
 236     (bytes[2] << 16) |
 237     (bytes[1] <<  8) |
 238     (bytes[0] <<  0);
 239
 240   // Calling the auto-generated decoder function.
 241   DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address,
 242                                           this, STI);
 243   if (result != MCDisassembler::Fail) {
 244     Size = 4;
 245     return result;
 246   }
 247
 248   MI.clear();
 249   Size = 0;
 250   return MCDisassembler::Fail;
 251 }
 252
 253 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 254   const AArch64Disassembler *Dis = static_cast<const AArch64Disassembler*>(D);
 255   return Dis->getRegInfo()->getRegClass(RC).getRegister(RegNo);
 256 }
 257
 258 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 259                                         uint64_t Address, const void *Decoder) {
 260   if (RegNo > 31)
 261     return MCDisassembler::Fail;
 262
 263   uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo);
 264   Inst.addOperand(MCOperand::CreateReg(Register));
 265   return MCDisassembler::Success;
 266 }
 267
 268 static DecodeStatus
 269 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 270                             uint64_t Address, const void *Decoder) {
 271   if (RegNo > 31)
 272     return MCDisassembler::Fail;
 273
 274   uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo);
 275   Inst.addOperand(MCOperand::CreateReg(Register));
 276   return MCDisassembler::Success;
 277 }
 278
 279 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 280                                              uint64_t Address,
 281                                              const void *Decoder) {
 282   if (RegNo > 31)
 283     return MCDisassembler::Fail;
 284
 285   uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo);
 286   Inst.addOperand(MCOperand::CreateReg(Register));
 287   return MCDisassembler::Success;
 288 }
 289
 290 static DecodeStatus
 291 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 292                             uint64_t Address, const void *Decoder) {
 293   if (RegNo > 31)
 294     return MCDisassembler::Fail;
 295
 296   uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo);
 297   Inst.addOperand(MCOperand::CreateReg(Register));
 298   return MCDisassembler::Success;
 299 }
 300
 301 static DecodeStatus
 302 DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 303                             uint64_t Address, const void *Decoder) {
 304   if (RegNo > 31)
 305     return MCDisassembler::Fail;
 306
 307   uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo);
 308   Inst.addOperand(MCOperand::CreateReg(Register));
 309   return MCDisassembler::Success;
 310 }
 311
 312 static DecodeStatus
 313 DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 314                             uint64_t Address, const void *Decoder) {
 315   if (RegNo > 31)
 316     return MCDisassembler::Fail;
 317
 318   uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo);
 319   Inst.addOperand(MCOperand::CreateReg(Register));
 320   return MCDisassembler::Success;
 321 }
 322
 323
 324 static DecodeStatus
 325 DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 326                             uint64_t Address, const void *Decoder) {
 327   if (RegNo > 31)
 328     return MCDisassembler::Fail;
 329
 330   uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo);
 331   Inst.addOperand(MCOperand::CreateReg(Register));
 332   return MCDisassembler::Success;
 333 }
 334
 335 static DecodeStatus
 336 DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 337                             uint64_t Address, const void *Decoder) {
 338   if (RegNo > 31)
 339     return MCDisassembler::Fail;
 340
 341   uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo);
 342   Inst.addOperand(MCOperand::CreateReg(Register));
 343   return MCDisassembler::Success;
 344 }
 345
 346
 347 static DecodeStatus
 348 DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 349                             uint64_t Address, const void *Decoder) {
 350   if (RegNo > 31)
 351     return MCDisassembler::Fail;
 352
 353   uint16_t Register = getReg(Decoder, AArch64::FPR128RegClassID, RegNo);
 354   Inst.addOperand(MCOperand::CreateReg(Register));
 355   return MCDisassembler::Success;
 356 }
 357
 358 static DecodeStatus DecodeVPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 359                                              uint64_t Address,
 360                                              const void *Decoder) {
 361   if (RegNo > 31)
 362     return MCDisassembler::Fail;
 363
 364   uint16_t Register = getReg(Decoder, AArch64::VPR64RegClassID, RegNo);
 365   Inst.addOperand(MCOperand::CreateReg(Register));
 366   return MCDisassembler::Success;
 367 }
 368
 369 static DecodeStatus
 370 DecodeVPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 371                                                   uint64_t Address, const void *Decoder) {
 372   if (RegNo > 31)
 373     return MCDisassembler::Fail;
 374
 375   uint16_t Register = getReg(Decoder, AArch64::VPR128RegClassID, RegNo);
 376   Inst.addOperand(MCOperand::CreateReg(Register));
 377   return MCDisassembler::Success;
 378 }
 379
 380 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
 381                                                unsigned OptionHiS,
 382                                                uint64_t Address,
 383                                                const void *Decoder) {
 384   // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1},
 385   // S}. Hence we want to check bit 1.
 386   if (!(OptionHiS & 2))
 387     return MCDisassembler::Fail;
 388
 389   Inst.addOperand(MCOperand::CreateImm(OptionHiS));
 390   return MCDisassembler::Success;
 391 }
 392
 393 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
 394                                                unsigned Imm6Bits,
 395                                                uint64_t Address,
 396                                                const void *Decoder) {
 397   // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be
 398   // between 0 and 31.
 399   if (Imm6Bits > 31)
 400     return MCDisassembler::Fail;
 401
 402   Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
 403   return MCDisassembler::Success;
 404 }
 405
 406 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
 407                                                unsigned Imm6Bits,
 408                                                uint64_t Address,
 409                                                const void *Decoder) {
 410   // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32.
 411   if (Imm6Bits < 32)
 412     return MCDisassembler::Fail;
 413
 414   Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
 415   return MCDisassembler::Success;
 416 }
 417
 418 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
 419                                         unsigned RmBits,
 420                                         uint64_t Address,
 421                                         const void *Decoder) {
 422   // Any bits are valid in the instruction (they're architecturally ignored),
 423   // but a code generator should insert 0.
 424   Inst.addOperand(MCOperand::CreateImm(0));
 425   return MCDisassembler::Success;
 426 }
 427
 428 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val,
 429                                          uint64_t Address,
 430                                          const void *Decoder) {
 431   Inst.addOperand(MCOperand::CreateImm(8 - Val));
 432   return MCDisassembler::Success;
 433 }
 434
 435 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val,
 436                                           uint64_t Address,
 437                                           const void *Decoder) {
 438   Inst.addOperand(MCOperand::CreateImm(16 - Val));
 439   return MCDisassembler::Success;
 440 }
 441
 442 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val,
 443                                           uint64_t Address,
 444                                           const void *Decoder) {
 445   Inst.addOperand(MCOperand::CreateImm(32 - Val));
 446   return MCDisassembler::Success;
 447 }
 448
 449 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val,
 450                                           uint64_t Address,
 451                                           const void *Decoder) {
 452   Inst.addOperand(MCOperand::CreateImm(64 - Val));
 453   return MCDisassembler::Success;
 454 }
 455
 456 template<int RegWidth>
 457 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
 458                                              unsigned FullImm,
 459                                              uint64_t Address,
 460                                              const void *Decoder) {
 461   unsigned Imm16 = FullImm & 0xffff;
 462   unsigned Shift = FullImm >> 16;
 463
 464   if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail;
 465
 466   Inst.addOperand(MCOperand::CreateImm(Imm16));
 467   Inst.addOperand(MCOperand::CreateImm(Shift));
 468   return MCDisassembler::Success;
 469 }
 470
 471 template<int RegWidth>
 472 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
 473                                             unsigned Bits,
 474                                             uint64_t Address,
 475                                             const void *Decoder) {
 476   uint64_t Imm;
 477   if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm))
 478     return MCDisassembler::Fail;
 479
 480   Inst.addOperand(MCOperand::CreateImm(Bits));
 481   return MCDisassembler::Success;
 482 }
 483
 484
 485 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
 486                                            unsigned ShiftAmount,
 487                                            uint64_t Address,
 488                                            const void *Decoder) {
 489   // Only values 0-4 are valid for this 3-bit field
 490   if (ShiftAmount > 4)
 491     return MCDisassembler::Fail;
 492
 493   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 494   return MCDisassembler::Success;
 495 }
 496
 497 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
 498                                             unsigned ShiftAmount,
 499                                             uint64_t Address,
 500                                             const void *Decoder) {
 501   // Only values below 32 are valid for a 32-bit register
 502   if (ShiftAmount > 31)
 503     return MCDisassembler::Fail;
 504
 505   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 506   return MCDisassembler::Success;
 507 }
 508
 509 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
 510                                               uint64_t Address,
 511                                               const void *Decoder) {
 512   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 513   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 514   unsigned ImmS = fieldFromInstruction(Insn, 10, 6);
 515   unsigned ImmR = fieldFromInstruction(Insn, 16, 6);
 516   unsigned SF = fieldFromInstruction(Insn, 31, 1);
 517
 518   // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise
 519   // out assertions that it thinks should never be hit.
 520   enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc;
 521   Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2);
 522
 523   if (!SF) {
 524     // ImmR and ImmS must be between 0 and 31 for 32-bit instructions.
 525     if (ImmR > 31 || ImmS > 31)
 526       return MCDisassembler::Fail;
 527   }
 528
 529   if (SF) {
 530     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 531     // BFM MCInsts use Rd as a source too.
 532     if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 533     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 534   } else {
 535     DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
 536     // BFM MCInsts use Rd as a source too.
 537     if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
 538     DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
 539   }
 540
 541   // ASR and LSR have more specific patterns so they won't get here:
 542   assert(!(ImmS == 31 && !SF && Opc != BFM)
 543          && "shift should have used auto decode");
 544   assert(!(ImmS == 63 && SF && Opc != BFM)
 545          && "shift should have used auto decode");
 546
 547   // Extension instructions similarly:
 548   if (Opc == SBFM && ImmR == 0) {
 549     assert((ImmS != 7 && ImmS != 15) && "extension got here");
 550     assert((ImmS != 31 || SF == 0) && "extension got here");
 551   } else if (Opc == UBFM && ImmR == 0) {
 552     assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here");
 553   }
 554
 555   if (Opc == UBFM) {
 556     // It might be a LSL instruction, which actually takes the shift amount
 557     // itself as an MCInst operand.
 558     if (SF && (ImmS + 1) % 64 == ImmR) {
 559       Inst.setOpcode(AArch64::LSLxxi);
 560       Inst.addOperand(MCOperand::CreateImm(63 - ImmS));
 561       return MCDisassembler::Success;
 562     } else if (!SF && (ImmS + 1) % 32 == ImmR) {
 563       Inst.setOpcode(AArch64::LSLwwi);
 564       Inst.addOperand(MCOperand::CreateImm(31 - ImmS));
 565       return MCDisassembler::Success;
 566     }
 567   }
 568
 569   // Otherwise it's definitely either an extract or an insert depending on which
 570   // of ImmR or ImmS is larger.
 571   unsigned ExtractOp, InsertOp;
 572   switch (Opc) {
 573   default: llvm_unreachable("unexpected instruction trying to decode bitfield");
 574   case SBFM:
 575     ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii;
 576     InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii;
 577     break;
 578   case BFM:
 579     ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii;
 580     InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii;
 581     break;
 582   case UBFM:
 583     ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii;
 584     InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii;
 585     break;
 586   }
 587
 588   // Otherwise it's a boring insert or extract
 589   Inst.addOperand(MCOperand::CreateImm(ImmR));
 590   Inst.addOperand(MCOperand::CreateImm(ImmS));
 591
 592
 593   if (ImmS < ImmR)
 594     Inst.setOpcode(InsertOp);
 595   else
 596     Inst.setOpcode(ExtractOp);
 597
 598   return MCDisassembler::Success;
 599 }
 600
 601 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 602                                               uint64_t Address,
 603                                               const void *Decoder) {
 604   // This decoder exists to add the dummy Lane operand to the MCInst, which must
 605   // be 1 in assembly but has no other real manifestation.
 606   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 607   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 608   unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
 609
 610   if (IsToVec) {
 611     DecodeVPR128RegisterClass(Inst, Rd, Address, Decoder);
 612     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 613   } else {
 614     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 615     DecodeVPR128RegisterClass(Inst, Rn, Address, Decoder);
 616   }
 617
 618   // Add the lane
 619   Inst.addOperand(MCOperand::CreateImm(1));
 620
 621   return MCDisassembler::Success;
 622 }
 623
 624
 625 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
 626                                               unsigned Insn,
 627                                               uint64_t Address,
 628                                               const void *Decoder) {
 629   DecodeStatus Result = MCDisassembler::Success;
 630   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
 631   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 632   unsigned Rt2 = fieldFromInstruction(Insn, 10, 5);
 633   unsigned SImm7 = fieldFromInstruction(Insn, 15, 7);
 634   unsigned L = fieldFromInstruction(Insn, 22, 1);
 635   unsigned V = fieldFromInstruction(Insn, 26, 1);
 636   unsigned Opc = fieldFromInstruction(Insn, 30, 2);
 637
 638   // Not an official name, but it turns out that bit 23 distinguishes indexed
 639   // from non-indexed operations.
 640   unsigned Indexed = fieldFromInstruction(Insn, 23, 1);
 641
 642   if (Indexed && L == 0) {
 643     // The MCInst for an indexed store has an out operand and 4 ins:
 644     //    Rn_wb, Rt, Rt2, Rn, Imm
 645     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 646   }
 647
 648   // You shouldn't load to the same register twice in an instruction...
 649   if (L && Rt == Rt2)
 650     Result = MCDisassembler::SoftFail;
 651
 652   // ... or do any operation that writes-back to a transfer register. But note
 653   // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
 654   if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn))
 655     Result = MCDisassembler::SoftFail;
 656
 657   // Exactly how we decode the MCInst's registers depends on the Opc and V
 658   // fields of the instruction. These also obviously determine the size of the
 659   // operation so we can fill in that information while we're at it.
 660   if (V) {
 661     // The instruction operates on the FP/SIMD registers
 662     switch (Opc) {
 663     default: return MCDisassembler::Fail;
 664     case 0:
 665       DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
 666       DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder);
 667       break;
 668     case 1:
 669       DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
 670       DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder);
 671       break;
 672     case 2:
 673       DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
 674       DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder);
 675       break;
 676     }
 677   } else {
 678     switch (Opc) {
 679     default: return MCDisassembler::Fail;
 680     case 0:
 681       DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
 682       DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder);
 683       break;
 684     case 1:
 685       assert(L && "unexpected \"store signed\" attempt");
 686       DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 687       DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
 688       break;
 689     case 2:
 690       DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 691       DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
 692       break;
 693     }
 694   }
 695
 696   if (Indexed && L == 1) {
 697     // The MCInst for an indexed load has 3 out operands and an 3 ins:
 698     //    Rt, Rt2, Rn_wb, Rt2, Rn, Imm
 699     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 700   }
 701
 702
 703   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 704   Inst.addOperand(MCOperand::CreateImm(SImm7));
 705
 706   return Result;
 707 }
 708
 709 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
 710                                                        uint32_t Val,
 711                                                        uint64_t Address,
 712                                                        const void *Decoder) {
 713   unsigned Rt = fieldFromInstruction(Val, 0, 5);
 714   unsigned Rn = fieldFromInstruction(Val, 5, 5);
 715   unsigned Rt2 = fieldFromInstruction(Val, 10, 5);
 716   unsigned MemSize = fieldFromInstruction(Val, 30, 2);
 717
 718   DecodeStatus S = MCDisassembler::Success;
 719   if (Rt == Rt2) S = MCDisassembler::SoftFail;
 720
 721   switch (MemSize) {
 722     case 2:
 723       if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder)))
 724         return MCDisassembler::Fail;
 725       if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder)))
 726         return MCDisassembler::Fail;
 727       break;
 728     case 3:
 729       if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder)))
 730         return MCDisassembler::Fail;
 731       if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder)))
 732         return MCDisassembler::Fail;
 733       break;
 734     default:
 735       llvm_unreachable("Invalid MemSize in DecodeLoadPairExclusiveInstruction");
 736   }
 737
 738   if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder)))
 739     return MCDisassembler::Fail;
 740
 741   return S;
 742 }
 743
 744 template<typename SomeNamedImmMapper>
 745 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
 746                                           unsigned Val,
 747                                           uint64_t Address,
 748                                           const void *Decoder) {
 749   SomeNamedImmMapper Mapper;
 750   bool ValidNamed;
 751   Mapper.toString(Val, ValidNamed);
 752   if (ValidNamed || Mapper.validImm(Val)) {
 753     Inst.addOperand(MCOperand::CreateImm(Val));
 754     return MCDisassembler::Success;
 755   }
 756
 757   return MCDisassembler::Fail;
 758 }
 759
 760 static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
 761                                         llvm::MCInst &Inst,
 762                                         unsigned Val,
 763                                         uint64_t Address,
 764                                         const void *Decoder) {
 765   bool ValidNamed;
 766   Mapper.toString(Val, ValidNamed);
 767
 768   Inst.addOperand(MCOperand::CreateImm(Val));
 769
 770   return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail;
 771 }
 772
 773 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
 774                                      unsigned Val,
 775                                      uint64_t Address,
 776                                      const void *Decoder) {
 777   return DecodeSysRegOperand(A64SysReg::MRSMapper(), Inst, Val, Address,
 778                              Decoder);
 779 }
 780
 781 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
 782                                      unsigned Val,
 783                                      uint64_t Address,
 784                                      const void *Decoder) {
 785   return DecodeSysRegOperand(A64SysReg::MSRMapper(), Inst, Val, Address,
 786                              Decoder);
 787 }
 788
 789 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
 790                                                    unsigned Insn,
 791                                                    uint64_t Address,
 792                                                    const void *Decoder) {
 793   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
 794   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 795   unsigned Imm9 = fieldFromInstruction(Insn, 12, 9);
 796
 797   unsigned Opc = fieldFromInstruction(Insn, 22, 2);
 798   unsigned V = fieldFromInstruction(Insn, 26, 1);
 799   unsigned Size = fieldFromInstruction(Insn, 30, 2);
 800
 801   if (Opc == 0 || (V == 1 && Opc == 2)) {
 802     // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm
 803     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 804   }
 805
 806   if (V == 0 && (Opc == 2 || Size == 3)) {
 807     DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 808   } else if (V == 0) {
 809     DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
 810   } else if (V == 1 && (Opc & 2)) {
 811     DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
 812   } else {
 813     switch (Size) {
 814     case 0:
 815       DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder);
 816       break;
 817     case 1:
 818       DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder);
 819       break;
 820     case 2:
 821       DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
 822       break;
 823     case 3:
 824       DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
 825       break;
 826     }
 827   }
 828
 829   if (Opc != 0 && (V != 1 || Opc != 2)) {
 830     // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm
 831     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 832   }
 833
 834   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 835
 836   Inst.addOperand(MCOperand::CreateImm(Imm9));
 837
 838   // N.b. The official documentation says undpredictable if Rt == Rn, but this
 839   // takes place at the architectural rather than encoding level:
 840   //
 841   // "STR xzr, [sp], #4" is perfectly valid.
 842   if (V == 0 && Rt == Rn && Rn != 31)
 843     return MCDisassembler::SoftFail;
 844   else
 845     return MCDisassembler::Success;
 846 }
 847
 848 static MCDisassembler *createAArch64Disassembler(const Target &T,
 849                                                  const MCSubtargetInfo &STI) {
 850   return new AArch64Disassembler(STI, T.createMCRegInfo(""));
 851 }
 852
 853 extern "C" void LLVMInitializeAArch64Disassembler() {
 854   TargetRegistry::RegisterMCDisassembler(TheAArch64Target,
 855                                          createAArch64Disassembler);
 856 }
 857
 858 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
 859 static DecodeStatus
 860 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
 861                              uint64_t Address, const void *Decoder) {
 862   bool IsLSL = false;
 863   if (Ext == A64SE::LSL)
 864     IsLSL = true;
 865   else if (Ext != A64SE::MSL)
 866     return MCDisassembler::Fail;
 867
 868   // MSL and LSLH accepts encoded shift amount 0 or 1.
 869   if ((!IsLSL || (IsLSL && IsHalf)) && ShiftAmount != 0 && ShiftAmount != 1)
 870     return MCDisassembler::Fail;
 871
 872   // LSL  accepts encoded shift amount 0, 1, 2 or 3.
 873   if (IsLSL && ShiftAmount > 3)
 874     return MCDisassembler::Fail;
 875
 876   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 877   return MCDisassembler::Success;
 878 }