1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the functions necessary to decode AArch64 instruction
11 // bitpatterns into MCInsts (with the help of TableGenerated information from
12 // the instruction definitions).
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "arm-disassembler"
19 #include "AArch64RegisterInfo.h"
20 #include "AArch64Subtarget.h"
21 #include "Utils/AArch64BaseInfo.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCDisassembler.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCFixedLenDisassembler.h"
26 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MemoryObject.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Support/raw_ostream.h"
36 typedef MCDisassembler::DecodeStatus DecodeStatus;
39 /// AArch64 disassembler for all AArch64 platforms.
40 class AArch64Disassembler : public MCDisassembler {
42 /// Initializes the disassembler.
44 AArch64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
45 : MCDisassembler(STI, Ctx) {
48 ~AArch64Disassembler() {}
50 /// See MCDisassembler.
51 DecodeStatus getInstruction(MCInst &instr,
53 const MemoryObject ®ion,
56 raw_ostream &cStream) const;
61 // Forward-declarations used in the auto-generated files.
62 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
63 uint64_t Address, const void *Decoder);
65 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
66 uint64_t Address, const void *Decoder);
68 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
69 uint64_t Address, const void *Decoder);
71 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
72 uint64_t Address, const void *Decoder);
74 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
75 uint64_t Address, const void *Decoder);
76 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
77 uint64_t Address, const void *Decoder);
78 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
79 uint64_t Address, const void *Decoder);
80 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
81 uint64_t Address, const void *Decoder);
82 static DecodeStatus DecodeFPR64LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
83 uint64_t Address, const void *Decoder);
84 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
85 unsigned RegNo, uint64_t Address,
87 static DecodeStatus DecodeFPR128LoRegisterClass(llvm::MCInst &Inst,
88 unsigned RegNo, uint64_t Address,
91 static DecodeStatus DecodeGPR64noxzrRegisterClass(llvm::MCInst &Inst,
96 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
99 static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
101 const void *Decoder);
102 static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst,
103 unsigned RegNo, uint64_t Address,
104 const void *Decoder);
105 static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst,
106 unsigned RegNo, uint64_t Address,
107 const void *Decoder);
108 static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
110 const void *Decoder);
111 static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
113 const void *Decoder);
115 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
118 const void *Decoder);
121 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
124 const void *Decoder);
126 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
129 const void *Decoder);
131 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
134 const void *Decoder);
136 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val,
137 uint64_t Address, const void *Decoder);
138 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val,
140 const void *Decoder);
141 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val,
143 const void *Decoder);
144 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val,
146 const void *Decoder);
148 static DecodeStatus DecodeShiftLeftImm8(MCInst &Inst, unsigned Val,
149 uint64_t Address, const void *Decoder);
150 static DecodeStatus DecodeShiftLeftImm16(MCInst &Inst, unsigned Val,
152 const void *Decoder);
153 static DecodeStatus DecodeShiftLeftImm32(MCInst &Inst, unsigned Val,
155 const void *Decoder);
156 static DecodeStatus DecodeShiftLeftImm64(MCInst &Inst, unsigned Val,
158 const void *Decoder);
160 template<int RegWidth>
161 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
164 const void *Decoder);
166 template<int RegWidth>
167 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
170 const void *Decoder);
172 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
173 unsigned ShiftAmount,
175 const void *Decoder);
176 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
178 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
179 uint64_t Address, const void *Decoder);
181 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
182 unsigned ShiftAmount,
184 const void *Decoder);
185 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
187 const void *Decoder);
189 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
191 const void *Decoder);
193 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
196 const void *Decoder);
198 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
201 const void *Decoder);
203 template<typename SomeNamedImmMapper>
204 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
207 const void *Decoder);
210 DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper,
211 llvm::MCInst &Inst, unsigned Val,
212 uint64_t Address, const void *Decoder);
214 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
217 const void *Decoder);
219 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
222 const void *Decoder);
225 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
228 const void *Decoder);
230 static DecodeStatus DecodeVLDSTPostInstruction(MCInst &Inst, unsigned Val,
232 const void *Decoder);
234 static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
236 const void *Decoder);
238 static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn,
240 const void *Decoder);
242 static bool Check(DecodeStatus &Out, DecodeStatus In);
244 #include "AArch64GenDisassemblerTables.inc"
246 static bool Check(DecodeStatus &Out, DecodeStatus In) {
248 case MCDisassembler::Success:
249 // Out stays the same.
251 case MCDisassembler::SoftFail:
254 case MCDisassembler::Fail:
258 llvm_unreachable("Invalid DecodeStatus!");
261 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
262 const MemoryObject &Region,
265 raw_ostream &cs) const {
270 // We want to read exactly 4 bytes of data.
271 if (Region.readBytes(Address, 4, bytes) == -1) {
273 return MCDisassembler::Fail;
276 // Encoded as a small-endian 32-bit word in the stream.
277 uint32_t insn = (bytes[3] << 24) |
282 // Calling the auto-generated decoder function.
283 DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address,
285 if (result != MCDisassembler::Fail) {
292 return MCDisassembler::Fail;
295 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
296 const AArch64Disassembler *Dis = static_cast<const AArch64Disassembler*>(D);
297 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
298 return RegInfo->getRegClass(RC).getRegister(RegNo);
301 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
302 uint64_t Address, const void *Decoder) {
304 return MCDisassembler::Fail;
306 uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo);
307 Inst.addOperand(MCOperand::CreateReg(Register));
308 return MCDisassembler::Success;
312 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
313 uint64_t Address, const void *Decoder) {
315 return MCDisassembler::Fail;
317 uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo);
318 Inst.addOperand(MCOperand::CreateReg(Register));
319 return MCDisassembler::Success;
322 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
324 const void *Decoder) {
326 return MCDisassembler::Fail;
328 uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo);
329 Inst.addOperand(MCOperand::CreateReg(Register));
330 return MCDisassembler::Success;
334 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
335 uint64_t Address, const void *Decoder) {
337 return MCDisassembler::Fail;
339 uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo);
340 Inst.addOperand(MCOperand::CreateReg(Register));
341 return MCDisassembler::Success;
345 DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
346 uint64_t Address, const void *Decoder) {
348 return MCDisassembler::Fail;
350 uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo);
351 Inst.addOperand(MCOperand::CreateReg(Register));
352 return MCDisassembler::Success;
356 DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
357 uint64_t Address, const void *Decoder) {
359 return MCDisassembler::Fail;
361 uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo);
362 Inst.addOperand(MCOperand::CreateReg(Register));
363 return MCDisassembler::Success;
368 DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
369 uint64_t Address, const void *Decoder) {
371 return MCDisassembler::Fail;
373 uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo);
374 Inst.addOperand(MCOperand::CreateReg(Register));
375 return MCDisassembler::Success;
379 DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
380 uint64_t Address, const void *Decoder) {
382 return MCDisassembler::Fail;
384 uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo);
385 Inst.addOperand(MCOperand::CreateReg(Register));
386 return MCDisassembler::Success;
390 DecodeFPR64LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
391 uint64_t Address, const void *Decoder) {
393 return MCDisassembler::Fail;
395 return DecodeFPR64RegisterClass(Inst, RegNo, Address, Decoder);
399 DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
400 uint64_t Address, const void *Decoder) {
402 return MCDisassembler::Fail;
404 uint16_t Register = getReg(Decoder, AArch64::FPR128RegClassID, RegNo);
405 Inst.addOperand(MCOperand::CreateReg(Register));
406 return MCDisassembler::Success;
410 DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
411 uint64_t Address, const void *Decoder) {
413 return MCDisassembler::Fail;
415 return DecodeFPR128RegisterClass(Inst, RegNo, Address, Decoder);
418 static DecodeStatus DecodeGPR64noxzrRegisterClass(llvm::MCInst &Inst,
421 const void *Decoder) {
423 return MCDisassembler::Fail;
425 uint16_t Register = getReg(Decoder, AArch64::GPR64noxzrRegClassID, RegNo);
426 Inst.addOperand(MCOperand::CreateReg(Register));
427 return MCDisassembler::Success;
430 static DecodeStatus DecodeRegisterClassByID(llvm::MCInst &Inst, unsigned RegNo,
432 const void *Decoder) {
434 return MCDisassembler::Fail;
436 uint16_t Register = getReg(Decoder, RegID, RegNo);
437 Inst.addOperand(MCOperand::CreateReg(Register));
438 return MCDisassembler::Success;
441 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
443 const void *Decoder) {
444 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DPairRegClassID,
448 static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
450 const void *Decoder) {
451 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QPairRegClassID,
455 static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst,
456 unsigned RegNo, uint64_t Address,
457 const void *Decoder) {
458 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DTripleRegClassID,
462 static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst,
463 unsigned RegNo, uint64_t Address,
464 const void *Decoder) {
465 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QTripleRegClassID,
469 static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
471 const void *Decoder) {
472 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DQuadRegClassID,
476 static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
478 const void *Decoder) {
479 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QQuadRegClassID,
483 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
486 const void *Decoder) {
487 // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1},
488 // S}. Hence we want to check bit 1.
489 if (!(OptionHiS & 2))
490 return MCDisassembler::Fail;
492 Inst.addOperand(MCOperand::CreateImm(OptionHiS));
493 return MCDisassembler::Success;
496 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
499 const void *Decoder) {
500 // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be
503 return MCDisassembler::Fail;
505 Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
506 return MCDisassembler::Success;
509 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
512 const void *Decoder) {
513 // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32.
515 return MCDisassembler::Fail;
517 Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
518 return MCDisassembler::Success;
521 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
524 const void *Decoder) {
525 // Any bits are valid in the instruction (they're architecturally ignored),
526 // but a code generator should insert 0.
527 Inst.addOperand(MCOperand::CreateImm(0));
528 return MCDisassembler::Success;
531 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val,
533 const void *Decoder) {
534 Inst.addOperand(MCOperand::CreateImm(8 - Val));
535 return MCDisassembler::Success;
538 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val,
540 const void *Decoder) {
541 Inst.addOperand(MCOperand::CreateImm(16 - Val));
542 return MCDisassembler::Success;
545 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val,
547 const void *Decoder) {
548 Inst.addOperand(MCOperand::CreateImm(32 - Val));
549 return MCDisassembler::Success;
552 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val,
554 const void *Decoder) {
555 Inst.addOperand(MCOperand::CreateImm(64 - Val));
556 return MCDisassembler::Success;
559 static DecodeStatus DecodeShiftLeftImm8(MCInst &Inst, unsigned Val,
561 const void *Decoder) {
563 return MCDisassembler::Fail;
565 Inst.addOperand(MCOperand::CreateImm(Val));
566 return MCDisassembler::Success;
569 static DecodeStatus DecodeShiftLeftImm16(MCInst &Inst, unsigned Val,
571 const void *Decoder) {
573 return MCDisassembler::Fail;
575 Inst.addOperand(MCOperand::CreateImm(Val));
576 return MCDisassembler::Success;
579 static DecodeStatus DecodeShiftLeftImm32(MCInst &Inst, unsigned Val,
581 const void *Decoder) {
583 return MCDisassembler::Fail;
585 Inst.addOperand(MCOperand::CreateImm(Val));
586 return MCDisassembler::Success;
589 static DecodeStatus DecodeShiftLeftImm64(MCInst &Inst, unsigned Val,
591 const void *Decoder) {
593 return MCDisassembler::Fail;
595 Inst.addOperand(MCOperand::CreateImm(Val));
596 return MCDisassembler::Success;
599 template<int RegWidth>
600 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
603 const void *Decoder) {
604 unsigned Imm16 = FullImm & 0xffff;
605 unsigned Shift = FullImm >> 16;
607 if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail;
609 Inst.addOperand(MCOperand::CreateImm(Imm16));
610 Inst.addOperand(MCOperand::CreateImm(Shift));
611 return MCDisassembler::Success;
614 template<int RegWidth>
615 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
618 const void *Decoder) {
620 if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm))
621 return MCDisassembler::Fail;
623 Inst.addOperand(MCOperand::CreateImm(Bits));
624 return MCDisassembler::Success;
628 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
629 unsigned ShiftAmount,
631 const void *Decoder) {
632 // Only values 0-4 are valid for this 3-bit field
634 return MCDisassembler::Fail;
636 Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
637 return MCDisassembler::Success;
640 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
641 unsigned ShiftAmount,
643 const void *Decoder) {
644 // Only values below 32 are valid for a 32-bit register
645 if (ShiftAmount > 31)
646 return MCDisassembler::Fail;
648 Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
649 return MCDisassembler::Success;
652 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
654 const void *Decoder) {
655 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
656 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
657 unsigned ImmS = fieldFromInstruction(Insn, 10, 6);
658 unsigned ImmR = fieldFromInstruction(Insn, 16, 6);
659 unsigned SF = fieldFromInstruction(Insn, 31, 1);
661 // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise
662 // out assertions that it thinks should never be hit.
663 enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc;
664 Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2);
667 // ImmR and ImmS must be between 0 and 31 for 32-bit instructions.
668 if (ImmR > 31 || ImmS > 31)
669 return MCDisassembler::Fail;
673 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
674 // BFM MCInsts use Rd as a source too.
675 if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
676 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
678 DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
679 // BFM MCInsts use Rd as a source too.
680 if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
681 DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
684 // ASR and LSR have more specific patterns so they won't get here:
685 assert(!(ImmS == 31 && !SF && Opc != BFM)
686 && "shift should have used auto decode");
687 assert(!(ImmS == 63 && SF && Opc != BFM)
688 && "shift should have used auto decode");
690 // Extension instructions similarly:
691 if (Opc == SBFM && ImmR == 0) {
692 assert((ImmS != 7 && ImmS != 15) && "extension got here");
693 assert((ImmS != 31 || SF == 0) && "extension got here");
694 } else if (Opc == UBFM && ImmR == 0) {
695 assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here");
699 // It might be a LSL instruction, which actually takes the shift amount
700 // itself as an MCInst operand.
701 if (SF && (ImmS + 1) % 64 == ImmR) {
702 Inst.setOpcode(AArch64::LSLxxi);
703 Inst.addOperand(MCOperand::CreateImm(63 - ImmS));
704 return MCDisassembler::Success;
705 } else if (!SF && (ImmS + 1) % 32 == ImmR) {
706 Inst.setOpcode(AArch64::LSLwwi);
707 Inst.addOperand(MCOperand::CreateImm(31 - ImmS));
708 return MCDisassembler::Success;
712 // Otherwise it's definitely either an extract or an insert depending on which
713 // of ImmR or ImmS is larger.
714 unsigned ExtractOp, InsertOp;
716 default: llvm_unreachable("unexpected instruction trying to decode bitfield");
718 ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii;
719 InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii;
722 ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii;
723 InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii;
726 ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii;
727 InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii;
731 // Otherwise it's a boring insert or extract
732 Inst.addOperand(MCOperand::CreateImm(ImmR));
733 Inst.addOperand(MCOperand::CreateImm(ImmS));
737 Inst.setOpcode(InsertOp);
739 Inst.setOpcode(ExtractOp);
741 return MCDisassembler::Success;
744 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
746 const void *Decoder) {
747 // This decoder exists to add the dummy Lane operand to the MCInst, which must
748 // be 1 in assembly but has no other real manifestation.
749 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
750 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
751 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
754 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
755 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
757 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
758 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
762 Inst.addOperand(MCOperand::CreateImm(1));
764 return MCDisassembler::Success;
768 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
771 const void *Decoder) {
772 DecodeStatus Result = MCDisassembler::Success;
773 unsigned Rt = fieldFromInstruction(Insn, 0, 5);
774 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
775 unsigned Rt2 = fieldFromInstruction(Insn, 10, 5);
776 unsigned SImm7 = fieldFromInstruction(Insn, 15, 7);
777 unsigned L = fieldFromInstruction(Insn, 22, 1);
778 unsigned V = fieldFromInstruction(Insn, 26, 1);
779 unsigned Opc = fieldFromInstruction(Insn, 30, 2);
781 // Not an official name, but it turns out that bit 23 distinguishes indexed
782 // from non-indexed operations.
783 unsigned Indexed = fieldFromInstruction(Insn, 23, 1);
785 if (Indexed && L == 0) {
786 // The MCInst for an indexed store has an out operand and 4 ins:
787 // Rn_wb, Rt, Rt2, Rn, Imm
788 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
791 // You shouldn't load to the same register twice in an instruction...
793 Result = MCDisassembler::SoftFail;
795 // ... or do any operation that writes-back to a transfer register. But note
796 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
797 if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn))
798 Result = MCDisassembler::SoftFail;
800 // Exactly how we decode the MCInst's registers depends on the Opc and V
801 // fields of the instruction. These also obviously determine the size of the
802 // operation so we can fill in that information while we're at it.
804 // The instruction operates on the FP/SIMD registers
806 default: return MCDisassembler::Fail;
808 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
809 DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder);
812 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
813 DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder);
816 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
817 DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder);
822 default: return MCDisassembler::Fail;
824 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
825 DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder);
828 assert(L && "unexpected \"store signed\" attempt");
829 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
830 DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
833 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
834 DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
839 if (Indexed && L == 1) {
840 // The MCInst for an indexed load has 3 out operands and an 3 ins:
841 // Rt, Rt2, Rn_wb, Rt2, Rn, Imm
842 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
846 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
847 Inst.addOperand(MCOperand::CreateImm(SImm7));
852 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
855 const void *Decoder) {
856 unsigned Rt = fieldFromInstruction(Val, 0, 5);
857 unsigned Rn = fieldFromInstruction(Val, 5, 5);
858 unsigned Rt2 = fieldFromInstruction(Val, 10, 5);
859 unsigned MemSize = fieldFromInstruction(Val, 30, 2);
861 DecodeStatus S = MCDisassembler::Success;
862 if (Rt == Rt2) S = MCDisassembler::SoftFail;
866 if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder)))
867 return MCDisassembler::Fail;
868 if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder)))
869 return MCDisassembler::Fail;
872 if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder)))
873 return MCDisassembler::Fail;
874 if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder)))
875 return MCDisassembler::Fail;
878 llvm_unreachable("Invalid MemSize in DecodeLoadPairExclusiveInstruction");
881 if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder)))
882 return MCDisassembler::Fail;
887 template<typename SomeNamedImmMapper>
888 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
891 const void *Decoder) {
892 SomeNamedImmMapper Mapper;
894 Mapper.toString(Val, ValidNamed);
895 if (ValidNamed || Mapper.validImm(Val)) {
896 Inst.addOperand(MCOperand::CreateImm(Val));
897 return MCDisassembler::Success;
900 return MCDisassembler::Fail;
903 static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
907 const void *Decoder) {
909 Mapper.toString(Val, ValidNamed);
911 Inst.addOperand(MCOperand::CreateImm(Val));
913 return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail;
916 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
919 const void *Decoder) {
920 return DecodeSysRegOperand(A64SysReg::MRSMapper(), Inst, Val, Address,
924 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
927 const void *Decoder) {
928 return DecodeSysRegOperand(A64SysReg::MSRMapper(), Inst, Val, Address,
932 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
935 const void *Decoder) {
936 unsigned Rt = fieldFromInstruction(Insn, 0, 5);
937 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
938 unsigned Imm9 = fieldFromInstruction(Insn, 12, 9);
940 unsigned Opc = fieldFromInstruction(Insn, 22, 2);
941 unsigned V = fieldFromInstruction(Insn, 26, 1);
942 unsigned Size = fieldFromInstruction(Insn, 30, 2);
944 if (Opc == 0 || (V == 1 && Opc == 2)) {
945 // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm
946 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
949 if (V == 0 && (Opc == 2 || Size == 3)) {
950 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
952 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
953 } else if (V == 1 && (Opc & 2)) {
954 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
958 DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder);
961 DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder);
964 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
967 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
972 if (Opc != 0 && (V != 1 || Opc != 2)) {
973 // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm
974 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
977 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
979 Inst.addOperand(MCOperand::CreateImm(Imm9));
981 // N.b. The official documentation says undpredictable if Rt == Rn, but this
982 // takes place at the architectural rather than encoding level:
984 // "STR xzr, [sp], #4" is perfectly valid.
985 if (V == 0 && Rt == Rn && Rn != 31)
986 return MCDisassembler::SoftFail;
988 return MCDisassembler::Success;
991 static MCDisassembler *createAArch64Disassembler(const Target &T,
992 const MCSubtargetInfo &STI,
994 return new AArch64Disassembler(STI, Ctx);
997 extern "C" void LLVMInitializeAArch64Disassembler() {
998 TargetRegistry::RegisterMCDisassembler(TheAArch64leTarget,
999 createAArch64Disassembler);
1000 TargetRegistry::RegisterMCDisassembler(TheAArch64beTarget,
1001 createAArch64Disassembler);
1004 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
1006 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
1007 uint64_t Address, const void *Decoder) {
1009 if (Ext == A64SE::LSL)
1011 else if (Ext != A64SE::MSL)
1012 return MCDisassembler::Fail;
1014 // MSL and LSLH accepts encoded shift amount 0 or 1.
1015 if ((!IsLSL || (IsLSL && IsHalf)) && ShiftAmount != 0 && ShiftAmount != 1)
1016 return MCDisassembler::Fail;
1018 // LSL accepts encoded shift amount 0, 1, 2 or 3.
1019 if (IsLSL && ShiftAmount > 3)
1020 return MCDisassembler::Fail;
1022 Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
1023 return MCDisassembler::Success;
1026 // Decode post-index vector load/store instructions.
1027 // This is necessary as we need to decode Rm: if Rm == 0b11111, the last
1028 // operand is an immediate equal the the length of vector list in bytes,
1029 // or Rm is decoded to a GPR64noxzr register.
1030 static DecodeStatus DecodeVLDSTPostInstruction(MCInst &Inst, unsigned Insn,
1032 const void *Decoder) {
1033 unsigned Rt = fieldFromInstruction(Insn, 0, 5);
1034 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
1035 unsigned Rm = fieldFromInstruction(Insn, 16, 5);
1036 unsigned Opcode = fieldFromInstruction(Insn, 12, 4);
1037 unsigned IsLoad = fieldFromInstruction(Insn, 22, 1);
1038 // 0 for 64bit vector list, 1 for 128bit vector list
1039 unsigned Is128BitVec = fieldFromInstruction(Insn, 30, 1);
1044 case 2: // ld1/st1 with 4 vectors
1047 case 6: // ld1/st1 with 3 vectors
1049 case 7: // ld1/st1 with 1 vector
1052 case 10: // ld1/st1 with 2 vectors
1055 llvm_unreachable("Invalid opcode for post-index load/store instructions");
1058 // Decode vector list of 1/2/3/4 vectors for load instructions.
1062 Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder)
1063 : DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
1066 Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder)
1067 : DecodeDPairRegisterClass(Inst, Rt, Address, Decoder);
1070 Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder)
1071 : DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder);
1074 Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder)
1075 : DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder);
1080 // Decode write back register, which is equal to Rn.
1081 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1082 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1084 if (Rm == 31) // If Rm is 0x11111, add the vector list length in byte
1085 Inst.addOperand(MCOperand::CreateImm(NumVecs * (Is128BitVec ? 16 : 8)));
1087 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder);
1089 // Decode vector list of 1/2/3/4 vectors for load instructions.
1093 Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder)
1094 : DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
1097 Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder)
1098 : DecodeDPairRegisterClass(Inst, Rt, Address, Decoder);
1101 Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder)
1102 : DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder);
1105 Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder)
1106 : DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder);
1111 return MCDisassembler::Success;
1114 // Decode post-index vector load/store lane instructions.
1115 // This is necessary as we need to decode Rm: if Rm == 0b11111, the last
1116 // operand is an immediate equal the the length of the changed bytes,
1117 // or Rm is decoded to a GPR64noxzr register.
1118 static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
1120 const void *Decoder) {
1121 bool Is64bitVec = false;
1122 bool IsLoadDup = false;
1123 bool IsLoad = false;
1124 // The total number of bytes transferred.
1125 // TransferBytes = NumVecs * OneLaneBytes
1126 unsigned TransferBytes = 0;
1127 unsigned NumVecs = 0;
1128 unsigned Opc = Inst.getOpcode();
1130 case AArch64::LD1R_WB_8B_fixed: case AArch64::LD1R_WB_8B_register:
1131 case AArch64::LD1R_WB_4H_fixed: case AArch64::LD1R_WB_4H_register:
1132 case AArch64::LD1R_WB_2S_fixed: case AArch64::LD1R_WB_2S_register:
1133 case AArch64::LD1R_WB_1D_fixed: case AArch64::LD1R_WB_1D_register: {
1135 case AArch64::LD1R_WB_8B_fixed: case AArch64::LD1R_WB_8B_register:
1136 TransferBytes = 1; break;
1137 case AArch64::LD1R_WB_4H_fixed: case AArch64::LD1R_WB_4H_register:
1138 TransferBytes = 2; break;
1139 case AArch64::LD1R_WB_2S_fixed: case AArch64::LD1R_WB_2S_register:
1140 TransferBytes = 4; break;
1141 case AArch64::LD1R_WB_1D_fixed: case AArch64::LD1R_WB_1D_register:
1142 TransferBytes = 8; break;
1150 case AArch64::LD1R_WB_16B_fixed: case AArch64::LD1R_WB_16B_register:
1151 case AArch64::LD1R_WB_8H_fixed: case AArch64::LD1R_WB_8H_register:
1152 case AArch64::LD1R_WB_4S_fixed: case AArch64::LD1R_WB_4S_register:
1153 case AArch64::LD1R_WB_2D_fixed: case AArch64::LD1R_WB_2D_register: {
1155 case AArch64::LD1R_WB_16B_fixed: case AArch64::LD1R_WB_16B_register:
1156 TransferBytes = 1; break;
1157 case AArch64::LD1R_WB_8H_fixed: case AArch64::LD1R_WB_8H_register:
1158 TransferBytes = 2; break;
1159 case AArch64::LD1R_WB_4S_fixed: case AArch64::LD1R_WB_4S_register:
1160 TransferBytes = 4; break;
1161 case AArch64::LD1R_WB_2D_fixed: case AArch64::LD1R_WB_2D_register:
1162 TransferBytes = 8; break;
1169 case AArch64::LD2R_WB_8B_fixed: case AArch64::LD2R_WB_8B_register:
1170 case AArch64::LD2R_WB_4H_fixed: case AArch64::LD2R_WB_4H_register:
1171 case AArch64::LD2R_WB_2S_fixed: case AArch64::LD2R_WB_2S_register:
1172 case AArch64::LD2R_WB_1D_fixed: case AArch64::LD2R_WB_1D_register: {
1174 case AArch64::LD2R_WB_8B_fixed: case AArch64::LD2R_WB_8B_register:
1175 TransferBytes = 2; break;
1176 case AArch64::LD2R_WB_4H_fixed: case AArch64::LD2R_WB_4H_register:
1177 TransferBytes = 4; break;
1178 case AArch64::LD2R_WB_2S_fixed: case AArch64::LD2R_WB_2S_register:
1179 TransferBytes = 8; break;
1180 case AArch64::LD2R_WB_1D_fixed: case AArch64::LD2R_WB_1D_register:
1181 TransferBytes = 16; break;
1189 case AArch64::LD2R_WB_16B_fixed: case AArch64::LD2R_WB_16B_register:
1190 case AArch64::LD2R_WB_8H_fixed: case AArch64::LD2R_WB_8H_register:
1191 case AArch64::LD2R_WB_4S_fixed: case AArch64::LD2R_WB_4S_register:
1192 case AArch64::LD2R_WB_2D_fixed: case AArch64::LD2R_WB_2D_register: {
1194 case AArch64::LD2R_WB_16B_fixed: case AArch64::LD2R_WB_16B_register:
1195 TransferBytes = 2; break;
1196 case AArch64::LD2R_WB_8H_fixed: case AArch64::LD2R_WB_8H_register:
1197 TransferBytes = 4; break;
1198 case AArch64::LD2R_WB_4S_fixed: case AArch64::LD2R_WB_4S_register:
1199 TransferBytes = 8; break;
1200 case AArch64::LD2R_WB_2D_fixed: case AArch64::LD2R_WB_2D_register:
1201 TransferBytes = 16; break;
1208 case AArch64::LD3R_WB_8B_fixed: case AArch64::LD3R_WB_8B_register:
1209 case AArch64::LD3R_WB_4H_fixed: case AArch64::LD3R_WB_4H_register:
1210 case AArch64::LD3R_WB_2S_fixed: case AArch64::LD3R_WB_2S_register:
1211 case AArch64::LD3R_WB_1D_fixed: case AArch64::LD3R_WB_1D_register: {
1213 case AArch64::LD3R_WB_8B_fixed: case AArch64::LD3R_WB_8B_register:
1214 TransferBytes = 3; break;
1215 case AArch64::LD3R_WB_4H_fixed: case AArch64::LD3R_WB_4H_register:
1216 TransferBytes = 6; break;
1217 case AArch64::LD3R_WB_2S_fixed: case AArch64::LD3R_WB_2S_register:
1218 TransferBytes = 12; break;
1219 case AArch64::LD3R_WB_1D_fixed: case AArch64::LD3R_WB_1D_register:
1220 TransferBytes = 24; break;
1228 case AArch64::LD3R_WB_16B_fixed: case AArch64::LD3R_WB_16B_register:
1229 case AArch64::LD3R_WB_4S_fixed: case AArch64::LD3R_WB_8H_register:
1230 case AArch64::LD3R_WB_8H_fixed: case AArch64::LD3R_WB_4S_register:
1231 case AArch64::LD3R_WB_2D_fixed: case AArch64::LD3R_WB_2D_register: {
1233 case AArch64::LD3R_WB_16B_fixed: case AArch64::LD3R_WB_16B_register:
1234 TransferBytes = 3; break;
1235 case AArch64::LD3R_WB_8H_fixed: case AArch64::LD3R_WB_8H_register:
1236 TransferBytes = 6; break;
1237 case AArch64::LD3R_WB_4S_fixed: case AArch64::LD3R_WB_4S_register:
1238 TransferBytes = 12; break;
1239 case AArch64::LD3R_WB_2D_fixed: case AArch64::LD3R_WB_2D_register:
1240 TransferBytes = 24; break;
1247 case AArch64::LD4R_WB_8B_fixed: case AArch64::LD4R_WB_8B_register:
1248 case AArch64::LD4R_WB_4H_fixed: case AArch64::LD4R_WB_4H_register:
1249 case AArch64::LD4R_WB_2S_fixed: case AArch64::LD4R_WB_2S_register:
1250 case AArch64::LD4R_WB_1D_fixed: case AArch64::LD4R_WB_1D_register: {
1252 case AArch64::LD4R_WB_8B_fixed: case AArch64::LD4R_WB_8B_register:
1253 TransferBytes = 4; break;
1254 case AArch64::LD4R_WB_4H_fixed: case AArch64::LD4R_WB_4H_register:
1255 TransferBytes = 8; break;
1256 case AArch64::LD4R_WB_2S_fixed: case AArch64::LD4R_WB_2S_register:
1257 TransferBytes = 16; break;
1258 case AArch64::LD4R_WB_1D_fixed: case AArch64::LD4R_WB_1D_register:
1259 TransferBytes = 32; break;
1267 case AArch64::LD4R_WB_16B_fixed: case AArch64::LD4R_WB_16B_register:
1268 case AArch64::LD4R_WB_4S_fixed: case AArch64::LD4R_WB_8H_register:
1269 case AArch64::LD4R_WB_8H_fixed: case AArch64::LD4R_WB_4S_register:
1270 case AArch64::LD4R_WB_2D_fixed: case AArch64::LD4R_WB_2D_register: {
1272 case AArch64::LD4R_WB_16B_fixed: case AArch64::LD4R_WB_16B_register:
1273 TransferBytes = 4; break;
1274 case AArch64::LD4R_WB_8H_fixed: case AArch64::LD4R_WB_8H_register:
1275 TransferBytes = 8; break;
1276 case AArch64::LD4R_WB_4S_fixed: case AArch64::LD4R_WB_4S_register:
1277 TransferBytes = 16; break;
1278 case AArch64::LD4R_WB_2D_fixed: case AArch64::LD4R_WB_2D_register:
1279 TransferBytes = 32; break;
1286 case AArch64::LD1LN_WB_B_fixed: case AArch64::LD1LN_WB_B_register:
1287 case AArch64::LD1LN_WB_H_fixed: case AArch64::LD1LN_WB_H_register:
1288 case AArch64::LD1LN_WB_S_fixed: case AArch64::LD1LN_WB_S_register:
1289 case AArch64::LD1LN_WB_D_fixed: case AArch64::LD1LN_WB_D_register: {
1291 case AArch64::LD1LN_WB_B_fixed: case AArch64::LD1LN_WB_B_register:
1292 TransferBytes = 1; break;
1293 case AArch64::LD1LN_WB_H_fixed: case AArch64::LD1LN_WB_H_register:
1294 TransferBytes = 2; break;
1295 case AArch64::LD1LN_WB_S_fixed: case AArch64::LD1LN_WB_S_register:
1296 TransferBytes = 4; break;
1297 case AArch64::LD1LN_WB_D_fixed: case AArch64::LD1LN_WB_D_register:
1298 TransferBytes = 8; break;
1305 case AArch64::LD2LN_WB_B_fixed: case AArch64::LD2LN_WB_B_register:
1306 case AArch64::LD2LN_WB_H_fixed: case AArch64::LD2LN_WB_H_register:
1307 case AArch64::LD2LN_WB_S_fixed: case AArch64::LD2LN_WB_S_register:
1308 case AArch64::LD2LN_WB_D_fixed: case AArch64::LD2LN_WB_D_register: {
1310 case AArch64::LD2LN_WB_B_fixed: case AArch64::LD2LN_WB_B_register:
1311 TransferBytes = 2; break;
1312 case AArch64::LD2LN_WB_H_fixed: case AArch64::LD2LN_WB_H_register:
1313 TransferBytes = 4; break;
1314 case AArch64::LD2LN_WB_S_fixed: case AArch64::LD2LN_WB_S_register:
1315 TransferBytes = 8; break;
1316 case AArch64::LD2LN_WB_D_fixed: case AArch64::LD2LN_WB_D_register:
1317 TransferBytes = 16; break;
1324 case AArch64::LD3LN_WB_B_fixed: case AArch64::LD3LN_WB_B_register:
1325 case AArch64::LD3LN_WB_H_fixed: case AArch64::LD3LN_WB_H_register:
1326 case AArch64::LD3LN_WB_S_fixed: case AArch64::LD3LN_WB_S_register:
1327 case AArch64::LD3LN_WB_D_fixed: case AArch64::LD3LN_WB_D_register: {
1329 case AArch64::LD3LN_WB_B_fixed: case AArch64::LD3LN_WB_B_register:
1330 TransferBytes = 3; break;
1331 case AArch64::LD3LN_WB_H_fixed: case AArch64::LD3LN_WB_H_register:
1332 TransferBytes = 6; break;
1333 case AArch64::LD3LN_WB_S_fixed: case AArch64::LD3LN_WB_S_register:
1334 TransferBytes = 12; break;
1335 case AArch64::LD3LN_WB_D_fixed: case AArch64::LD3LN_WB_D_register:
1336 TransferBytes = 24; break;
1343 case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register:
1344 case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register:
1345 case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register:
1346 case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: {
1348 case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register:
1349 TransferBytes = 4; break;
1350 case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register:
1351 TransferBytes = 8; break;
1352 case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register:
1353 TransferBytes = 16; break;
1354 case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register:
1355 TransferBytes = 32; break;
1362 case AArch64::ST1LN_WB_B_fixed: case AArch64::ST1LN_WB_B_register:
1363 case AArch64::ST1LN_WB_H_fixed: case AArch64::ST1LN_WB_H_register:
1364 case AArch64::ST1LN_WB_S_fixed: case AArch64::ST1LN_WB_S_register:
1365 case AArch64::ST1LN_WB_D_fixed: case AArch64::ST1LN_WB_D_register: {
1367 case AArch64::ST1LN_WB_B_fixed: case AArch64::ST1LN_WB_B_register:
1368 TransferBytes = 1; break;
1369 case AArch64::ST1LN_WB_H_fixed: case AArch64::ST1LN_WB_H_register:
1370 TransferBytes = 2; break;
1371 case AArch64::ST1LN_WB_S_fixed: case AArch64::ST1LN_WB_S_register:
1372 TransferBytes = 4; break;
1373 case AArch64::ST1LN_WB_D_fixed: case AArch64::ST1LN_WB_D_register:
1374 TransferBytes = 8; break;
1380 case AArch64::ST2LN_WB_B_fixed: case AArch64::ST2LN_WB_B_register:
1381 case AArch64::ST2LN_WB_H_fixed: case AArch64::ST2LN_WB_H_register:
1382 case AArch64::ST2LN_WB_S_fixed: case AArch64::ST2LN_WB_S_register:
1383 case AArch64::ST2LN_WB_D_fixed: case AArch64::ST2LN_WB_D_register: {
1385 case AArch64::ST2LN_WB_B_fixed: case AArch64::ST2LN_WB_B_register:
1386 TransferBytes = 2; break;
1387 case AArch64::ST2LN_WB_H_fixed: case AArch64::ST2LN_WB_H_register:
1388 TransferBytes = 4; break;
1389 case AArch64::ST2LN_WB_S_fixed: case AArch64::ST2LN_WB_S_register:
1390 TransferBytes = 8; break;
1391 case AArch64::ST2LN_WB_D_fixed: case AArch64::ST2LN_WB_D_register:
1392 TransferBytes = 16; break;
1398 case AArch64::ST3LN_WB_B_fixed: case AArch64::ST3LN_WB_B_register:
1399 case AArch64::ST3LN_WB_H_fixed: case AArch64::ST3LN_WB_H_register:
1400 case AArch64::ST3LN_WB_S_fixed: case AArch64::ST3LN_WB_S_register:
1401 case AArch64::ST3LN_WB_D_fixed: case AArch64::ST3LN_WB_D_register: {
1403 case AArch64::ST3LN_WB_B_fixed: case AArch64::ST3LN_WB_B_register:
1404 TransferBytes = 3; break;
1405 case AArch64::ST3LN_WB_H_fixed: case AArch64::ST3LN_WB_H_register:
1406 TransferBytes = 6; break;
1407 case AArch64::ST3LN_WB_S_fixed: case AArch64::ST3LN_WB_S_register:
1408 TransferBytes = 12; break;
1409 case AArch64::ST3LN_WB_D_fixed: case AArch64::ST3LN_WB_D_register:
1410 TransferBytes = 24; break;
1416 case AArch64::ST4LN_WB_B_fixed: case AArch64::ST4LN_WB_B_register:
1417 case AArch64::ST4LN_WB_H_fixed: case AArch64::ST4LN_WB_H_register:
1418 case AArch64::ST4LN_WB_S_fixed: case AArch64::ST4LN_WB_S_register:
1419 case AArch64::ST4LN_WB_D_fixed: case AArch64::ST4LN_WB_D_register: {
1421 case AArch64::ST4LN_WB_B_fixed: case AArch64::ST4LN_WB_B_register:
1422 TransferBytes = 4; break;
1423 case AArch64::ST4LN_WB_H_fixed: case AArch64::ST4LN_WB_H_register:
1424 TransferBytes = 8; break;
1425 case AArch64::ST4LN_WB_S_fixed: case AArch64::ST4LN_WB_S_register:
1426 TransferBytes = 16; break;
1427 case AArch64::ST4LN_WB_D_fixed: case AArch64::ST4LN_WB_D_register:
1428 TransferBytes = 32; break;
1435 return MCDisassembler::Fail;
1436 } // End of switch (Opc)
1438 unsigned Rt = fieldFromInstruction(Insn, 0, 5);
1439 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
1440 unsigned Rm = fieldFromInstruction(Insn, 16, 5);
1442 // Decode post-index of load duplicate lane
1446 Is64bitVec ? DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder)
1447 : DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
1450 Is64bitVec ? DecodeDPairRegisterClass(Inst, Rt, Address, Decoder)
1451 : DecodeQPairRegisterClass(Inst, Rt, Address, Decoder);
1454 Is64bitVec ? DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder)
1455 : DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder);
1458 Is64bitVec ? DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder)
1459 : DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder);
1462 // Decode write back register, which is equal to Rn.
1463 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1464 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1466 if (Rm == 31) // If Rm is 0x11111, add the number of transferred bytes
1467 Inst.addOperand(MCOperand::CreateImm(TransferBytes));
1469 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder);
1471 return MCDisassembler::Success;
1474 // Decode post-index of load/store lane
1475 // Loads have a vector list as output.
1479 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
1482 DecodeQPairRegisterClass(Inst, Rt, Address, Decoder);
1485 DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder);
1488 DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder);
1492 // Decode write back register, which is equal to Rn.
1493 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1494 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1496 if (Rm == 31) // If Rm is 0x11111, add the number of transferred bytes
1497 Inst.addOperand(MCOperand::CreateImm(TransferBytes));
1499 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder);
1501 // Decode the source vector list.
1504 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
1507 DecodeQPairRegisterClass(Inst, Rt, Address, Decoder);
1510 DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder);
1513 DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder);
1517 unsigned Q = fieldFromInstruction(Insn, 30, 1);
1518 unsigned S = fieldFromInstruction(Insn, 10, 3);
1520 // Calculate the number of lanes by number of vectors and transferred bytes.
1521 // NumLanes = 16 bytes / bytes of each lane
1522 unsigned NumLanes = 16 / (TransferBytes / NumVecs);
1524 case 16: // A vector has 16 lanes, each lane is 1 bytes.
1525 lane = (Q << 3) | S;
1528 lane = (Q << 2) | (S >> 1);
1531 lane = (Q << 1) | (S >> 2);
1537 Inst.addOperand(MCOperand::CreateImm(lane));
1539 return MCDisassembler::Success;
1542 static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn,
1544 const void *Decoder) {
1545 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
1546 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
1547 unsigned size = fieldFromInstruction(Insn, 22, 2);
1548 unsigned Q = fieldFromInstruction(Insn, 30, 1);
1550 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
1553 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
1555 DecodeFPR64RegisterClass(Inst, Rn, Address, Decoder);
1559 Inst.addOperand(MCOperand::CreateImm(8));
1562 Inst.addOperand(MCOperand::CreateImm(16));
1565 Inst.addOperand(MCOperand::CreateImm(32));
1568 return MCDisassembler::Fail;
1570 return MCDisassembler::Success;