lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

   1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the functions necessary to decode AArch64 instruction
  11 // bitpatterns into MCInsts (with the help of TableGenerated information from
  12 // the instruction definitions).
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #define DEBUG_TYPE "arm-disassembler"
  17
  18 #include "AArch64.h"
  19 #include "AArch64RegisterInfo.h"
  20 #include "AArch64Subtarget.h"
  21 #include "Utils/AArch64BaseInfo.h"
  22 #include "llvm/MC/MCInst.h"
  23 #include "llvm/MC/MCInstrDesc.h"
  24 #include "llvm/MC/MCExpr.h"
  25 #include "llvm/MC/MCContext.h"
  26 #include "llvm/MC/MCDisassembler.h"
  27 #include "llvm/MC/MCFixedLenDisassembler.h"
  28 #include "llvm/Support/Debug.h"
  29 #include "llvm/Support/MemoryObject.h"
  30 #include "llvm/Support/ErrorHandling.h"
  31 #include "llvm/Support/TargetRegistry.h"
  32 #include "llvm/Support/raw_ostream.h"
  33
  34 using namespace llvm;
  35
  36 typedef MCDisassembler::DecodeStatus DecodeStatus;
  37
  38 namespace {
  39 /// AArch64 disassembler for all AArch64 platforms.
  40 class AArch64Disassembler : public MCDisassembler {
  41   OwningPtr<const MCRegisterInfo> RegInfo;
  42 public:
  43   /// Initializes the disassembler.
  44   ///
  45   AArch64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info)
  46     : MCDisassembler(STI), RegInfo(Info) {
  47   }
  48
  49   ~AArch64Disassembler() {}
  50
  51   /// See MCDisassembler.
  52   DecodeStatus getInstruction(MCInst &instr,
  53                               uint64_t &size,
  54                               const MemoryObject &region,
  55                               uint64_t address,
  56                               raw_ostream &vStream,
  57                               raw_ostream &cStream) const;
  58
  59   const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
  60 };
  61
  62 }
  63
  64 // Forward-declarations used in the auto-generated files.
  65 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  66                                          uint64_t Address, const void *Decoder);
  67 static DecodeStatus
  68 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  69                             uint64_t Address, const void *Decoder);
  70
  71 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  72                                          uint64_t Address, const void *Decoder);
  73 static DecodeStatus
  74 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  75                             uint64_t Address, const void *Decoder);
  76
  77 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  78                                          uint64_t Address, const void *Decoder);
  79 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  80                                          uint64_t Address, const void *Decoder);
  81 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  82                                          uint64_t Address, const void *Decoder);
  83 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  84                                          uint64_t Address, const void *Decoder);
  85 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
  86                                               unsigned RegNo, uint64_t Address,
  87                                               const void *Decoder);
  88
  89 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
  90                                                unsigned OptionHiS,
  91                                                uint64_t Address,
  92                                                const void *Decoder);
  93
  94
  95 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
  96                                                unsigned Imm6Bits,
  97                                                uint64_t Address,
  98                                                const void *Decoder);
  99
 100 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
 101                                                unsigned Imm6Bits,
 102                                                uint64_t Address,
 103                                                const void *Decoder);
 104
 105 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
 106                                         unsigned RmBits,
 107                                         uint64_t Address,
 108                                         const void *Decoder);
 109
 110 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val,
 111                                          uint64_t Address, const void *Decoder);
 112 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val,
 113                                           uint64_t Address,
 114                                           const void *Decoder);
 115 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val,
 116                                           uint64_t Address,
 117                                           const void *Decoder);
 118 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val,
 119                                           uint64_t Address,
 120                                           const void *Decoder);
 121
 122 template<int RegWidth>
 123 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
 124                                              unsigned FullImm,
 125                                              uint64_t Address,
 126                                              const void *Decoder);
 127
 128 template<int RegWidth>
 129 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
 130                                             unsigned Bits,
 131                                             uint64_t Address,
 132                                             const void *Decoder);
 133
 134 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
 135                                            unsigned ShiftAmount,
 136                                            uint64_t Address,
 137                                            const void *Decoder);
 138 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
 139 static DecodeStatus
 140 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
 141                              uint64_t Address, const void *Decoder);
 142
 143 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
 144                                             unsigned ShiftAmount,
 145                                             uint64_t Address,
 146                                             const void *Decoder);
 147 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
 148                                               uint64_t Address,
 149                                               const void *Decoder);
 150
 151 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 152                                               uint64_t Address,
 153                                               const void *Decoder);
 154
 155 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
 156                                               unsigned Insn,
 157                                               uint64_t Address,
 158                                               const void *Decoder);
 159
 160 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
 161                                                        unsigned Val,
 162                                                        uint64_t Address,
 163                                                        const void *Decoder);
 164
 165 template<typename SomeNamedImmMapper>
 166 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
 167                                           unsigned Val,
 168                                           uint64_t Address,
 169                                           const void *Decoder);
 170
 171 static DecodeStatus
 172 DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper,
 173                     llvm::MCInst &Inst, unsigned Val,
 174                     uint64_t Address, const void *Decoder);
 175
 176 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
 177                                      unsigned Val,
 178                                      uint64_t Address,
 179                                      const void *Decoder);
 180
 181 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
 182                                      unsigned Val,
 183                                      uint64_t Address,
 184                                      const void *Decoder);
 185
 186
 187 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
 188                                                    unsigned Val,
 189                                                    uint64_t Address,
 190                                                    const void *Decoder);
 191
 192
 193 static bool Check(DecodeStatus &Out, DecodeStatus In);
 194
 195 #include "AArch64GenDisassemblerTables.inc"
 196 #include "AArch64GenInstrInfo.inc"
 197
 198 static bool Check(DecodeStatus &Out, DecodeStatus In) {
 199   switch (In) {
 200     case MCDisassembler::Success:
 201       // Out stays the same.
 202       return true;
 203     case MCDisassembler::SoftFail:
 204       Out = In;
 205       return true;
 206     case MCDisassembler::Fail:
 207       Out = In;
 208       return false;
 209   }
 210   llvm_unreachable("Invalid DecodeStatus!");
 211 }
 212
 213 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
 214                                                  const MemoryObject &Region,
 215                                                  uint64_t Address,
 216                                                  raw_ostream &os,
 217                                                  raw_ostream &cs) const {
 218   CommentStream = &cs;
 219
 220   uint8_t bytes[4];
 221
 222   // We want to read exactly 4 bytes of data.
 223   if (Region.readBytes(Address, 4, bytes) == -1) {
 224     Size = 0;
 225     return MCDisassembler::Fail;
 226   }
 227
 228   // Encoded as a small-endian 32-bit word in the stream.
 229   uint32_t insn = (bytes[3] << 24) |
 230     (bytes[2] << 16) |
 231     (bytes[1] <<  8) |
 232     (bytes[0] <<  0);
 233
 234   // Calling the auto-generated decoder function.
 235   DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address,
 236                                           this, STI);
 237   if (result != MCDisassembler::Fail) {
 238     Size = 4;
 239     return result;
 240   }
 241
 242   MI.clear();
 243   Size = 0;
 244   return MCDisassembler::Fail;
 245 }
 246
 247 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 248   const AArch64Disassembler *Dis = static_cast<const AArch64Disassembler*>(D);
 249   return Dis->getRegInfo()->getRegClass(RC).getRegister(RegNo);
 250 }
 251
 252 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 253                                         uint64_t Address, const void *Decoder) {
 254   if (RegNo > 31)
 255     return MCDisassembler::Fail;
 256
 257   uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo);
 258   Inst.addOperand(MCOperand::CreateReg(Register));
 259   return MCDisassembler::Success;
 260 }
 261
 262 static DecodeStatus
 263 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 264                             uint64_t Address, const void *Decoder) {
 265   if (RegNo > 31)
 266     return MCDisassembler::Fail;
 267
 268   uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo);
 269   Inst.addOperand(MCOperand::CreateReg(Register));
 270   return MCDisassembler::Success;
 271 }
 272
 273 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 274                                              uint64_t Address,
 275                                              const void *Decoder) {
 276   if (RegNo > 31)
 277     return MCDisassembler::Fail;
 278
 279   uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo);
 280   Inst.addOperand(MCOperand::CreateReg(Register));
 281   return MCDisassembler::Success;
 282 }
 283
 284 static DecodeStatus
 285 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 286                             uint64_t Address, const void *Decoder) {
 287   if (RegNo > 31)
 288     return MCDisassembler::Fail;
 289
 290   uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo);
 291   Inst.addOperand(MCOperand::CreateReg(Register));
 292   return MCDisassembler::Success;
 293 }
 294
 295 static DecodeStatus
 296 DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 297                             uint64_t Address, const void *Decoder) {
 298   if (RegNo > 31)
 299     return MCDisassembler::Fail;
 300
 301   uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo);
 302   Inst.addOperand(MCOperand::CreateReg(Register));
 303   return MCDisassembler::Success;
 304 }
 305
 306 static DecodeStatus
 307 DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 308                             uint64_t Address, const void *Decoder) {
 309   if (RegNo > 31)
 310     return MCDisassembler::Fail;
 311
 312   uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo);
 313   Inst.addOperand(MCOperand::CreateReg(Register));
 314   return MCDisassembler::Success;
 315 }
 316
 317
 318 static DecodeStatus
 319 DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 320                             uint64_t Address, const void *Decoder) {
 321   if (RegNo > 31)
 322     return MCDisassembler::Fail;
 323
 324   uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo);
 325   Inst.addOperand(MCOperand::CreateReg(Register));
 326   return MCDisassembler::Success;
 327 }
 328
 329 static DecodeStatus
 330 DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 331                             uint64_t Address, const void *Decoder) {
 332   if (RegNo > 31)
 333     return MCDisassembler::Fail;
 334
 335   uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo);
 336   Inst.addOperand(MCOperand::CreateReg(Register));
 337   return MCDisassembler::Success;
 338 }
 339
 340
 341 static DecodeStatus
 342 DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 343                             uint64_t Address, const void *Decoder) {
 344   if (RegNo > 31)
 345     return MCDisassembler::Fail;
 346
 347   uint16_t Register = getReg(Decoder, AArch64::FPR128RegClassID, RegNo);
 348   Inst.addOperand(MCOperand::CreateReg(Register));
 349   return MCDisassembler::Success;
 350 }
 351
 352 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
 353                                                unsigned OptionHiS,
 354                                                uint64_t Address,
 355                                                const void *Decoder) {
 356   // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1},
 357   // S}. Hence we want to check bit 1.
 358   if (!(OptionHiS & 2))
 359     return MCDisassembler::Fail;
 360
 361   Inst.addOperand(MCOperand::CreateImm(OptionHiS));
 362   return MCDisassembler::Success;
 363 }
 364
 365 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
 366                                                unsigned Imm6Bits,
 367                                                uint64_t Address,
 368                                                const void *Decoder) {
 369   // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be
 370   // between 0 and 31.
 371   if (Imm6Bits > 31)
 372     return MCDisassembler::Fail;
 373
 374   Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
 375   return MCDisassembler::Success;
 376 }
 377
 378 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
 379                                                unsigned Imm6Bits,
 380                                                uint64_t Address,
 381                                                const void *Decoder) {
 382   // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32.
 383   if (Imm6Bits < 32)
 384     return MCDisassembler::Fail;
 385
 386   Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
 387   return MCDisassembler::Success;
 388 }
 389
 390 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
 391                                         unsigned RmBits,
 392                                         uint64_t Address,
 393                                         const void *Decoder) {
 394   // Any bits are valid in the instruction (they're architecturally ignored),
 395   // but a code generator should insert 0.
 396   Inst.addOperand(MCOperand::CreateImm(0));
 397   return MCDisassembler::Success;
 398 }
 399
 400 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val,
 401                                          uint64_t Address,
 402                                          const void *Decoder) {
 403   Inst.addOperand(MCOperand::CreateImm(8 - Val));
 404   return MCDisassembler::Success;
 405 }
 406
 407 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val,
 408                                           uint64_t Address,
 409                                           const void *Decoder) {
 410   Inst.addOperand(MCOperand::CreateImm(16 - Val));
 411   return MCDisassembler::Success;
 412 }
 413
 414 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val,
 415                                           uint64_t Address,
 416                                           const void *Decoder) {
 417   Inst.addOperand(MCOperand::CreateImm(32 - Val));
 418   return MCDisassembler::Success;
 419 }
 420
 421 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val,
 422                                           uint64_t Address,
 423                                           const void *Decoder) {
 424   Inst.addOperand(MCOperand::CreateImm(64 - Val));
 425   return MCDisassembler::Success;
 426 }
 427
 428 template<int RegWidth>
 429 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
 430                                              unsigned FullImm,
 431                                              uint64_t Address,
 432                                              const void *Decoder) {
 433   unsigned Imm16 = FullImm & 0xffff;
 434   unsigned Shift = FullImm >> 16;
 435
 436   if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail;
 437
 438   Inst.addOperand(MCOperand::CreateImm(Imm16));
 439   Inst.addOperand(MCOperand::CreateImm(Shift));
 440   return MCDisassembler::Success;
 441 }
 442
 443 template<int RegWidth>
 444 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
 445                                             unsigned Bits,
 446                                             uint64_t Address,
 447                                             const void *Decoder) {
 448   uint64_t Imm;
 449   if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm))
 450     return MCDisassembler::Fail;
 451
 452   Inst.addOperand(MCOperand::CreateImm(Bits));
 453   return MCDisassembler::Success;
 454 }
 455
 456
 457 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
 458                                            unsigned ShiftAmount,
 459                                            uint64_t Address,
 460                                            const void *Decoder) {
 461   // Only values 0-4 are valid for this 3-bit field
 462   if (ShiftAmount > 4)
 463     return MCDisassembler::Fail;
 464
 465   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 466   return MCDisassembler::Success;
 467 }
 468
 469 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
 470                                             unsigned ShiftAmount,
 471                                             uint64_t Address,
 472                                             const void *Decoder) {
 473   // Only values below 32 are valid for a 32-bit register
 474   if (ShiftAmount > 31)
 475     return MCDisassembler::Fail;
 476
 477   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 478   return MCDisassembler::Success;
 479 }
 480
 481 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
 482                                               uint64_t Address,
 483                                               const void *Decoder) {
 484   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 485   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 486   unsigned ImmS = fieldFromInstruction(Insn, 10, 6);
 487   unsigned ImmR = fieldFromInstruction(Insn, 16, 6);
 488   unsigned SF = fieldFromInstruction(Insn, 31, 1);
 489
 490   // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise
 491   // out assertions that it thinks should never be hit.
 492   enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc;
 493   Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2);
 494
 495   if (!SF) {
 496     // ImmR and ImmS must be between 0 and 31 for 32-bit instructions.
 497     if (ImmR > 31 || ImmS > 31)
 498       return MCDisassembler::Fail;
 499   }
 500
 501   if (SF) {
 502     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 503     // BFM MCInsts use Rd as a source too.
 504     if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 505     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 506   } else {
 507     DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
 508     // BFM MCInsts use Rd as a source too.
 509     if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
 510     DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
 511   }
 512
 513   // ASR and LSR have more specific patterns so they won't get here:
 514   assert(!(ImmS == 31 && !SF && Opc != BFM)
 515          && "shift should have used auto decode");
 516   assert(!(ImmS == 63 && SF && Opc != BFM)
 517          && "shift should have used auto decode");
 518
 519   // Extension instructions similarly:
 520   if (Opc == SBFM && ImmR == 0) {
 521     assert((ImmS != 7 && ImmS != 15) && "extension got here");
 522     assert((ImmS != 31 || SF == 0) && "extension got here");
 523   } else if (Opc == UBFM && ImmR == 0) {
 524     assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here");
 525   }
 526
 527   if (Opc == UBFM) {
 528     // It might be a LSL instruction, which actually takes the shift amount
 529     // itself as an MCInst operand.
 530     if (SF && (ImmS + 1) % 64 == ImmR) {
 531       Inst.setOpcode(AArch64::LSLxxi);
 532       Inst.addOperand(MCOperand::CreateImm(63 - ImmS));
 533       return MCDisassembler::Success;
 534     } else if (!SF && (ImmS + 1) % 32 == ImmR) {
 535       Inst.setOpcode(AArch64::LSLwwi);
 536       Inst.addOperand(MCOperand::CreateImm(31 - ImmS));
 537       return MCDisassembler::Success;
 538     }
 539   }
 540
 541   // Otherwise it's definitely either an extract or an insert depending on which
 542   // of ImmR or ImmS is larger.
 543   unsigned ExtractOp, InsertOp;
 544   switch (Opc) {
 545   default: llvm_unreachable("unexpected instruction trying to decode bitfield");
 546   case SBFM:
 547     ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii;
 548     InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii;
 549     break;
 550   case BFM:
 551     ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii;
 552     InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii;
 553     break;
 554   case UBFM:
 555     ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii;
 556     InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii;
 557     break;
 558   }
 559
 560   // Otherwise it's a boring insert or extract
 561   Inst.addOperand(MCOperand::CreateImm(ImmR));
 562   Inst.addOperand(MCOperand::CreateImm(ImmS));
 563
 564
 565   if (ImmS < ImmR)
 566     Inst.setOpcode(InsertOp);
 567   else
 568     Inst.setOpcode(ExtractOp);
 569
 570   return MCDisassembler::Success;
 571 }
 572
 573 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 574                                               uint64_t Address,
 575                                               const void *Decoder) {
 576   // This decoder exists to add the dummy Lane operand to the MCInst, which must
 577   // be 1 in assembly but has no other real manifestation.
 578   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 579   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 580   unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
 581
 582   if (IsToVec) {
 583     DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
 584     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 585   } else {
 586     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 587     DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
 588   }
 589
 590   // Add the lane
 591   Inst.addOperand(MCOperand::CreateImm(1));
 592
 593   return MCDisassembler::Success;
 594 }
 595
 596
 597 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
 598                                               unsigned Insn,
 599                                               uint64_t Address,
 600                                               const void *Decoder) {
 601   DecodeStatus Result = MCDisassembler::Success;
 602   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
 603   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 604   unsigned Rt2 = fieldFromInstruction(Insn, 10, 5);
 605   unsigned SImm7 = fieldFromInstruction(Insn, 15, 7);
 606   unsigned L = fieldFromInstruction(Insn, 22, 1);
 607   unsigned V = fieldFromInstruction(Insn, 26, 1);
 608   unsigned Opc = fieldFromInstruction(Insn, 30, 2);
 609
 610   // Not an official name, but it turns out that bit 23 distinguishes indexed
 611   // from non-indexed operations.
 612   unsigned Indexed = fieldFromInstruction(Insn, 23, 1);
 613
 614   if (Indexed && L == 0) {
 615     // The MCInst for an indexed store has an out operand and 4 ins:
 616     //    Rn_wb, Rt, Rt2, Rn, Imm
 617     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 618   }
 619
 620   // You shouldn't load to the same register twice in an instruction...
 621   if (L && Rt == Rt2)
 622     Result = MCDisassembler::SoftFail;
 623
 624   // ... or do any operation that writes-back to a transfer register. But note
 625   // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
 626   if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn))
 627     Result = MCDisassembler::SoftFail;
 628
 629   // Exactly how we decode the MCInst's registers depends on the Opc and V
 630   // fields of the instruction. These also obviously determine the size of the
 631   // operation so we can fill in that information while we're at it.
 632   if (V) {
 633     // The instruction operates on the FP/SIMD registers
 634     switch (Opc) {
 635     default: return MCDisassembler::Fail;
 636     case 0:
 637       DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
 638       DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder);
 639       break;
 640     case 1:
 641       DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
 642       DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder);
 643       break;
 644     case 2:
 645       DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
 646       DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder);
 647       break;
 648     }
 649   } else {
 650     switch (Opc) {
 651     default: return MCDisassembler::Fail;
 652     case 0:
 653       DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
 654       DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder);
 655       break;
 656     case 1:
 657       assert(L && "unexpected \"store signed\" attempt");
 658       DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 659       DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
 660       break;
 661     case 2:
 662       DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 663       DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
 664       break;
 665     }
 666   }
 667
 668   if (Indexed && L == 1) {
 669     // The MCInst for an indexed load has 3 out operands and an 3 ins:
 670     //    Rt, Rt2, Rn_wb, Rt2, Rn, Imm
 671     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 672   }
 673
 674
 675   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 676   Inst.addOperand(MCOperand::CreateImm(SImm7));
 677
 678   return Result;
 679 }
 680
 681 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
 682                                                        uint32_t Val,
 683                                                        uint64_t Address,
 684                                                        const void *Decoder) {
 685   unsigned Rt = fieldFromInstruction(Val, 0, 5);
 686   unsigned Rn = fieldFromInstruction(Val, 5, 5);
 687   unsigned Rt2 = fieldFromInstruction(Val, 10, 5);
 688   unsigned MemSize = fieldFromInstruction(Val, 30, 2);
 689
 690   DecodeStatus S = MCDisassembler::Success;
 691   if (Rt == Rt2) S = MCDisassembler::SoftFail;
 692
 693   switch (MemSize) {
 694     case 2:
 695       if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder)))
 696         return MCDisassembler::Fail;
 697       if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder)))
 698         return MCDisassembler::Fail;
 699       break;
 700     case 3:
 701       if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder)))
 702         return MCDisassembler::Fail;
 703       if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder)))
 704         return MCDisassembler::Fail;
 705       break;
 706     default:
 707       llvm_unreachable("Invalid MemSize in DecodeLoadPairExclusiveInstruction");
 708   }
 709
 710   if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder)))
 711     return MCDisassembler::Fail;
 712
 713   return S;
 714 }
 715
 716 template<typename SomeNamedImmMapper>
 717 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
 718                                           unsigned Val,
 719                                           uint64_t Address,
 720                                           const void *Decoder) {
 721   SomeNamedImmMapper Mapper;
 722   bool ValidNamed;
 723   Mapper.toString(Val, ValidNamed);
 724   if (ValidNamed || Mapper.validImm(Val)) {
 725     Inst.addOperand(MCOperand::CreateImm(Val));
 726     return MCDisassembler::Success;
 727   }
 728
 729   return MCDisassembler::Fail;
 730 }
 731
 732 static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
 733                                         llvm::MCInst &Inst,
 734                                         unsigned Val,
 735                                         uint64_t Address,
 736                                         const void *Decoder) {
 737   bool ValidNamed;
 738   Mapper.toString(Val, ValidNamed);
 739
 740   Inst.addOperand(MCOperand::CreateImm(Val));
 741
 742   return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail;
 743 }
 744
 745 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
 746                                      unsigned Val,
 747                                      uint64_t Address,
 748                                      const void *Decoder) {
 749   return DecodeSysRegOperand(A64SysReg::MRSMapper(), Inst, Val, Address,
 750                              Decoder);
 751 }
 752
 753 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
 754                                      unsigned Val,
 755                                      uint64_t Address,
 756                                      const void *Decoder) {
 757   return DecodeSysRegOperand(A64SysReg::MSRMapper(), Inst, Val, Address,
 758                              Decoder);
 759 }
 760
 761 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
 762                                                    unsigned Insn,
 763                                                    uint64_t Address,
 764                                                    const void *Decoder) {
 765   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
 766   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 767   unsigned Imm9 = fieldFromInstruction(Insn, 12, 9);
 768
 769   unsigned Opc = fieldFromInstruction(Insn, 22, 2);
 770   unsigned V = fieldFromInstruction(Insn, 26, 1);
 771   unsigned Size = fieldFromInstruction(Insn, 30, 2);
 772
 773   if (Opc == 0 || (V == 1 && Opc == 2)) {
 774     // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm
 775     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 776   }
 777
 778   if (V == 0 && (Opc == 2 || Size == 3)) {
 779     DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 780   } else if (V == 0) {
 781     DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
 782   } else if (V == 1 && (Opc & 2)) {
 783     DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
 784   } else {
 785     switch (Size) {
 786     case 0:
 787       DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder);
 788       break;
 789     case 1:
 790       DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder);
 791       break;
 792     case 2:
 793       DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
 794       break;
 795     case 3:
 796       DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
 797       break;
 798     }
 799   }
 800
 801   if (Opc != 0 && (V != 1 || Opc != 2)) {
 802     // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm
 803     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 804   }
 805
 806   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 807
 808   Inst.addOperand(MCOperand::CreateImm(Imm9));
 809
 810   // N.b. The official documentation says undpredictable if Rt == Rn, but this
 811   // takes place at the architectural rather than encoding level:
 812   //
 813   // "STR xzr, [sp], #4" is perfectly valid.
 814   if (V == 0 && Rt == Rn && Rn != 31)
 815     return MCDisassembler::SoftFail;
 816   else
 817     return MCDisassembler::Success;
 818 }
 819
 820 static MCDisassembler *createAArch64Disassembler(const Target &T,
 821                                                  const MCSubtargetInfo &STI) {
 822   return new AArch64Disassembler(STI, T.createMCRegInfo(""));
 823 }
 824
 825 extern "C" void LLVMInitializeAArch64Disassembler() {
 826   TargetRegistry::RegisterMCDisassembler(TheAArch64Target,
 827                                          createAArch64Disassembler);
 828 }
 829
 830 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
 831 static DecodeStatus
 832 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
 833                              uint64_t Address, const void *Decoder) {
 834   bool IsLSL = false;
 835   if (Ext == A64SE::LSL)
 836     IsLSL = true;
 837   else if (Ext != A64SE::MSL)
 838     return MCDisassembler::Fail;
 839
 840   // MSL and LSLH accepts encoded shift amount 0 or 1.
 841   if ((!IsLSL || (IsLSL && IsHalf)) && ShiftAmount != 0 && ShiftAmount != 1)
 842     return MCDisassembler::Fail;
 843
 844   // LSL  accepts encoded shift amount 0, 1, 2 or 3.
 845   if (IsLSL && ShiftAmount > 3)
 846     return MCDisassembler::Fail;
 847
 848   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 849   return MCDisassembler::Success;
 850 }