lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

   1 //===- AArch64Disassembler.cpp - Disassembler for AArch64/Thumb ISA -------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #define DEBUG_TYPE "arm-disassembler"
  11
  12 #include "AArch64.h"
  13 #include "AArch64RegisterInfo.h"
  14 #include "AArch64Subtarget.h"
  15 #include "MCTargetDesc/AArch64BaseInfo.h"
  16 #include "llvm/MC/MCInst.h"
  17 #include "llvm/MC/MCInstrDesc.h"
  18 #include "llvm/MC/MCExpr.h"
  19 #include "llvm/MC/MCContext.h"
  20 #include "llvm/MC/MCDisassembler.h"
  21 #include "llvm/MC/MCFixedLenDisassembler.h"
  22 #include "llvm/Support/Debug.h"
  23 #include "llvm/Support/MemoryObject.h"
  24 #include "llvm/Support/ErrorHandling.h"
  25 #include "llvm/Support/TargetRegistry.h"
  26 #include "llvm/Support/raw_ostream.h"
  27
  28 using namespace llvm;
  29
  30 typedef MCDisassembler::DecodeStatus DecodeStatus;
  31
  32 namespace {
  33 /// AArch64 disassembler for all AArch64 platforms.
  34 class AArch64Disassembler : public MCDisassembler {
  35   const MCRegisterInfo *RegInfo;
  36 public:
  37   /// Initializes the disassembler.
  38   ///
  39   AArch64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info)
  40     : MCDisassembler(STI), RegInfo(Info) {
  41   }
  42
  43   ~AArch64Disassembler() {
  44   }
  45
  46   /// See MCDisassembler.
  47   DecodeStatus getInstruction(MCInst &instr,
  48                               uint64_t &size,
  49                               const MemoryObject &region,
  50                               uint64_t address,
  51                               raw_ostream &vStream,
  52                               raw_ostream &cStream) const;
  53
  54   const MCRegisterInfo *getRegInfo() const { return RegInfo; }
  55 };
  56
  57 }
  58
  59 // Forward-declarations used in the auto-generated files.
  60 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  61                                          uint64_t Address, const void *Decoder);
  62 static DecodeStatus
  63 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  64                             uint64_t Address, const void *Decoder);
  65
  66 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  67                                          uint64_t Address, const void *Decoder);
  68 static DecodeStatus
  69 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  70                             uint64_t Address, const void *Decoder);
  71
  72 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  73                                          uint64_t Address, const void *Decoder);
  74 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  75                                          uint64_t Address, const void *Decoder);
  76 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  77                                          uint64_t Address, const void *Decoder);
  78 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  79                                          uint64_t Address, const void *Decoder);
  80 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  81                                          uint64_t Address, const void *Decoder);
  82 static DecodeStatus DecodeVPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  83                                               uint64_t Address, const void *Decoder);
  84 static DecodeStatus DecodeVPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  85                                               uint64_t Address, const void *Decoder);
  86
  87 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
  88                                                unsigned OptionHiS,
  89                                                uint64_t Address,
  90                                                const void *Decoder);
  91
  92
  93 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
  94                                                unsigned Imm6Bits,
  95                                                uint64_t Address,
  96                                                const void *Decoder);
  97
  98 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
  99                                                unsigned Imm6Bits,
 100                                                uint64_t Address,
 101                                                const void *Decoder);
 102
 103 template<int RegWidth>
 104 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
 105                                              unsigned FullImm,
 106                                              uint64_t Address,
 107                                              const void *Decoder);
 108
 109 template<int RegWidth>
 110 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
 111                                             unsigned Bits,
 112                                             uint64_t Address,
 113                                             const void *Decoder);
 114
 115 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
 116                                            unsigned ShiftAmount,
 117                                            uint64_t Address,
 118                                            const void *Decoder);
 119
 120 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
 121                                             unsigned ShiftAmount,
 122                                             uint64_t Address,
 123                                             const void *Decoder);
 124 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
 125                                               uint64_t Address,
 126                                               const void *Decoder);
 127
 128 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 129                                               uint64_t Address,
 130                                               const void *Decoder);
 131
 132 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
 133                                               unsigned Insn,
 134                                               uint64_t Address,
 135                                               const void *Decoder);
 136
 137 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
 138                                                        unsigned Val,
 139                                                        uint64_t Address,
 140                                                        const void *Decoder);
 141
 142 template<typename SomeNamedImmMapper>
 143 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
 144                                           unsigned Val,
 145                                           uint64_t Address,
 146                                           const void *Decoder);
 147
 148 static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper,
 149                                         llvm::MCInst &Inst,
 150                                         unsigned Val,
 151                                         uint64_t Address,
 152                                         const void *Decoder);
 153
 154 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
 155                                      unsigned Val,
 156                                      uint64_t Address,
 157                                      const void *Decoder);
 158
 159 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
 160                                      unsigned Val,
 161                                      uint64_t Address,
 162                                      const void *Decoder);
 163
 164
 165 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
 166                                                    unsigned Val,
 167                                                    uint64_t Address,
 168                                                    const void *Decoder);
 169
 170
 171 static bool Check(DecodeStatus &Out, DecodeStatus In);
 172
 173 #include "AArch64GenDisassemblerTables.inc"
 174 #include "AArch64GenInstrInfo.inc"
 175
 176 static bool Check(DecodeStatus &Out, DecodeStatus In) {
 177   switch (In) {
 178     case MCDisassembler::Success:
 179       // Out stays the same.
 180       return true;
 181     case MCDisassembler::SoftFail:
 182       Out = In;
 183       return true;
 184     case MCDisassembler::Fail:
 185       Out = In;
 186       return false;
 187   }
 188   llvm_unreachable("Invalid DecodeStatus!");
 189 }
 190
 191 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
 192                                                  const MemoryObject &Region,
 193                                                  uint64_t Address,
 194                                                  raw_ostream &os,
 195                                                  raw_ostream &cs) const {
 196   CommentStream = &cs;
 197
 198   uint8_t bytes[4];
 199
 200   // We want to read exactly 4 bytes of data.
 201   if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
 202     Size = 0;
 203     return MCDisassembler::Fail;
 204   }
 205
 206   // Encoded as a small-endian 32-bit word in the stream.
 207   uint32_t insn = (bytes[3] << 24) |
 208     (bytes[2] << 16) |
 209     (bytes[1] <<  8) |
 210     (bytes[0] <<  0);
 211
 212   // Calling the auto-generated decoder function.
 213   DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address,
 214                                           this, STI);
 215   if (result != MCDisassembler::Fail) {
 216     Size = 4;
 217     return result;
 218   }
 219
 220   MI.clear();
 221   Size = 0;
 222   return MCDisassembler::Fail;
 223 }
 224
 225 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 226   const AArch64Disassembler *Dis = static_cast<const AArch64Disassembler*>(D);
 227   return Dis->getRegInfo()->getRegClass(RC).getRegister(RegNo);
 228 }
 229
 230 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 231                                         uint64_t Address, const void *Decoder) {
 232   if (RegNo > 31)
 233     return MCDisassembler::Fail;
 234
 235   uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo);
 236   Inst.addOperand(MCOperand::CreateReg(Register));
 237   return MCDisassembler::Success;
 238 }
 239
 240 static DecodeStatus
 241 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 242                             uint64_t Address, const void *Decoder) {
 243   if (RegNo > 31)
 244     return MCDisassembler::Fail;
 245
 246   uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo);
 247   Inst.addOperand(MCOperand::CreateReg(Register));
 248   return MCDisassembler::Success;
 249 }
 250
 251 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 252                                              uint64_t Address, const void *Decoder) {
 253   if (RegNo > 31)
 254     return MCDisassembler::Fail;
 255
 256   uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo);
 257   Inst.addOperand(MCOperand::CreateReg(Register));
 258   return MCDisassembler::Success;
 259 }
 260
 261 static DecodeStatus
 262 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 263                             uint64_t Address, const void *Decoder) {
 264   if (RegNo > 31)
 265     return MCDisassembler::Fail;
 266
 267   uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo);
 268   Inst.addOperand(MCOperand::CreateReg(Register));
 269   return MCDisassembler::Success;
 270 }
 271
 272 static DecodeStatus
 273 DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 274                             uint64_t Address, const void *Decoder) {
 275   if (RegNo > 31)
 276     return MCDisassembler::Fail;
 277
 278   uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo);
 279   Inst.addOperand(MCOperand::CreateReg(Register));
 280   return MCDisassembler::Success;
 281 }
 282
 283 static DecodeStatus
 284 DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 285                             uint64_t Address, const void *Decoder) {
 286   if (RegNo > 31)
 287     return MCDisassembler::Fail;
 288
 289   uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo);
 290   Inst.addOperand(MCOperand::CreateReg(Register));
 291   return MCDisassembler::Success;
 292 }
 293
 294
 295 static DecodeStatus
 296 DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 297                             uint64_t Address, const void *Decoder) {
 298   if (RegNo > 31)
 299     return MCDisassembler::Fail;
 300
 301   uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo);
 302   Inst.addOperand(MCOperand::CreateReg(Register));
 303   return MCDisassembler::Success;
 304 }
 305
 306 static DecodeStatus
 307 DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 308                             uint64_t Address, const void *Decoder) {
 309   if (RegNo > 31)
 310     return MCDisassembler::Fail;
 311
 312   uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo);
 313   Inst.addOperand(MCOperand::CreateReg(Register));
 314   return MCDisassembler::Success;
 315 }
 316
 317
 318 static DecodeStatus
 319 DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 320                             uint64_t Address, const void *Decoder) {
 321   if (RegNo > 31)
 322     return MCDisassembler::Fail;
 323
 324   uint16_t Register = getReg(Decoder, AArch64::FPR128RegClassID, RegNo);
 325   Inst.addOperand(MCOperand::CreateReg(Register));
 326   return MCDisassembler::Success;
 327 }
 328
 329
 330 static DecodeStatus
 331 DecodeVPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 332                          uint64_t Address, const void *Decoder) {
 333   if (RegNo > 31)
 334     return MCDisassembler::Fail;
 335
 336   uint16_t Register = getReg(Decoder, AArch64::VPR64RegClassID, RegNo);
 337   Inst.addOperand(MCOperand::CreateReg(Register));
 338   return MCDisassembler::Success;
 339 }
 340
 341 static DecodeStatus
 342 DecodeVPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 343                          uint64_t Address, const void *Decoder) {
 344   if (RegNo > 31)
 345     return MCDisassembler::Fail;
 346
 347   uint16_t Register = getReg(Decoder, AArch64::VPR128RegClassID, RegNo);
 348   Inst.addOperand(MCOperand::CreateReg(Register));
 349   return MCDisassembler::Success;
 350 }
 351
 352 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
 353                                                unsigned OptionHiS,
 354                                                uint64_t Address,
 355                                                const void *Decoder) {
 356   // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1},
 357   // S}. Hence we want to check bit 1.
 358   if (!(OptionHiS & 2))
 359     return MCDisassembler::Fail;
 360
 361   Inst.addOperand(MCOperand::CreateImm(OptionHiS));
 362   return MCDisassembler::Success;
 363 }
 364
 365 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
 366                                                unsigned Imm6Bits,
 367                                                uint64_t Address,
 368                                                const void *Decoder) {
 369   // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be
 370   // between 0 and 31.
 371   if (Imm6Bits > 31)
 372     return MCDisassembler::Fail;
 373
 374   Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
 375   return MCDisassembler::Success;
 376 }
 377
 378 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
 379                                                unsigned Imm6Bits,
 380                                                uint64_t Address,
 381                                                const void *Decoder) {
 382   // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32.
 383   if (Imm6Bits < 32)
 384     return MCDisassembler::Fail;
 385
 386   Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
 387   return MCDisassembler::Success;
 388 }
 389
 390
 391 template<int RegWidth>
 392 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
 393                                              unsigned FullImm,
 394                                              uint64_t Address,
 395                                              const void *Decoder) {
 396   unsigned Imm16 = FullImm & 0xffff;
 397   unsigned Shift = FullImm >> 16;
 398
 399   if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail;
 400
 401   Inst.addOperand(MCOperand::CreateImm(Imm16));
 402   Inst.addOperand(MCOperand::CreateImm(Shift));
 403   return MCDisassembler::Success;
 404 }
 405
 406 template<int RegWidth>
 407 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
 408                                             unsigned Bits,
 409                                             uint64_t Address,
 410                                             const void *Decoder) {
 411   uint64_t Imm;
 412   if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm))
 413     return MCDisassembler::Fail;
 414
 415   Inst.addOperand(MCOperand::CreateImm(Bits));
 416   return MCDisassembler::Success;
 417 }
 418
 419
 420 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
 421                                            unsigned ShiftAmount,
 422                                            uint64_t Address,
 423                                            const void *Decoder) {
 424   // Only values 0-4 are valid for this 3-bit field
 425   if (ShiftAmount > 4)
 426     return MCDisassembler::Fail;
 427
 428   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 429   return MCDisassembler::Success;
 430 }
 431
 432 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
 433                                             unsigned ShiftAmount,
 434                                             uint64_t Address,
 435                                             const void *Decoder) {
 436   // Only values below 32 are valid for a 32-bit register
 437   if (ShiftAmount > 31)
 438     return MCDisassembler::Fail;
 439
 440   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 441   return MCDisassembler::Success;
 442 }
 443
 444 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
 445                                               uint64_t Address,
 446                                               const void *Decoder) {
 447   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 448   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 449   unsigned ImmS = fieldFromInstruction(Insn, 10, 6);
 450   unsigned ImmR = fieldFromInstruction(Insn, 16, 6);
 451   unsigned SF = fieldFromInstruction(Insn, 31, 1);
 452
 453   // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise
 454   // out assertions that it thinks should never be hit.
 455   enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc;
 456   Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2);
 457
 458   if (!SF) {
 459     // ImmR and ImmS must be between 0 and 31 for 32-bit instructions.
 460     if (ImmR > 31 || ImmS > 31)
 461       return MCDisassembler::Fail;
 462   }
 463
 464   if (SF) {
 465     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 466     // BFM MCInsts use Rd as a source too.
 467     if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 468     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 469   } else {
 470     DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
 471     // BFM MCInsts use Rd as a source too.
 472     if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
 473     DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
 474   }
 475
 476   // ASR and LSR have more specific patterns so they won't get here:
 477   assert(!(ImmS == 31 && !SF && Opc != BFM) && "shift should have used auto decode");
 478   assert(!(ImmS == 63 && SF && Opc != BFM) && "shift should have used auto decode");
 479
 480   // Extension instructions similarly:
 481   if (Opc == SBFM && ImmR == 0) {
 482     assert((ImmS != 7 && ImmS != 15) && "extension got here");
 483     assert((ImmS != 31 || SF == 0) && "extension got here");
 484   } else if (Opc == UBFM && ImmR == 0) {
 485     assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here");
 486   }
 487
 488   if (Opc == UBFM) {
 489     // It might be a LSL instruction, which actually takes the shift amount
 490     // itself as an MCInst operand.
 491     if (SF && (ImmS + 1) % 64 == ImmR) {
 492       Inst.setOpcode(AArch64::LSLxxi);
 493       Inst.addOperand(MCOperand::CreateImm(63 - ImmS));
 494       return MCDisassembler::Success;
 495     } else if (!SF && (ImmS + 1) % 32 == ImmR) {
 496       Inst.setOpcode(AArch64::LSLwwi);
 497       Inst.addOperand(MCOperand::CreateImm(31 - ImmS));
 498       return MCDisassembler::Success;
 499     }
 500   }
 501
 502   // Otherwise it's definitely either an extract or an insert depending on which
 503   // of ImmR or ImmS is larger.
 504   unsigned ExtractOp, InsertOp;
 505   switch (Opc) {
 506   default: llvm_unreachable("unexpected instruction trying to decode bitfield");
 507   case SBFM:
 508     ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii;
 509     InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii;
 510     break;
 511   case BFM:
 512     ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii;
 513     InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii;
 514     break;
 515   case UBFM:
 516     ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii;
 517     InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii;
 518     break;
 519   }
 520
 521   // Otherwise it's a boring insert or extract
 522   Inst.addOperand(MCOperand::CreateImm(ImmR));
 523   Inst.addOperand(MCOperand::CreateImm(ImmS));
 524
 525
 526   if (ImmS < ImmR)
 527     Inst.setOpcode(InsertOp);
 528   else
 529     Inst.setOpcode(ExtractOp);
 530
 531   return MCDisassembler::Success;
 532 }
 533
 534 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 535                                               uint64_t Address,
 536                                               const void *Decoder) {
 537   // This decoder exists to add the dummy Lane operand to the MCInst, which must
 538   // be 1 in assembly but has no other real manifestation.
 539   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 540   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 541   unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
 542
 543   if (IsToVec) {
 544     DecodeVPR128RegisterClass(Inst, Rd, Address, Decoder);
 545     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 546   } else {
 547     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 548     DecodeVPR128RegisterClass(Inst, Rn, Address, Decoder);
 549   }
 550
 551   // Add the lane
 552   Inst.addOperand(MCOperand::CreateImm(1));
 553
 554   return MCDisassembler::Success;
 555 }
 556
 557
 558 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
 559                                               unsigned Insn,
 560                                               uint64_t Address,
 561                                               const void *Decoder) {
 562   DecodeStatus Result = MCDisassembler::Success;
 563   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
 564   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 565   unsigned Rt2 = fieldFromInstruction(Insn, 10, 5);
 566   unsigned SImm7 = fieldFromInstruction(Insn, 15, 7);
 567   unsigned L = fieldFromInstruction(Insn, 22, 1);
 568   unsigned V = fieldFromInstruction(Insn, 26, 1);
 569   unsigned Opc = fieldFromInstruction(Insn, 30, 2);
 570
 571   // Not an official name, but it turns out that bit 23 distinguishes indexed
 572   // from non-indexed operations.
 573   unsigned Indexed = fieldFromInstruction(Insn, 23, 1);
 574
 575   if (Indexed && L == 0) {
 576     // The MCInst for an indexed store has an out operand and 4 ins:
 577     //    Rn_wb, Rt, Rt2, Rn, Imm
 578     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 579   }
 580
 581   // You shouldn't load to the same register twice in an instruction...
 582   if (L && Rt == Rt2)
 583     Result = MCDisassembler::SoftFail;
 584
 585   // ... or do any operation that writes-back to a transfer register. But note
 586   // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
 587   if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn))
 588     Result = MCDisassembler::SoftFail;
 589
 590   // Exactly how we decode the MCInst's registers depends on the Opc and V
 591   // fields of the instruction. These also obviously determine the size of the
 592   // operation so we can fill in that information while we're at it.
 593   if (V) {
 594     // The instruction operates on the FP/SIMD registers
 595     switch (Opc) {
 596     default: return MCDisassembler::Fail;
 597     case 0:
 598       DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
 599       DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder);
 600       break;
 601     case 1:
 602       DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
 603       DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder);
 604       break;
 605     case 2:
 606       DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
 607       DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder);
 608       break;
 609     }
 610   } else {
 611     switch (Opc) {
 612     default: return MCDisassembler::Fail;
 613     case 0:
 614       DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
 615       DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder);
 616       break;
 617     case 1:
 618       assert(L && "unexpected \"store signed\" attempt");
 619       DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 620       DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
 621       break;
 622     case 2:
 623       DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 624       DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
 625       break;
 626     }
 627   }
 628
 629   if (Indexed && L == 1) {
 630     // The MCInst for an indexed load has 3 out operands and an 3 ins:
 631     //    Rt, Rt2, Rn_wb, Rt2, Rn, Imm
 632     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 633   }
 634
 635
 636   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 637   Inst.addOperand(MCOperand::CreateImm(SImm7));
 638
 639   return Result;
 640 }
 641
 642 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
 643                                                        uint32_t Val,
 644                                                        uint64_t Address,
 645                                                        const void *Decoder) {
 646   unsigned Rt = fieldFromInstruction(Val, 0, 5);
 647   unsigned Rn = fieldFromInstruction(Val, 5, 5);
 648   unsigned Rt2 = fieldFromInstruction(Val, 10, 5);
 649   unsigned MemSize = fieldFromInstruction(Val, 30, 2);
 650
 651   DecodeStatus S = MCDisassembler::Success;
 652   if (Rt == Rt2) S = MCDisassembler::SoftFail;
 653
 654   switch (MemSize) {
 655     case 2:
 656       if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder)))
 657         return MCDisassembler::Fail;
 658       if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder)))
 659         return MCDisassembler::Fail;
 660       break;
 661     case 3:
 662       if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder)))
 663         return MCDisassembler::Fail;
 664       if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder)))
 665         return MCDisassembler::Fail;
 666       break;
 667     default:
 668       llvm_unreachable("Invalid MemSize in DecodeLoadPairExclusiveInstruction");
 669   }
 670
 671   if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder)))
 672     return MCDisassembler::Fail;
 673
 674   return S;
 675 }
 676
 677 template<typename SomeNamedImmMapper>
 678 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
 679                                           unsigned Val,
 680                                           uint64_t Address,
 681                                           const void *Decoder) {
 682   SomeNamedImmMapper Mapper;
 683   bool ValidNamed;
 684   Mapper.toString(Val, ValidNamed);
 685   if (ValidNamed || Mapper.validImm(Val)) {
 686     Inst.addOperand(MCOperand::CreateImm(Val));
 687     return MCDisassembler::Success;
 688   }
 689
 690   return MCDisassembler::Fail;
 691 }
 692
 693 static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
 694                                         llvm::MCInst &Inst,
 695                                         unsigned Val,
 696                                         uint64_t Address,
 697                                         const void *Decoder) {
 698   bool ValidNamed;
 699   Mapper.toString(Val, ValidNamed);
 700
 701   Inst.addOperand(MCOperand::CreateImm(Val));
 702
 703   return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail;
 704 }
 705
 706 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
 707                                      unsigned Val,
 708                                      uint64_t Address,
 709                                      const void *Decoder) {
 710   return DecodeSysRegOperand(A64SysReg::MRSMapper(), Inst, Val, Address,
 711                              Decoder);
 712 }
 713
 714 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
 715                                      unsigned Val,
 716                                      uint64_t Address,
 717                                      const void *Decoder) {
 718   return DecodeSysRegOperand(A64SysReg::MSRMapper(), Inst, Val, Address,
 719                              Decoder);
 720 }
 721
 722 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
 723                                                    unsigned Insn,
 724                                                    uint64_t Address,
 725                                                    const void *Decoder) {
 726   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
 727   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 728   unsigned Imm9 = fieldFromInstruction(Insn, 12, 9);
 729
 730   unsigned Opc = fieldFromInstruction(Insn, 22, 2);
 731   unsigned V = fieldFromInstruction(Insn, 26, 1);
 732   unsigned Size = fieldFromInstruction(Insn, 30, 2);
 733
 734   if (Opc == 0 || (V == 1 && Opc == 2)) {
 735     // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm
 736     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 737   }
 738
 739   if (V == 0 && (Opc == 2 || Size == 3)) {
 740     DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 741   } else if (V == 0) {
 742     DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
 743   } else if (V == 1 && (Opc & 2)) {
 744     DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
 745   } else {
 746     switch (Size) {
 747     case 0:
 748       DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder);
 749       break;
 750     case 1:
 751       DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder);
 752       break;
 753     case 2:
 754       DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
 755       break;
 756     case 3:
 757       DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
 758       break;
 759     }
 760   }
 761
 762   if (Opc != 0 && (V != 1 || Opc != 2)) {
 763     // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm
 764     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 765   }
 766
 767   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 768
 769   Inst.addOperand(MCOperand::CreateImm(Imm9));
 770
 771   // N.b. The official documentation says undpredictable if Rt == Rn, but this
 772   // takes place at the architectural rather than encoding level:
 773   //
 774   // "STR xzr, [sp], #4" is perfectly valid.
 775   if (V == 0 && Rt == Rn && Rn != 31)
 776     return MCDisassembler::SoftFail;
 777   else
 778     return MCDisassembler::Success;
 779 }
 780
 781 static MCDisassembler *createAArch64Disassembler(const Target &T,
 782                                                  const MCSubtargetInfo &STI) {
 783   return new AArch64Disassembler(STI, T.createMCRegInfo(""));
 784 }
 785
 786 extern "C" void LLVMInitializeAArch64Disassembler() {
 787   TargetRegistry::RegisterMCDisassembler(TheAArch64Target,
 788                                          createAArch64Disassembler);
 789 }
 790
 791