lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

   1 //===- AArch64Disassembler.cpp - Disassembler for AArch64/Thumb ISA -------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #define DEBUG_TYPE "arm-disassembler"
  11
  12 #include "AArch64.h"
  13 #include "AArch64RegisterInfo.h"
  14 #include "AArch64Subtarget.h"
  15 #include "MCTargetDesc/AArch64BaseInfo.h"
  16 #include "llvm/MC/MCInst.h"
  17 #include "llvm/MC/MCInstrDesc.h"
  18 #include "llvm/MC/MCExpr.h"
  19 #include "llvm/MC/MCContext.h"
  20 #include "llvm/MC/MCDisassembler.h"
  21 #include "llvm/MC/MCFixedLenDisassembler.h"
  22 #include "llvm/Support/Debug.h"
  23 #include "llvm/Support/MemoryObject.h"
  24 #include "llvm/Support/ErrorHandling.h"
  25 #include "llvm/Support/TargetRegistry.h"
  26 #include "llvm/Support/raw_ostream.h"
  27
  28 using namespace llvm;
  29
  30 typedef MCDisassembler::DecodeStatus DecodeStatus;
  31
  32 namespace {
  33 /// AArch64 disassembler for all AArch64 platforms.
  34 class AArch64Disassembler : public MCDisassembler {
  35   const MCRegisterInfo *RegInfo;
  36 public:
  37   /// Initializes the disassembler.
  38   ///
  39   AArch64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info)
  40     : MCDisassembler(STI), RegInfo(Info) {
  41   }
  42
  43   ~AArch64Disassembler() {
  44   }
  45
  46   /// See MCDisassembler.
  47   DecodeStatus getInstruction(MCInst &instr,
  48                               uint64_t &size,
  49                               const MemoryObject &region,
  50                               uint64_t address,
  51                               raw_ostream &vStream,
  52                               raw_ostream &cStream) const;
  53
  54   const MCRegisterInfo *getRegInfo() const { return RegInfo; }
  55 };
  56
  57 }
  58
  59 // Forward-declarations used in the auto-generated files.
  60 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  61                                          uint64_t Address, const void *Decoder);
  62 static DecodeStatus
  63 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  64                             uint64_t Address, const void *Decoder);
  65
  66 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  67                                          uint64_t Address, const void *Decoder);
  68 static DecodeStatus
  69 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  70                             uint64_t Address, const void *Decoder);
  71
  72 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  73                                          uint64_t Address, const void *Decoder);
  74 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  75                                          uint64_t Address, const void *Decoder);
  76 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  77                                          uint64_t Address, const void *Decoder);
  78 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  79                                          uint64_t Address, const void *Decoder);
  80 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  81                                          uint64_t Address, const void *Decoder);
  82 static DecodeStatus DecodeVPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  83                                               uint64_t Address, const void *Decoder);
  84
  85 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
  86                                                unsigned OptionHiS,
  87                                                uint64_t Address,
  88                                                const void *Decoder);
  89
  90
  91 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
  92                                                unsigned Imm6Bits,
  93                                                uint64_t Address,
  94                                                const void *Decoder);
  95
  96 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
  97                                                unsigned Imm6Bits,
  98                                                uint64_t Address,
  99                                                const void *Decoder);
 100
 101 template<int RegWidth>
 102 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
 103                                              unsigned FullImm,
 104                                              uint64_t Address,
 105                                              const void *Decoder);
 106
 107 template<int RegWidth>
 108 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
 109                                             unsigned Bits,
 110                                             uint64_t Address,
 111                                             const void *Decoder);
 112
 113 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
 114                                            unsigned ShiftAmount,
 115                                            uint64_t Address,
 116                                            const void *Decoder);
 117
 118 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
 119                                             unsigned ShiftAmount,
 120                                             uint64_t Address,
 121                                             const void *Decoder);
 122 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
 123                                               uint64_t Address,
 124                                               const void *Decoder);
 125
 126 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 127                                               uint64_t Address,
 128                                               const void *Decoder);
 129
 130 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
 131                                               unsigned Insn,
 132                                               uint64_t Address,
 133                                               const void *Decoder);
 134
 135 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
 136                                                        unsigned Val,
 137                                                        uint64_t Address,
 138                                                        const void *Decoder);
 139
 140 template<typename SomeNamedImmMapper>
 141 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
 142                                           unsigned Val,
 143                                           uint64_t Address,
 144                                           const void *Decoder);
 145
 146 static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper,
 147                                         llvm::MCInst &Inst,
 148                                         unsigned Val,
 149                                         uint64_t Address,
 150                                         const void *Decoder);
 151
 152 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
 153                                      unsigned Val,
 154                                      uint64_t Address,
 155                                      const void *Decoder);
 156
 157 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
 158                                      unsigned Val,
 159                                      uint64_t Address,
 160                                      const void *Decoder);
 161
 162
 163 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
 164                                                    unsigned Val,
 165                                                    uint64_t Address,
 166                                                    const void *Decoder);
 167
 168
 169 static bool Check(DecodeStatus &Out, DecodeStatus In);
 170
 171 #include "AArch64GenDisassemblerTables.inc"
 172 #include "AArch64GenInstrInfo.inc"
 173
 174 static bool Check(DecodeStatus &Out, DecodeStatus In) {
 175   switch (In) {
 176     case MCDisassembler::Success:
 177       // Out stays the same.
 178       return true;
 179     case MCDisassembler::SoftFail:
 180       Out = In;
 181       return true;
 182     case MCDisassembler::Fail:
 183       Out = In;
 184       return false;
 185   }
 186   llvm_unreachable("Invalid DecodeStatus!");
 187 }
 188
 189 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
 190                                                  const MemoryObject &Region,
 191                                                  uint64_t Address,
 192                                                  raw_ostream &os,
 193                                                  raw_ostream &cs) const {
 194   CommentStream = &cs;
 195
 196   uint8_t bytes[4];
 197
 198   // We want to read exactly 4 bytes of data.
 199   if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
 200     Size = 0;
 201     return MCDisassembler::Fail;
 202   }
 203
 204   // Encoded as a small-endian 32-bit word in the stream.
 205   uint32_t insn = (bytes[3] << 24) |
 206     (bytes[2] << 16) |
 207     (bytes[1] <<  8) |
 208     (bytes[0] <<  0);
 209
 210   // Calling the auto-generated decoder function.
 211   DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address,
 212                                           this, STI);
 213   if (result != MCDisassembler::Fail) {
 214     Size = 4;
 215     return result;
 216   }
 217
 218   MI.clear();
 219   Size = 0;
 220   return MCDisassembler::Fail;
 221 }
 222
 223 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 224   const AArch64Disassembler *Dis = static_cast<const AArch64Disassembler*>(D);
 225   return Dis->getRegInfo()->getRegClass(RC).getRegister(RegNo);
 226 }
 227
 228 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 229                                         uint64_t Address, const void *Decoder) {
 230   if (RegNo > 31)
 231     return MCDisassembler::Fail;
 232
 233   uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo);
 234   Inst.addOperand(MCOperand::CreateReg(Register));
 235   return MCDisassembler::Success;
 236 }
 237
 238 static DecodeStatus
 239 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 240                             uint64_t Address, const void *Decoder) {
 241   if (RegNo > 31)
 242     return MCDisassembler::Fail;
 243
 244   uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo);
 245   Inst.addOperand(MCOperand::CreateReg(Register));
 246   return MCDisassembler::Success;
 247 }
 248
 249 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 250                                              uint64_t Address, const void *Decoder) {
 251   if (RegNo > 31)
 252     return MCDisassembler::Fail;
 253
 254   uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo);
 255   Inst.addOperand(MCOperand::CreateReg(Register));
 256   return MCDisassembler::Success;
 257 }
 258
 259 static DecodeStatus
 260 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 261                             uint64_t Address, const void *Decoder) {
 262   if (RegNo > 31)
 263     return MCDisassembler::Fail;
 264
 265   uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo);
 266   Inst.addOperand(MCOperand::CreateReg(Register));
 267   return MCDisassembler::Success;
 268 }
 269
 270 static DecodeStatus
 271 DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 272                             uint64_t Address, const void *Decoder) {
 273   if (RegNo > 31)
 274     return MCDisassembler::Fail;
 275
 276   uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo);
 277   Inst.addOperand(MCOperand::CreateReg(Register));
 278   return MCDisassembler::Success;
 279 }
 280
 281 static DecodeStatus
 282 DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 283                             uint64_t Address, const void *Decoder) {
 284   if (RegNo > 31)
 285     return MCDisassembler::Fail;
 286
 287   uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo);
 288   Inst.addOperand(MCOperand::CreateReg(Register));
 289   return MCDisassembler::Success;
 290 }
 291
 292
 293 static DecodeStatus
 294 DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 295                             uint64_t Address, const void *Decoder) {
 296   if (RegNo > 31)
 297     return MCDisassembler::Fail;
 298
 299   uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo);
 300   Inst.addOperand(MCOperand::CreateReg(Register));
 301   return MCDisassembler::Success;
 302 }
 303
 304 static DecodeStatus
 305 DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 306                             uint64_t Address, const void *Decoder) {
 307   if (RegNo > 31)
 308     return MCDisassembler::Fail;
 309
 310   uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo);
 311   Inst.addOperand(MCOperand::CreateReg(Register));
 312   return MCDisassembler::Success;
 313 }
 314
 315
 316 static DecodeStatus
 317 DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 318                             uint64_t Address, const void *Decoder) {
 319   if (RegNo > 31)
 320     return MCDisassembler::Fail;
 321
 322   uint16_t Register = getReg(Decoder, AArch64::FPR128RegClassID, RegNo);
 323   Inst.addOperand(MCOperand::CreateReg(Register));
 324   return MCDisassembler::Success;
 325 }
 326
 327 static DecodeStatus
 328 DecodeVPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 329                          uint64_t Address, const void *Decoder) {
 330   if (RegNo > 31)
 331     return MCDisassembler::Fail;
 332
 333   uint16_t Register = getReg(Decoder, AArch64::VPR128RegClassID, RegNo);
 334   Inst.addOperand(MCOperand::CreateReg(Register));
 335   return MCDisassembler::Success;
 336 }
 337
 338 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
 339                                                unsigned OptionHiS,
 340                                                uint64_t Address,
 341                                                const void *Decoder) {
 342   // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1},
 343   // S}. Hence we want to check bit 1.
 344   if (!(OptionHiS & 2))
 345     return MCDisassembler::Fail;
 346
 347   Inst.addOperand(MCOperand::CreateImm(OptionHiS));
 348   return MCDisassembler::Success;
 349 }
 350
 351 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
 352                                                unsigned Imm6Bits,
 353                                                uint64_t Address,
 354                                                const void *Decoder) {
 355   // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be
 356   // between 0 and 31.
 357   if (Imm6Bits > 31)
 358     return MCDisassembler::Fail;
 359
 360   Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
 361   return MCDisassembler::Success;
 362 }
 363
 364 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
 365                                                unsigned Imm6Bits,
 366                                                uint64_t Address,
 367                                                const void *Decoder) {
 368   // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32.
 369   if (Imm6Bits < 32)
 370     return MCDisassembler::Fail;
 371
 372   Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
 373   return MCDisassembler::Success;
 374 }
 375
 376
 377 template<int RegWidth>
 378 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
 379                                              unsigned FullImm,
 380                                              uint64_t Address,
 381                                              const void *Decoder) {
 382   unsigned Imm16 = FullImm & 0xffff;
 383   unsigned Shift = FullImm >> 16;
 384
 385   if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail;
 386
 387   Inst.addOperand(MCOperand::CreateImm(Imm16));
 388   Inst.addOperand(MCOperand::CreateImm(Shift));
 389   return MCDisassembler::Success;
 390 }
 391
 392 template<int RegWidth>
 393 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
 394                                             unsigned Bits,
 395                                             uint64_t Address,
 396                                             const void *Decoder) {
 397   uint64_t Imm;
 398   if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm))
 399     return MCDisassembler::Fail;
 400
 401   Inst.addOperand(MCOperand::CreateImm(Bits));
 402   return MCDisassembler::Success;
 403 }
 404
 405
 406 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
 407                                            unsigned ShiftAmount,
 408                                            uint64_t Address,
 409                                            const void *Decoder) {
 410   // Only values 0-4 are valid for this 3-bit field
 411   if (ShiftAmount > 4)
 412     return MCDisassembler::Fail;
 413
 414   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 415   return MCDisassembler::Success;
 416 }
 417
 418 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
 419                                             unsigned ShiftAmount,
 420                                             uint64_t Address,
 421                                             const void *Decoder) {
 422   // Only values below 32 are valid for a 32-bit register
 423   if (ShiftAmount > 31)
 424     return MCDisassembler::Fail;
 425
 426   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 427   return MCDisassembler::Success;
 428 }
 429
 430 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
 431                                               uint64_t Address,
 432                                               const void *Decoder) {
 433   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 434   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 435   unsigned ImmS = fieldFromInstruction(Insn, 10, 6);
 436   unsigned ImmR = fieldFromInstruction(Insn, 16, 6);
 437   unsigned SF = fieldFromInstruction(Insn, 31, 1);
 438
 439   // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise
 440   // out assertions that it thinks should never be hit.
 441   enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc;
 442   Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2);
 443
 444   if (!SF) {
 445     // ImmR and ImmS must be between 0 and 31 for 32-bit instructions.
 446     if (ImmR > 31 || ImmS > 31)
 447       return MCDisassembler::Fail;
 448   }
 449
 450   if (SF) {
 451     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 452     // BFM MCInsts use Rd as a source too.
 453     if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 454     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 455   } else {
 456     DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
 457     // BFM MCInsts use Rd as a source too.
 458     if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
 459     DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
 460   }
 461
 462   // ASR and LSR have more specific patterns so they won't get here:
 463   assert(!(ImmS == 31 && !SF && Opc != BFM) && "shift should have used auto decode");
 464   assert(!(ImmS == 63 && SF && Opc != BFM) && "shift should have used auto decode");
 465
 466   // Extension instructions similarly:
 467   if (Opc == SBFM && ImmR == 0) {
 468     assert((ImmS != 7 && ImmS != 15) && "extension got here");
 469     assert((ImmS != 31 || SF == 0) && "extension got here");
 470   } else if (Opc == UBFM && ImmR == 0) {
 471     assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here");
 472   }
 473
 474   if (Opc == UBFM) {
 475     // It might be a LSL instruction, which actually takes the shift amount
 476     // itself as an MCInst operand.
 477     if (SF && (ImmS + 1) % 64 == ImmR) {
 478       Inst.setOpcode(AArch64::LSLxxi);
 479       Inst.addOperand(MCOperand::CreateImm(63 - ImmS));
 480       return MCDisassembler::Success;
 481     } else if (!SF && (ImmS + 1) % 32 == ImmR) {
 482       Inst.setOpcode(AArch64::LSLwwi);
 483       Inst.addOperand(MCOperand::CreateImm(31 - ImmS));
 484       return MCDisassembler::Success;
 485     }
 486   }
 487
 488   // Otherwise it's definitely either an extract or an insert depending on which
 489   // of ImmR or ImmS is larger.
 490   unsigned ExtractOp, InsertOp;
 491   switch (Opc) {
 492   default: llvm_unreachable("unexpected instruction trying to decode bitfield");
 493   case SBFM:
 494     ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii;
 495     InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii;
 496     break;
 497   case BFM:
 498     ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii;
 499     InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii;
 500     break;
 501   case UBFM:
 502     ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii;
 503     InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii;
 504     break;
 505   }
 506
 507   // Otherwise it's a boring insert or extract
 508   Inst.addOperand(MCOperand::CreateImm(ImmR));
 509   Inst.addOperand(MCOperand::CreateImm(ImmS));
 510
 511
 512   if (ImmS < ImmR)
 513     Inst.setOpcode(InsertOp);
 514   else
 515     Inst.setOpcode(ExtractOp);
 516
 517   return MCDisassembler::Success;
 518 }
 519
 520 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 521                                               uint64_t Address,
 522                                               const void *Decoder) {
 523   // This decoder exists to add the dummy Lane operand to the MCInst, which must
 524   // be 1 in assembly but has no other real manifestation.
 525   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 526   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 527   unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
 528
 529   if (IsToVec) {
 530     DecodeVPR128RegisterClass(Inst, Rd, Address, Decoder);
 531     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 532   } else {
 533     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 534     DecodeVPR128RegisterClass(Inst, Rn, Address, Decoder);
 535   }
 536
 537   // Add the lane
 538   Inst.addOperand(MCOperand::CreateImm(1));
 539
 540   return MCDisassembler::Success;
 541 }
 542
 543
 544 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
 545                                               unsigned Insn,
 546                                               uint64_t Address,
 547                                               const void *Decoder) {
 548   DecodeStatus Result = MCDisassembler::Success;
 549   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
 550   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 551   unsigned Rt2 = fieldFromInstruction(Insn, 10, 5);
 552   unsigned SImm7 = fieldFromInstruction(Insn, 15, 7);
 553   unsigned L = fieldFromInstruction(Insn, 22, 1);
 554   unsigned V = fieldFromInstruction(Insn, 26, 1);
 555   unsigned Opc = fieldFromInstruction(Insn, 30, 2);
 556
 557   // Not an official name, but it turns out that bit 23 distinguishes indexed
 558   // from non-indexed operations.
 559   unsigned Indexed = fieldFromInstruction(Insn, 23, 1);
 560
 561   if (Indexed && L == 0) {
 562     // The MCInst for an indexed store has an out operand and 4 ins:
 563     //    Rn_wb, Rt, Rt2, Rn, Imm
 564     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 565   }
 566
 567   // You shouldn't load to the same register twice in an instruction...
 568   if (L && Rt == Rt2)
 569     Result = MCDisassembler::SoftFail;
 570
 571   // ... or do any operation that writes-back to a transfer register. But note
 572   // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
 573   if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn))
 574     Result = MCDisassembler::SoftFail;
 575
 576   // Exactly how we decode the MCInst's registers depends on the Opc and V
 577   // fields of the instruction. These also obviously determine the size of the
 578   // operation so we can fill in that information while we're at it.
 579   if (V) {
 580     // The instruction operates on the FP/SIMD registers
 581     switch (Opc) {
 582     default: return MCDisassembler::Fail;
 583     case 0:
 584       DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
 585       DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder);
 586       break;
 587     case 1:
 588       DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
 589       DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder);
 590       break;
 591     case 2:
 592       DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
 593       DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder);
 594       break;
 595     }
 596   } else {
 597     switch (Opc) {
 598     default: return MCDisassembler::Fail;
 599     case 0:
 600       DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
 601       DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder);
 602       break;
 603     case 1:
 604       assert(L && "unexpected \"store signed\" attempt");
 605       DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 606       DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
 607       break;
 608     case 2:
 609       DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 610       DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
 611       break;
 612     }
 613   }
 614
 615   if (Indexed && L == 1) {
 616     // The MCInst for an indexed load has 3 out operands and an 3 ins:
 617     //    Rt, Rt2, Rn_wb, Rt2, Rn, Imm
 618     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 619   }
 620
 621
 622   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 623   Inst.addOperand(MCOperand::CreateImm(SImm7));
 624
 625   return Result;
 626 }
 627
 628 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
 629                                                        uint32_t Val,
 630                                                        uint64_t Address,
 631                                                        const void *Decoder) {
 632   unsigned Rt = fieldFromInstruction(Val, 0, 5);
 633   unsigned Rn = fieldFromInstruction(Val, 5, 5);
 634   unsigned Rt2 = fieldFromInstruction(Val, 10, 5);
 635   unsigned MemSize = fieldFromInstruction(Val, 30, 2);
 636
 637   DecodeStatus S = MCDisassembler::Success;
 638   if (Rt == Rt2) S = MCDisassembler::SoftFail;
 639
 640   switch (MemSize) {
 641     case 2:
 642       if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder)))
 643         return MCDisassembler::Fail;
 644       if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder)))
 645         return MCDisassembler::Fail;
 646       break;
 647     case 3:
 648       if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder)))
 649         return MCDisassembler::Fail;
 650       if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder)))
 651         return MCDisassembler::Fail;
 652       break;
 653     default:
 654       llvm_unreachable("Invalid MemSize in DecodeLoadPairExclusiveInstruction");
 655   }
 656
 657   if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder)))
 658     return MCDisassembler::Fail;
 659
 660   return S;
 661 }
 662
 663 template<typename SomeNamedImmMapper>
 664 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
 665                                           unsigned Val,
 666                                           uint64_t Address,
 667                                           const void *Decoder) {
 668   SomeNamedImmMapper Mapper;
 669   bool ValidNamed;
 670   Mapper.toString(Val, ValidNamed);
 671   if (ValidNamed || Mapper.validImm(Val)) {
 672     Inst.addOperand(MCOperand::CreateImm(Val));
 673     return MCDisassembler::Success;
 674   }
 675
 676   return MCDisassembler::Fail;
 677 }
 678
 679 static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
 680                                         llvm::MCInst &Inst,
 681                                         unsigned Val,
 682                                         uint64_t Address,
 683                                         const void *Decoder) {
 684   bool ValidNamed;
 685   Mapper.toString(Val, ValidNamed);
 686
 687   Inst.addOperand(MCOperand::CreateImm(Val));
 688
 689   return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail;
 690 }
 691
 692 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
 693                                      unsigned Val,
 694                                      uint64_t Address,
 695                                      const void *Decoder) {
 696   return DecodeSysRegOperand(A64SysReg::MRSMapper(), Inst, Val, Address,
 697                              Decoder);
 698 }
 699
 700 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
 701                                      unsigned Val,
 702                                      uint64_t Address,
 703                                      const void *Decoder) {
 704   return DecodeSysRegOperand(A64SysReg::MSRMapper(), Inst, Val, Address,
 705                              Decoder);
 706 }
 707
 708 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
 709                                                    unsigned Insn,
 710                                                    uint64_t Address,
 711                                                    const void *Decoder) {
 712   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
 713   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 714   unsigned Imm9 = fieldFromInstruction(Insn, 12, 9);
 715
 716   unsigned Opc = fieldFromInstruction(Insn, 22, 2);
 717   unsigned V = fieldFromInstruction(Insn, 26, 1);
 718   unsigned Size = fieldFromInstruction(Insn, 30, 2);
 719
 720   if (Opc == 0 || (V == 1 && Opc == 2)) {
 721     // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm
 722     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 723   }
 724
 725   if (V == 0 && (Opc == 2 || Size == 3)) {
 726     DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 727   } else if (V == 0) {
 728     DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
 729   } else if (V == 1 && (Opc & 2)) {
 730     DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
 731   } else {
 732     switch (Size) {
 733     case 0:
 734       DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder);
 735       break;
 736     case 1:
 737       DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder);
 738       break;
 739     case 2:
 740       DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
 741       break;
 742     case 3:
 743       DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
 744       break;
 745     }
 746   }
 747
 748   if (Opc != 0 && (V != 1 || Opc != 2)) {
 749     // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm
 750     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 751   }
 752
 753   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 754
 755   Inst.addOperand(MCOperand::CreateImm(Imm9));
 756
 757   // N.b. The official documentation says undpredictable if Rt == Rn, but this
 758   // takes place at the architectural rather than encoding level:
 759   //
 760   // "STR xzr, [sp], #4" is perfectly valid.
 761   if (V == 0 && Rt == Rn && Rn != 31)
 762     return MCDisassembler::SoftFail;
 763   else
 764     return MCDisassembler::Success;
 765 }
 766
 767 static MCDisassembler *createAArch64Disassembler(const Target &T,
 768                                                  const MCSubtargetInfo &STI) {
 769   return new AArch64Disassembler(STI, T.createMCRegInfo(""));
 770 }
 771
 772 extern "C" void LLVMInitializeAArch64Disassembler() {
 773   TargetRegistry::RegisterMCDisassembler(TheAArch64Target,
 774                                          createAArch64Disassembler);
 775 }
 776
 777