lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

   1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the functions necessary to decode AArch64 instruction
  11 // bitpatterns into MCInsts (with the help of TableGenerated information from
  12 // the instruction definitions).
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #define DEBUG_TYPE "arm-disassembler"
  17
  18 #include "AArch64.h"
  19 #include "AArch64RegisterInfo.h"
  20 #include "AArch64Subtarget.h"
  21 #include "Utils/AArch64BaseInfo.h"
  22 #include "llvm/MC/MCInst.h"
  23 #include "llvm/MC/MCInstrDesc.h"
  24 #include "llvm/MC/MCExpr.h"
  25 #include "llvm/MC/MCContext.h"
  26 #include "llvm/MC/MCDisassembler.h"
  27 #include "llvm/MC/MCFixedLenDisassembler.h"
  28 #include "llvm/Support/Debug.h"
  29 #include "llvm/Support/MemoryObject.h"
  30 #include "llvm/Support/ErrorHandling.h"
  31 #include "llvm/Support/TargetRegistry.h"
  32 #include "llvm/Support/raw_ostream.h"
  33
  34 using namespace llvm;
  35
  36 typedef MCDisassembler::DecodeStatus DecodeStatus;
  37
  38 namespace {
  39 /// AArch64 disassembler for all AArch64 platforms.
  40 class AArch64Disassembler : public MCDisassembler {
  41   OwningPtr<const MCRegisterInfo> RegInfo;
  42 public:
  43   /// Initializes the disassembler.
  44   ///
  45   AArch64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info)
  46     : MCDisassembler(STI), RegInfo(Info) {
  47   }
  48
  49   ~AArch64Disassembler() {}
  50
  51   /// See MCDisassembler.
  52   DecodeStatus getInstruction(MCInst &instr,
  53                               uint64_t &size,
  54                               const MemoryObject &region,
  55                               uint64_t address,
  56                               raw_ostream &vStream,
  57                               raw_ostream &cStream) const;
  58
  59   const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
  60 };
  61
  62 }
  63
  64 // Forward-declarations used in the auto-generated files.
  65 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  66                                          uint64_t Address, const void *Decoder);
  67 static DecodeStatus
  68 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  69                             uint64_t Address, const void *Decoder);
  70
  71 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  72                                          uint64_t Address, const void *Decoder);
  73 static DecodeStatus
  74 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  75                             uint64_t Address, const void *Decoder);
  76
  77 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  78                                          uint64_t Address, const void *Decoder);
  79 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  80                                          uint64_t Address, const void *Decoder);
  81 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  82                                          uint64_t Address, const void *Decoder);
  83 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
  84                                          uint64_t Address, const void *Decoder);
  85 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
  86                                               unsigned RegNo, uint64_t Address,
  87                                               const void *Decoder);
  88 static DecodeStatus DecodeVPR128RegisterClass(llvm::MCInst &Inst,
  89                                               unsigned RegNo, uint64_t Address,
  90                                               const void *Decoder);
  91
  92 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
  93                                                unsigned OptionHiS,
  94                                                uint64_t Address,
  95                                                const void *Decoder);
  96
  97
  98 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
  99                                                unsigned Imm6Bits,
 100                                                uint64_t Address,
 101                                                const void *Decoder);
 102
 103 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
 104                                                unsigned Imm6Bits,
 105                                                uint64_t Address,
 106                                                const void *Decoder);
 107
 108 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
 109                                         unsigned RmBits,
 110                                         uint64_t Address,
 111                                         const void *Decoder);
 112
 113 template<int RegWidth>
 114 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
 115                                              unsigned FullImm,
 116                                              uint64_t Address,
 117                                              const void *Decoder);
 118
 119 template<int RegWidth>
 120 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
 121                                             unsigned Bits,
 122                                             uint64_t Address,
 123                                             const void *Decoder);
 124
 125 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
 126                                            unsigned ShiftAmount,
 127                                            uint64_t Address,
 128                                            const void *Decoder);
 129
 130 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
 131                                             unsigned ShiftAmount,
 132                                             uint64_t Address,
 133                                             const void *Decoder);
 134 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
 135                                               uint64_t Address,
 136                                               const void *Decoder);
 137
 138 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 139                                               uint64_t Address,
 140                                               const void *Decoder);
 141
 142 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
 143                                               unsigned Insn,
 144                                               uint64_t Address,
 145                                               const void *Decoder);
 146
 147 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
 148                                                        unsigned Val,
 149                                                        uint64_t Address,
 150                                                        const void *Decoder);
 151
 152 template<typename SomeNamedImmMapper>
 153 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
 154                                           unsigned Val,
 155                                           uint64_t Address,
 156                                           const void *Decoder);
 157
 158 static DecodeStatus
 159 DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper,
 160                     llvm::MCInst &Inst, unsigned Val,
 161                     uint64_t Address, const void *Decoder);
 162
 163 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
 164                                      unsigned Val,
 165                                      uint64_t Address,
 166                                      const void *Decoder);
 167
 168 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
 169                                      unsigned Val,
 170                                      uint64_t Address,
 171                                      const void *Decoder);
 172
 173
 174 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
 175                                                    unsigned Val,
 176                                                    uint64_t Address,
 177                                                    const void *Decoder);
 178
 179
 180 static bool Check(DecodeStatus &Out, DecodeStatus In);
 181
 182 #include "AArch64GenDisassemblerTables.inc"
 183 #include "AArch64GenInstrInfo.inc"
 184
 185 static bool Check(DecodeStatus &Out, DecodeStatus In) {
 186   switch (In) {
 187     case MCDisassembler::Success:
 188       // Out stays the same.
 189       return true;
 190     case MCDisassembler::SoftFail:
 191       Out = In;
 192       return true;
 193     case MCDisassembler::Fail:
 194       Out = In;
 195       return false;
 196   }
 197   llvm_unreachable("Invalid DecodeStatus!");
 198 }
 199
 200 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
 201                                                  const MemoryObject &Region,
 202                                                  uint64_t Address,
 203                                                  raw_ostream &os,
 204                                                  raw_ostream &cs) const {
 205   CommentStream = &cs;
 206
 207   uint8_t bytes[4];
 208
 209   // We want to read exactly 4 bytes of data.
 210   if (Region.readBytes(Address, 4, bytes) == -1) {
 211     Size = 0;
 212     return MCDisassembler::Fail;
 213   }
 214
 215   // Encoded as a small-endian 32-bit word in the stream.
 216   uint32_t insn = (bytes[3] << 24) |
 217     (bytes[2] << 16) |
 218     (bytes[1] <<  8) |
 219     (bytes[0] <<  0);
 220
 221   // Calling the auto-generated decoder function.
 222   DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address,
 223                                           this, STI);
 224   if (result != MCDisassembler::Fail) {
 225     Size = 4;
 226     return result;
 227   }
 228
 229   MI.clear();
 230   Size = 0;
 231   return MCDisassembler::Fail;
 232 }
 233
 234 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 235   const AArch64Disassembler *Dis = static_cast<const AArch64Disassembler*>(D);
 236   return Dis->getRegInfo()->getRegClass(RC).getRegister(RegNo);
 237 }
 238
 239 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 240                                         uint64_t Address, const void *Decoder) {
 241   if (RegNo > 31)
 242     return MCDisassembler::Fail;
 243
 244   uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo);
 245   Inst.addOperand(MCOperand::CreateReg(Register));
 246   return MCDisassembler::Success;
 247 }
 248
 249 static DecodeStatus
 250 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 251                             uint64_t Address, const void *Decoder) {
 252   if (RegNo > 31)
 253     return MCDisassembler::Fail;
 254
 255   uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo);
 256   Inst.addOperand(MCOperand::CreateReg(Register));
 257   return MCDisassembler::Success;
 258 }
 259
 260 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 261                                              uint64_t Address,
 262                                              const void *Decoder) {
 263   if (RegNo > 31)
 264     return MCDisassembler::Fail;
 265
 266   uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo);
 267   Inst.addOperand(MCOperand::CreateReg(Register));
 268   return MCDisassembler::Success;
 269 }
 270
 271 static DecodeStatus
 272 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 273                             uint64_t Address, const void *Decoder) {
 274   if (RegNo > 31)
 275     return MCDisassembler::Fail;
 276
 277   uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo);
 278   Inst.addOperand(MCOperand::CreateReg(Register));
 279   return MCDisassembler::Success;
 280 }
 281
 282 static DecodeStatus
 283 DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 284                             uint64_t Address, const void *Decoder) {
 285   if (RegNo > 31)
 286     return MCDisassembler::Fail;
 287
 288   uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo);
 289   Inst.addOperand(MCOperand::CreateReg(Register));
 290   return MCDisassembler::Success;
 291 }
 292
 293 static DecodeStatus
 294 DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 295                             uint64_t Address, const void *Decoder) {
 296   if (RegNo > 31)
 297     return MCDisassembler::Fail;
 298
 299   uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo);
 300   Inst.addOperand(MCOperand::CreateReg(Register));
 301   return MCDisassembler::Success;
 302 }
 303
 304
 305 static DecodeStatus
 306 DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 307                             uint64_t Address, const void *Decoder) {
 308   if (RegNo > 31)
 309     return MCDisassembler::Fail;
 310
 311   uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo);
 312   Inst.addOperand(MCOperand::CreateReg(Register));
 313   return MCDisassembler::Success;
 314 }
 315
 316 static DecodeStatus
 317 DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 318                             uint64_t Address, const void *Decoder) {
 319   if (RegNo > 31)
 320     return MCDisassembler::Fail;
 321
 322   uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo);
 323   Inst.addOperand(MCOperand::CreateReg(Register));
 324   return MCDisassembler::Success;
 325 }
 326
 327
 328 static DecodeStatus
 329 DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 330                             uint64_t Address, const void *Decoder) {
 331   if (RegNo > 31)
 332     return MCDisassembler::Fail;
 333
 334   uint16_t Register = getReg(Decoder, AArch64::FPR128RegClassID, RegNo);
 335   Inst.addOperand(MCOperand::CreateReg(Register));
 336   return MCDisassembler::Success;
 337 }
 338
 339 static DecodeStatus
 340 DecodeVPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
 341                          uint64_t Address, const void *Decoder) {
 342   if (RegNo > 31)
 343     return MCDisassembler::Fail;
 344
 345   uint16_t Register = getReg(Decoder, AArch64::VPR128RegClassID, RegNo);
 346   Inst.addOperand(MCOperand::CreateReg(Register));
 347   return MCDisassembler::Success;
 348 }
 349
 350 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
 351                                                unsigned OptionHiS,
 352                                                uint64_t Address,
 353                                                const void *Decoder) {
 354   // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1},
 355   // S}. Hence we want to check bit 1.
 356   if (!(OptionHiS & 2))
 357     return MCDisassembler::Fail;
 358
 359   Inst.addOperand(MCOperand::CreateImm(OptionHiS));
 360   return MCDisassembler::Success;
 361 }
 362
 363 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
 364                                                unsigned Imm6Bits,
 365                                                uint64_t Address,
 366                                                const void *Decoder) {
 367   // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be
 368   // between 0 and 31.
 369   if (Imm6Bits > 31)
 370     return MCDisassembler::Fail;
 371
 372   Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
 373   return MCDisassembler::Success;
 374 }
 375
 376 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
 377                                                unsigned Imm6Bits,
 378                                                uint64_t Address,
 379                                                const void *Decoder) {
 380   // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32.
 381   if (Imm6Bits < 32)
 382     return MCDisassembler::Fail;
 383
 384   Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
 385   return MCDisassembler::Success;
 386 }
 387
 388 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
 389                                         unsigned RmBits,
 390                                         uint64_t Address,
 391                                         const void *Decoder) {
 392   // Any bits are valid in the instruction (they're architecturally ignored),
 393   // but a code generator should insert 0.
 394   Inst.addOperand(MCOperand::CreateImm(0));
 395   return MCDisassembler::Success;
 396 }
 397
 398
 399
 400 template<int RegWidth>
 401 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
 402                                              unsigned FullImm,
 403                                              uint64_t Address,
 404                                              const void *Decoder) {
 405   unsigned Imm16 = FullImm & 0xffff;
 406   unsigned Shift = FullImm >> 16;
 407
 408   if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail;
 409
 410   Inst.addOperand(MCOperand::CreateImm(Imm16));
 411   Inst.addOperand(MCOperand::CreateImm(Shift));
 412   return MCDisassembler::Success;
 413 }
 414
 415 template<int RegWidth>
 416 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
 417                                             unsigned Bits,
 418                                             uint64_t Address,
 419                                             const void *Decoder) {
 420   uint64_t Imm;
 421   if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm))
 422     return MCDisassembler::Fail;
 423
 424   Inst.addOperand(MCOperand::CreateImm(Bits));
 425   return MCDisassembler::Success;
 426 }
 427
 428
 429 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
 430                                            unsigned ShiftAmount,
 431                                            uint64_t Address,
 432                                            const void *Decoder) {
 433   // Only values 0-4 are valid for this 3-bit field
 434   if (ShiftAmount > 4)
 435     return MCDisassembler::Fail;
 436
 437   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 438   return MCDisassembler::Success;
 439 }
 440
 441 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
 442                                             unsigned ShiftAmount,
 443                                             uint64_t Address,
 444                                             const void *Decoder) {
 445   // Only values below 32 are valid for a 32-bit register
 446   if (ShiftAmount > 31)
 447     return MCDisassembler::Fail;
 448
 449   Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
 450   return MCDisassembler::Success;
 451 }
 452
 453 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
 454                                               uint64_t Address,
 455                                               const void *Decoder) {
 456   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 457   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 458   unsigned ImmS = fieldFromInstruction(Insn, 10, 6);
 459   unsigned ImmR = fieldFromInstruction(Insn, 16, 6);
 460   unsigned SF = fieldFromInstruction(Insn, 31, 1);
 461
 462   // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise
 463   // out assertions that it thinks should never be hit.
 464   enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc;
 465   Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2);
 466
 467   if (!SF) {
 468     // ImmR and ImmS must be between 0 and 31 for 32-bit instructions.
 469     if (ImmR > 31 || ImmS > 31)
 470       return MCDisassembler::Fail;
 471   }
 472
 473   if (SF) {
 474     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 475     // BFM MCInsts use Rd as a source too.
 476     if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 477     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 478   } else {
 479     DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
 480     // BFM MCInsts use Rd as a source too.
 481     if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
 482     DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
 483   }
 484
 485   // ASR and LSR have more specific patterns so they won't get here:
 486   assert(!(ImmS == 31 && !SF && Opc != BFM)
 487          && "shift should have used auto decode");
 488   assert(!(ImmS == 63 && SF && Opc != BFM)
 489          && "shift should have used auto decode");
 490
 491   // Extension instructions similarly:
 492   if (Opc == SBFM && ImmR == 0) {
 493     assert((ImmS != 7 && ImmS != 15) && "extension got here");
 494     assert((ImmS != 31 || SF == 0) && "extension got here");
 495   } else if (Opc == UBFM && ImmR == 0) {
 496     assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here");
 497   }
 498
 499   if (Opc == UBFM) {
 500     // It might be a LSL instruction, which actually takes the shift amount
 501     // itself as an MCInst operand.
 502     if (SF && (ImmS + 1) % 64 == ImmR) {
 503       Inst.setOpcode(AArch64::LSLxxi);
 504       Inst.addOperand(MCOperand::CreateImm(63 - ImmS));
 505       return MCDisassembler::Success;
 506     } else if (!SF && (ImmS + 1) % 32 == ImmR) {
 507       Inst.setOpcode(AArch64::LSLwwi);
 508       Inst.addOperand(MCOperand::CreateImm(31 - ImmS));
 509       return MCDisassembler::Success;
 510     }
 511   }
 512
 513   // Otherwise it's definitely either an extract or an insert depending on which
 514   // of ImmR or ImmS is larger.
 515   unsigned ExtractOp, InsertOp;
 516   switch (Opc) {
 517   default: llvm_unreachable("unexpected instruction trying to decode bitfield");
 518   case SBFM:
 519     ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii;
 520     InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii;
 521     break;
 522   case BFM:
 523     ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii;
 524     InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii;
 525     break;
 526   case UBFM:
 527     ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii;
 528     InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii;
 529     break;
 530   }
 531
 532   // Otherwise it's a boring insert or extract
 533   Inst.addOperand(MCOperand::CreateImm(ImmR));
 534   Inst.addOperand(MCOperand::CreateImm(ImmS));
 535
 536
 537   if (ImmS < ImmR)
 538     Inst.setOpcode(InsertOp);
 539   else
 540     Inst.setOpcode(ExtractOp);
 541
 542   return MCDisassembler::Success;
 543 }
 544
 545 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
 546                                               uint64_t Address,
 547                                               const void *Decoder) {
 548   // This decoder exists to add the dummy Lane operand to the MCInst, which must
 549   // be 1 in assembly but has no other real manifestation.
 550   unsigned Rd = fieldFromInstruction(Insn, 0, 5);
 551   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 552   unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
 553
 554   if (IsToVec) {
 555     DecodeVPR128RegisterClass(Inst, Rd, Address, Decoder);
 556     DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
 557   } else {
 558     DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
 559     DecodeVPR128RegisterClass(Inst, Rn, Address, Decoder);
 560   }
 561
 562   // Add the lane
 563   Inst.addOperand(MCOperand::CreateImm(1));
 564
 565   return MCDisassembler::Success;
 566 }
 567
 568
 569 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
 570                                               unsigned Insn,
 571                                               uint64_t Address,
 572                                               const void *Decoder) {
 573   DecodeStatus Result = MCDisassembler::Success;
 574   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
 575   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 576   unsigned Rt2 = fieldFromInstruction(Insn, 10, 5);
 577   unsigned SImm7 = fieldFromInstruction(Insn, 15, 7);
 578   unsigned L = fieldFromInstruction(Insn, 22, 1);
 579   unsigned V = fieldFromInstruction(Insn, 26, 1);
 580   unsigned Opc = fieldFromInstruction(Insn, 30, 2);
 581
 582   // Not an official name, but it turns out that bit 23 distinguishes indexed
 583   // from non-indexed operations.
 584   unsigned Indexed = fieldFromInstruction(Insn, 23, 1);
 585
 586   if (Indexed && L == 0) {
 587     // The MCInst for an indexed store has an out operand and 4 ins:
 588     //    Rn_wb, Rt, Rt2, Rn, Imm
 589     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 590   }
 591
 592   // You shouldn't load to the same register twice in an instruction...
 593   if (L && Rt == Rt2)
 594     Result = MCDisassembler::SoftFail;
 595
 596   // ... or do any operation that writes-back to a transfer register. But note
 597   // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
 598   if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn))
 599     Result = MCDisassembler::SoftFail;
 600
 601   // Exactly how we decode the MCInst's registers depends on the Opc and V
 602   // fields of the instruction. These also obviously determine the size of the
 603   // operation so we can fill in that information while we're at it.
 604   if (V) {
 605     // The instruction operates on the FP/SIMD registers
 606     switch (Opc) {
 607     default: return MCDisassembler::Fail;
 608     case 0:
 609       DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
 610       DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder);
 611       break;
 612     case 1:
 613       DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
 614       DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder);
 615       break;
 616     case 2:
 617       DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
 618       DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder);
 619       break;
 620     }
 621   } else {
 622     switch (Opc) {
 623     default: return MCDisassembler::Fail;
 624     case 0:
 625       DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
 626       DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder);
 627       break;
 628     case 1:
 629       assert(L && "unexpected \"store signed\" attempt");
 630       DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 631       DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
 632       break;
 633     case 2:
 634       DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 635       DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
 636       break;
 637     }
 638   }
 639
 640   if (Indexed && L == 1) {
 641     // The MCInst for an indexed load has 3 out operands and an 3 ins:
 642     //    Rt, Rt2, Rn_wb, Rt2, Rn, Imm
 643     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 644   }
 645
 646
 647   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 648   Inst.addOperand(MCOperand::CreateImm(SImm7));
 649
 650   return Result;
 651 }
 652
 653 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
 654                                                        uint32_t Val,
 655                                                        uint64_t Address,
 656                                                        const void *Decoder) {
 657   unsigned Rt = fieldFromInstruction(Val, 0, 5);
 658   unsigned Rn = fieldFromInstruction(Val, 5, 5);
 659   unsigned Rt2 = fieldFromInstruction(Val, 10, 5);
 660   unsigned MemSize = fieldFromInstruction(Val, 30, 2);
 661
 662   DecodeStatus S = MCDisassembler::Success;
 663   if (Rt == Rt2) S = MCDisassembler::SoftFail;
 664
 665   switch (MemSize) {
 666     case 2:
 667       if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder)))
 668         return MCDisassembler::Fail;
 669       if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder)))
 670         return MCDisassembler::Fail;
 671       break;
 672     case 3:
 673       if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder)))
 674         return MCDisassembler::Fail;
 675       if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder)))
 676         return MCDisassembler::Fail;
 677       break;
 678     default:
 679       llvm_unreachable("Invalid MemSize in DecodeLoadPairExclusiveInstruction");
 680   }
 681
 682   if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder)))
 683     return MCDisassembler::Fail;
 684
 685   return S;
 686 }
 687
 688 template<typename SomeNamedImmMapper>
 689 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
 690                                           unsigned Val,
 691                                           uint64_t Address,
 692                                           const void *Decoder) {
 693   SomeNamedImmMapper Mapper;
 694   bool ValidNamed;
 695   Mapper.toString(Val, ValidNamed);
 696   if (ValidNamed || Mapper.validImm(Val)) {
 697     Inst.addOperand(MCOperand::CreateImm(Val));
 698     return MCDisassembler::Success;
 699   }
 700
 701   return MCDisassembler::Fail;
 702 }
 703
 704 static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
 705                                         llvm::MCInst &Inst,
 706                                         unsigned Val,
 707                                         uint64_t Address,
 708                                         const void *Decoder) {
 709   bool ValidNamed;
 710   Mapper.toString(Val, ValidNamed);
 711
 712   Inst.addOperand(MCOperand::CreateImm(Val));
 713
 714   return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail;
 715 }
 716
 717 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
 718                                      unsigned Val,
 719                                      uint64_t Address,
 720                                      const void *Decoder) {
 721   return DecodeSysRegOperand(A64SysReg::MRSMapper(), Inst, Val, Address,
 722                              Decoder);
 723 }
 724
 725 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
 726                                      unsigned Val,
 727                                      uint64_t Address,
 728                                      const void *Decoder) {
 729   return DecodeSysRegOperand(A64SysReg::MSRMapper(), Inst, Val, Address,
 730                              Decoder);
 731 }
 732
 733 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
 734                                                    unsigned Insn,
 735                                                    uint64_t Address,
 736                                                    const void *Decoder) {
 737   unsigned Rt = fieldFromInstruction(Insn, 0, 5);
 738   unsigned Rn = fieldFromInstruction(Insn, 5, 5);
 739   unsigned Imm9 = fieldFromInstruction(Insn, 12, 9);
 740
 741   unsigned Opc = fieldFromInstruction(Insn, 22, 2);
 742   unsigned V = fieldFromInstruction(Insn, 26, 1);
 743   unsigned Size = fieldFromInstruction(Insn, 30, 2);
 744
 745   if (Opc == 0 || (V == 1 && Opc == 2)) {
 746     // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm
 747     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 748   }
 749
 750   if (V == 0 && (Opc == 2 || Size == 3)) {
 751     DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
 752   } else if (V == 0) {
 753     DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
 754   } else if (V == 1 && (Opc & 2)) {
 755     DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
 756   } else {
 757     switch (Size) {
 758     case 0:
 759       DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder);
 760       break;
 761     case 1:
 762       DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder);
 763       break;
 764     case 2:
 765       DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
 766       break;
 767     case 3:
 768       DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
 769       break;
 770     }
 771   }
 772
 773   if (Opc != 0 && (V != 1 || Opc != 2)) {
 774     // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm
 775     DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 776   }
 777
 778   DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
 779
 780   Inst.addOperand(MCOperand::CreateImm(Imm9));
 781
 782   // N.b. The official documentation says undpredictable if Rt == Rn, but this
 783   // takes place at the architectural rather than encoding level:
 784   //
 785   // "STR xzr, [sp], #4" is perfectly valid.
 786   if (V == 0 && Rt == Rn && Rn != 31)
 787     return MCDisassembler::SoftFail;
 788   else
 789     return MCDisassembler::Success;
 790 }
 791
 792 static MCDisassembler *createAArch64Disassembler(const Target &T,
 793                                                  const MCSubtargetInfo &STI) {
 794   return new AArch64Disassembler(STI, T.createMCRegInfo(""));
 795 }
 796
 797 extern "C" void LLVMInitializeAArch64Disassembler() {
 798   TargetRegistry::RegisterMCDisassembler(TheAArch64Target,
 799                                          createAArch64Disassembler);
 800 }
 801
 802