1 //===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an AArch64 MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_AARCH64INSTPRINTER_H
15 #define LLVM_AARCH64INSTPRINTER_H
17 #include "MCTargetDesc/AArch64MCTargetDesc.h"
18 #include "Utils/AArch64BaseInfo.h"
19 #include "llvm/MC/MCInstPrinter.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
26 class AArch64InstPrinter : public MCInstPrinter {
28 AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
29 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
31 // Autogenerated by tblgen
32 void printInstruction(const MCInst *MI, raw_ostream &O);
33 bool printAliasInstr(const MCInst *MI, raw_ostream &O);
34 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
35 unsigned PrintMethodIdx, raw_ostream &O);
36 static const char *getRegisterName(unsigned RegNo);
37 static const char *getInstructionName(unsigned Opcode);
39 void printRegName(raw_ostream &O, unsigned RegNum) const override;
41 template<unsigned MemSize, unsigned RmSize>
42 void printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum,
44 printAddrRegExtendOperand(MI, OpNum, O, MemSize, RmSize);
48 void printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum,
49 raw_ostream &O, unsigned MemSize,
52 void printAddSubImmLSL0Operand(const MCInst *MI,
53 unsigned OpNum, raw_ostream &O);
54 void printAddSubImmLSL12Operand(const MCInst *MI,
55 unsigned OpNum, raw_ostream &O);
57 void printBareImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
59 template<unsigned RegWidth>
60 void printBFILSBOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
61 void printBFIWidthOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
62 void printBFXWidthOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
65 void printCondCodeOperand(const MCInst *MI, unsigned OpNum,
67 void printInverseCondCodeOperand(const MCInst *MI, unsigned OpNum,
70 void printCRxOperand(const MCInst *MI, unsigned OpNum,
73 void printCVTFixedPosOperand(const MCInst *MI, unsigned OpNum,
76 void printFPImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &o);
78 void printFPZeroOperand(const MCInst *MI, unsigned OpNum, raw_ostream &o);
80 template<int MemScale>
81 void printOffsetUImm12Operand(const MCInst *MI,
82 unsigned OpNum, raw_ostream &o) {
83 printOffsetUImm12Operand(MI, OpNum, o, MemScale);
86 void printOffsetUImm12Operand(const MCInst *MI, unsigned OpNum,
87 raw_ostream &o, int MemScale);
89 template<unsigned field_width, unsigned scale>
90 void printLabelOperand(const MCInst *MI, unsigned OpNum,
93 template<unsigned RegWidth>
94 void printLogicalImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
96 template<typename SomeNamedImmMapper>
97 void printNamedImmOperand(const MCInst *MI, unsigned OpNum,
99 printNamedImmOperand(SomeNamedImmMapper(), MI, OpNum, O);
102 void printNamedImmOperand(const NamedImmMapper &Mapper,
103 const MCInst *MI, unsigned OpNum,
106 void printSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
107 const MCInst *MI, unsigned OpNum,
110 void printMRSOperand(const MCInst *MI, unsigned OpNum,
112 printSysRegOperand(A64SysReg::MRSMapper(), MI, OpNum, O);
115 void printMSROperand(const MCInst *MI, unsigned OpNum,
117 printSysRegOperand(A64SysReg::MSRMapper(), MI, OpNum, O);
120 void printShiftOperand(const char *name, const MCInst *MI,
121 unsigned OpIdx, raw_ostream &O);
123 void printLSLOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
125 void printLSROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
126 printShiftOperand("lsr", MI, OpNum, O);
128 void printASROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
129 printShiftOperand("asr", MI, OpNum, O);
131 void printROROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
132 printShiftOperand("ror", MI, OpNum, O);
135 template<A64SE::ShiftExtSpecifiers Shift>
136 void printShiftOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
137 printShiftOperand(MI, OpNum, O, Shift);
140 void printShiftOperand(const MCInst *MI, unsigned OpNum,
141 raw_ostream &O, A64SE::ShiftExtSpecifiers Sh);
144 void printMoveWideImmOperand(const MCInst *MI, unsigned OpNum,
147 template<int MemSize> void
148 printSImm7ScaledOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
150 void printOffsetSImm9Operand(const MCInst *MI, unsigned OpNum,
153 void printPRFMOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
155 template<A64SE::ShiftExtSpecifiers EXT>
156 void printRegExtendOperand(const MCInst *MI, unsigned OpNum,
158 printRegExtendOperand(MI, OpNum, O, EXT);
161 void printRegExtendOperand(const MCInst *MI, unsigned OpNum,
162 raw_ostream &O, A64SE::ShiftExtSpecifiers Ext);
164 void printVPRRegister(const MCInst *MI, unsigned OpNo, raw_ostream &O);
165 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
166 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
168 bool isStackReg(unsigned RegNo) {
169 return RegNo == AArch64::XSP || RegNo == AArch64::WSP;
172 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
173 void printNeonMovImmShiftOperand(const MCInst *MI, unsigned OpNum,
175 void printNeonUImm0Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
176 void printUImmHexOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
177 void printUImmBareOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
178 void printNeonUImm64MaskOperand(const MCInst *MI, unsigned OpNum,
181 template <A64Layout::VectorLayout Layout, unsigned Count>
182 void printVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O);