1 //===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an AArch64 MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_AARCH64INSTPRINTER_H
15 #define LLVM_AARCH64INSTPRINTER_H
17 #include "MCTargetDesc/AArch64MCTargetDesc.h"
18 #include "Utils/AArch64BaseInfo.h"
19 #include "llvm/MC/MCInstPrinter.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
26 class AArch64InstPrinter : public MCInstPrinter {
28 AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
29 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
31 // Autogenerated by tblgen
32 void printInstruction(const MCInst *MI, raw_ostream &O);
33 bool printAliasInstr(const MCInst *MI, raw_ostream &O);
34 static const char *getRegisterName(unsigned RegNo);
35 static const char *getInstructionName(unsigned Opcode);
37 void printRegName(raw_ostream &O, unsigned RegNum) const;
39 template<unsigned MemSize, unsigned RmSize>
40 void printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum,
42 printAddrRegExtendOperand(MI, OpNum, O, MemSize, RmSize);
46 void printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum,
47 raw_ostream &O, unsigned MemSize,
50 void printAddSubImmLSL0Operand(const MCInst *MI,
51 unsigned OpNum, raw_ostream &O);
52 void printAddSubImmLSL12Operand(const MCInst *MI,
53 unsigned OpNum, raw_ostream &O);
55 void printBareImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
57 template<unsigned RegWidth>
58 void printBFILSBOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
59 void printBFIWidthOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
60 void printBFXWidthOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
63 void printCondCodeOperand(const MCInst *MI, unsigned OpNum,
66 void printCRxOperand(const MCInst *MI, unsigned OpNum,
69 void printCVTFixedPosOperand(const MCInst *MI, unsigned OpNum,
72 void printFPImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &o);
74 void printFPZeroOperand(const MCInst *MI, unsigned OpNum, raw_ostream &o);
76 template<int MemScale>
77 void printOffsetUImm12Operand(const MCInst *MI,
78 unsigned OpNum, raw_ostream &o) {
79 printOffsetUImm12Operand(MI, OpNum, o, MemScale);
82 void printOffsetUImm12Operand(const MCInst *MI, unsigned OpNum,
83 raw_ostream &o, int MemScale);
85 template<unsigned field_width, unsigned scale>
86 void printLabelOperand(const MCInst *MI, unsigned OpNum,
89 template<unsigned RegWidth>
90 void printLogicalImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
92 template<typename SomeNamedImmMapper>
93 void printNamedImmOperand(const MCInst *MI, unsigned OpNum,
95 printNamedImmOperand(SomeNamedImmMapper(), MI, OpNum, O);
98 void printNamedImmOperand(const NamedImmMapper &Mapper,
99 const MCInst *MI, unsigned OpNum,
102 void printSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
103 const MCInst *MI, unsigned OpNum,
106 void printMRSOperand(const MCInst *MI, unsigned OpNum,
108 printSysRegOperand(A64SysReg::MRSMapper(), MI, OpNum, O);
111 void printMSROperand(const MCInst *MI, unsigned OpNum,
113 printSysRegOperand(A64SysReg::MSRMapper(), MI, OpNum, O);
116 void printShiftOperand(const char *name, const MCInst *MI,
117 unsigned OpIdx, raw_ostream &O);
119 void printLSLOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
121 void printLSROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
122 printShiftOperand("lsr", MI, OpNum, O);
124 void printASROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
125 printShiftOperand("asr", MI, OpNum, O);
127 void printROROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
128 printShiftOperand("ror", MI, OpNum, O);
131 template<A64SE::ShiftExtSpecifiers Shift>
132 void printShiftOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
133 printShiftOperand(MI, OpNum, O, Shift);
136 void printShiftOperand(const MCInst *MI, unsigned OpNum,
137 raw_ostream &O, A64SE::ShiftExtSpecifiers Sh);
140 void printMoveWideImmOperand(const MCInst *MI, unsigned OpNum,
143 template<int MemSize> void
144 printSImm7ScaledOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
146 void printOffsetSImm9Operand(const MCInst *MI, unsigned OpNum,
149 void printPRFMOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
151 template<A64SE::ShiftExtSpecifiers EXT>
152 void printRegExtendOperand(const MCInst *MI, unsigned OpNum,
154 printRegExtendOperand(MI, OpNum, O, EXT);
157 void printRegExtendOperand(const MCInst *MI, unsigned OpNum,
158 raw_ostream &O, A64SE::ShiftExtSpecifiers Ext);
160 void printVPRRegister(const MCInst *MI, unsigned OpNo, raw_ostream &O);
161 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
162 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
164 bool isStackReg(unsigned RegNo) {
165 return RegNo == AArch64::XSP || RegNo == AArch64::WSP;
168 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
169 void printNeonMovImmShiftOperand(const MCInst *MI, unsigned OpNum,
171 void printNeonUImm0Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
172 void printUImmHexOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
173 void printUImmBareOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
174 void printNeonUImm64MaskOperand(const MCInst *MI, unsigned OpNum,
177 template <A64Layout::VectorLayout Layout, unsigned Count>
178 void printVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O);