1 //===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an AArch64 MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_AARCH64INSTPRINTER_H
15 #define LLVM_AARCH64INSTPRINTER_H
17 #include "MCTargetDesc/AArch64BaseInfo.h"
18 #include "llvm/MC/MCInstPrinter.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
25 class AArch64InstPrinter : public MCInstPrinter {
27 AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
28 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
30 // Autogenerated by tblgen
31 void printInstruction(const MCInst *MI, raw_ostream &O);
32 bool printAliasInstr(const MCInst *MI, raw_ostream &O);
33 static const char *getRegisterName(unsigned RegNo);
34 static const char *getInstructionName(unsigned Opcode);
36 void printRegName(raw_ostream &O, unsigned RegNum) const;
38 template<unsigned MemSize, unsigned RmSize>
39 void printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum,
41 printAddrRegExtendOperand(MI, OpNum, O, MemSize, RmSize);
45 void printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum,
46 raw_ostream &O, unsigned MemSize,
49 void printAddSubImmLSL0Operand(const MCInst *MI,
50 unsigned OpNum, raw_ostream &O);
51 void printAddSubImmLSL12Operand(const MCInst *MI,
52 unsigned OpNum, raw_ostream &O);
54 void printBareImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
56 template<unsigned RegWidth>
57 void printBFILSBOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
58 void printBFIWidthOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
59 void printBFXWidthOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
62 void printCondCodeOperand(const MCInst *MI, unsigned OpNum,
65 void printCRxOperand(const MCInst *MI, unsigned OpNum,
68 void printCVTFixedPosOperand(const MCInst *MI, unsigned OpNum,
71 void printFPImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &o);
73 void printFPZeroOperand(const MCInst *MI, unsigned OpNum, raw_ostream &o);
75 template<int MemScale>
76 void printOffsetUImm12Operand(const MCInst *MI,
77 unsigned OpNum, raw_ostream &o) {
78 printOffsetUImm12Operand(MI, OpNum, o, MemScale);
81 void printOffsetUImm12Operand(const MCInst *MI, unsigned OpNum,
82 raw_ostream &o, int MemScale);
84 template<unsigned field_width, unsigned scale>
85 void printLabelOperand(const MCInst *MI, unsigned OpNum,
88 template<unsigned RegWidth>
89 void printLogicalImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
91 template<typename SomeNamedImmMapper>
92 void printNamedImmOperand(const MCInst *MI, unsigned OpNum,
94 printNamedImmOperand(SomeNamedImmMapper(), MI, OpNum, O);
97 void printNamedImmOperand(const NamedImmMapper &Mapper,
98 const MCInst *MI, unsigned OpNum,
101 void printSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
102 const MCInst *MI, unsigned OpNum,
105 void printMRSOperand(const MCInst *MI, unsigned OpNum,
107 printSysRegOperand(A64SysReg::MRSMapper(), MI, OpNum, O);
110 void printMSROperand(const MCInst *MI, unsigned OpNum,
112 printSysRegOperand(A64SysReg::MSRMapper(), MI, OpNum, O);
115 void printShiftOperand(const char *name, const MCInst *MI,
116 unsigned OpIdx, raw_ostream &O);
118 void printLSLOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
120 void printLSROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
121 printShiftOperand("lsr", MI, OpNum, O);
123 void printASROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
124 printShiftOperand("asr", MI, OpNum, O);
126 void printROROperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
127 printShiftOperand("ror", MI, OpNum, O);
130 template<A64SE::ShiftExtSpecifiers Shift>
131 void printShiftOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
132 printShiftOperand(MI, OpNum, O, Shift);
135 void printShiftOperand(const MCInst *MI, unsigned OpNum,
136 raw_ostream &O, A64SE::ShiftExtSpecifiers Sh);
139 void printMoveWideImmOperand(const MCInst *MI, unsigned OpNum,
142 template<int MemSize> void
143 printSImm7ScaledOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
145 void printOffsetSImm9Operand(const MCInst *MI, unsigned OpNum,
148 void printPRFMOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
150 template<A64SE::ShiftExtSpecifiers EXT>
151 void printRegExtendOperand(const MCInst *MI, unsigned OpNum,
153 printRegExtendOperand(MI, OpNum, O, EXT);
156 void printRegExtendOperand(const MCInst *MI, unsigned OpNum,
157 raw_ostream &O, A64SE::ShiftExtSpecifiers Ext);
159 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
160 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
162 bool isStackReg(unsigned RegNo) {
163 return RegNo == AArch64::XSP || RegNo == AArch64::WSP;