1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides AArch64 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64MCTargetDesc.h"
15 #include "AArch64ELFStreamer.h"
16 #include "AArch64MCAsmInfo.h"
17 #include "InstPrinter/AArch64InstPrinter.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCInstrAnalysis.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Support/ErrorHandling.h"
28 #define GET_REGINFO_MC_DESC
29 #include "AArch64GenRegisterInfo.inc"
31 #define GET_INSTRINFO_MC_DESC
32 #include "AArch64GenInstrInfo.inc"
34 #define GET_SUBTARGETINFO_MC_DESC
35 #include "AArch64GenSubtargetInfo.inc"
39 MCSubtargetInfo *AArch64_MC::createAArch64MCSubtargetInfo(StringRef TT,
42 MCSubtargetInfo *X = new MCSubtargetInfo();
43 InitAArch64MCSubtargetInfo(X, TT, CPU, "");
48 static MCInstrInfo *createAArch64MCInstrInfo() {
49 MCInstrInfo *X = new MCInstrInfo();
50 InitAArch64MCInstrInfo(X);
54 static MCRegisterInfo *createAArch64MCRegisterInfo(StringRef Triple) {
55 MCRegisterInfo *X = new MCRegisterInfo();
56 InitAArch64MCRegisterInfo(X, AArch64::X30);
60 static MCAsmInfo *createAArch64MCAsmInfo(const Target &T, StringRef TT) {
63 MCAsmInfo *MAI = new AArch64ELFMCAsmInfo();
64 MachineLocation Dst(MachineLocation::VirtualFP);
65 MachineLocation Src(AArch64::XSP, 0);
66 MAI->addInitialFrameState(0, Dst, Src);
71 static MCCodeGenInfo *createAArch64MCCodeGenInfo(StringRef TT, Reloc::Model RM,
73 CodeGenOpt::Level OL) {
74 MCCodeGenInfo *X = new MCCodeGenInfo();
75 if (RM == Reloc::Default || RM == Reloc::DynamicNoPIC) {
76 // On ELF platforms the default static relocation model has a smart enough
77 // linker to cope with referencing external symbols defined in a shared
78 // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
82 if (CM == CodeModel::Default)
83 CM = CodeModel::Small;
85 X->InitMCCodeGenInfo(RM, CM, OL);
89 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
90 MCContext &Ctx, MCAsmBackend &MAB,
92 MCCodeEmitter *Emitter,
97 return createAArch64ELFStreamer(Ctx, MAB, OS, Emitter, RelaxAll, NoExecStack);
101 static MCInstPrinter *createAArch64MCInstPrinter(const Target &T,
102 unsigned SyntaxVariant,
103 const MCAsmInfo &MAI,
104 const MCInstrInfo &MII,
105 const MCRegisterInfo &MRI,
106 const MCSubtargetInfo &STI) {
107 if (SyntaxVariant == 0)
108 return new AArch64InstPrinter(MAI, MII, MRI, STI);
114 class AArch64MCInstrAnalysis : public MCInstrAnalysis {
116 AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
118 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
119 if (Inst.getOpcode() == AArch64::Bcc
120 && Inst.getOperand(0).getImm() == A64CC::AL)
122 return MCInstrAnalysis::isUnconditionalBranch(Inst);
125 virtual bool isConditionalBranch(const MCInst &Inst) const {
126 if (Inst.getOpcode() == AArch64::Bcc
127 && Inst.getOperand(0).getImm() == A64CC::AL)
129 return MCInstrAnalysis::isConditionalBranch(Inst);
132 uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr,
133 uint64_t Size) const {
134 unsigned LblOperand = Inst.getOpcode() == AArch64::Bcc ? 1 : 0;
135 // FIXME: We only handle PCRel branches for now.
136 if (Info->get(Inst.getOpcode()).OpInfo[LblOperand].OperandType
137 != MCOI::OPERAND_PCREL)
140 int64_t Imm = Inst.getOperand(LblOperand).getImm();
148 static MCInstrAnalysis *createAArch64MCInstrAnalysis(const MCInstrInfo *Info) {
149 return new AArch64MCInstrAnalysis(Info);
154 extern "C" void LLVMInitializeAArch64TargetMC() {
155 // Register the MC asm info.
156 RegisterMCAsmInfoFn A(TheAArch64Target, createAArch64MCAsmInfo);
158 // Register the MC codegen info.
159 TargetRegistry::RegisterMCCodeGenInfo(TheAArch64Target,
160 createAArch64MCCodeGenInfo);
162 // Register the MC instruction info.
163 TargetRegistry::RegisterMCInstrInfo(TheAArch64Target,
164 createAArch64MCInstrInfo);
166 // Register the MC register info.
167 TargetRegistry::RegisterMCRegInfo(TheAArch64Target,
168 createAArch64MCRegisterInfo);
170 // Register the MC subtarget info.
171 using AArch64_MC::createAArch64MCSubtargetInfo;
172 TargetRegistry::RegisterMCSubtargetInfo(TheAArch64Target,
173 createAArch64MCSubtargetInfo);
175 // Register the MC instruction analyzer.
176 TargetRegistry::RegisterMCInstrAnalysis(TheAArch64Target,
177 createAArch64MCInstrAnalysis);
179 // Register the MC Code Emitter
180 TargetRegistry::RegisterMCCodeEmitter(TheAArch64Target,
181 createAArch64MCCodeEmitter);
183 // Register the asm backend.
184 TargetRegistry::RegisterMCAsmBackend(TheAArch64Target,
185 createAArch64AsmBackend);
187 // Register the object streamer.
188 TargetRegistry::RegisterMCObjectStreamer(TheAArch64Target,
191 // Register the MCInstPrinter.
192 TargetRegistry::RegisterMCInstPrinter(TheAArch64Target,
193 createAArch64MCInstPrinter);