1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #ifndef LLVM_LIB_TARGET_R600_AMDGPU_H
12 #define LLVM_LIB_TARGET_R600_AMDGPU_H
14 #include "llvm/Support/TargetRegistry.h"
15 #include "llvm/Target/TargetMachine.h"
19 class AMDGPUInstrPrinter;
20 class AMDGPUSubtarget;
21 class AMDGPUTargetMachine;
23 class MachineSchedContext;
26 class ScheduleDAGInstrs;
31 FunctionPass *createR600VectorRegMerger(TargetMachine &tm);
32 FunctionPass *createR600TextureIntrinsicsReplacer();
33 FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
34 FunctionPass *createR600EmitClauseMarkers();
35 FunctionPass *createR600ClauseMergePass(TargetMachine &tm);
36 FunctionPass *createR600Packetizer(TargetMachine &tm);
37 FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm);
38 FunctionPass *createAMDGPUCFGStructurizerPass();
41 FunctionPass *createSITypeRewriter();
42 FunctionPass *createSIAnnotateControlFlowPass();
43 FunctionPass *createSIFoldOperandsPass();
44 FunctionPass *createSILowerI1CopiesPass();
45 FunctionPass *createSIShrinkInstructionsPass();
46 FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm);
47 FunctionPass *createSILowerControlFlowPass(TargetMachine &tm);
48 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
49 FunctionPass *createSIFixSGPRCopiesPass();
50 FunctionPass *createSIFixSGPRLiveRangesPass();
51 FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
52 FunctionPass *createSIInsertWaits(TargetMachine &tm);
54 ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C);
56 ModulePass *createAMDGPUAnnotateKernelFeaturesPass();
57 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
58 extern char &AMDGPUAnnotateKernelFeaturesID;
60 void initializeSIFoldOperandsPass(PassRegistry &);
61 extern char &SIFoldOperandsID;
63 void initializeSIFixSGPRCopiesPass(PassRegistry &);
64 extern char &SIFixSGPRCopiesID;
66 void initializeSILowerI1CopiesPass(PassRegistry &);
67 extern char &SILowerI1CopiesID;
69 void initializeSILoadStoreOptimizerPass(PassRegistry &);
70 extern char &SILoadStoreOptimizerID;
72 // Passes common to R600 and SI
73 FunctionPass *createAMDGPUPromoteAlloca(const AMDGPUSubtarget &ST);
74 Pass *createAMDGPUStructurizeCFGPass();
75 FunctionPass *createAMDGPUISelDag(TargetMachine &tm);
76 ModulePass *createAMDGPUAlwaysInlinePass();
77 ModulePass *createAMDGPUOpenCLImageTypeLoweringPass();
78 FunctionPass *createAMDGPUAnnotateUniformValues();
80 void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&);
81 extern char &SIFixControlFlowLiveIntervalsID;
83 void initializeSIFixSGPRLiveRangesPass(PassRegistry&);
84 extern char &SIFixSGPRLiveRangesID;
86 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
87 extern char &AMDGPUAnnotateUniformValuesPassID;
89 extern Target TheAMDGPUTarget;
90 extern Target TheGCNTarget;
95 TI_SCRATCH_RSRC_DWORD0,
96 TI_SCRATCH_RSRC_DWORD1,
97 TI_SCRATCH_RSRC_DWORD2,
98 TI_SCRATCH_RSRC_DWORD3
102 } // End namespace llvm
104 namespace ShaderType {
113 /// OpenCL uses address spaces to differentiate between
114 /// various memory regions on the hardware. On the CPU
115 /// all of the address spaces point to the same memory,
116 /// however on the GPU, each address space points to
117 /// a separate piece of memory that is unique from other
118 /// memory locations.
120 enum AddressSpaces : unsigned {
121 PRIVATE_ADDRESS = 0, ///< Address space for private memory.
122 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
123 CONSTANT_ADDRESS = 2, ///< Address space for constant memory
124 LOCAL_ADDRESS = 3, ///< Address space for local memory.
125 FLAT_ADDRESS = 4, ///< Address space for flat memory.
126 REGION_ADDRESS = 5, ///< Address space for region memory.
127 PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0)
128 PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1)
130 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this
131 // order to be able to dynamically index a constant buffer, for example:
133 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
135 CONSTANT_BUFFER_0 = 8,
136 CONSTANT_BUFFER_1 = 9,
137 CONSTANT_BUFFER_2 = 10,
138 CONSTANT_BUFFER_3 = 11,
139 CONSTANT_BUFFER_4 = 12,
140 CONSTANT_BUFFER_5 = 13,
141 CONSTANT_BUFFER_6 = 14,
142 CONSTANT_BUFFER_7 = 15,
143 CONSTANT_BUFFER_8 = 16,
144 CONSTANT_BUFFER_9 = 17,
145 CONSTANT_BUFFER_10 = 18,
146 CONSTANT_BUFFER_11 = 19,
147 CONSTANT_BUFFER_12 = 20,
148 CONSTANT_BUFFER_13 = 21,
149 CONSTANT_BUFFER_14 = 22,
150 CONSTANT_BUFFER_15 = 23,
151 ADDRESS_NONE = 24, ///< Address space for unknown memory.
152 LAST_ADDRESS = ADDRESS_NONE,
154 // Some places use this if the address space can't be determined.
155 UNKNOWN_ADDRESS_SPACE = ~0u
158 } // namespace AMDGPUAS