1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code. When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
16 //===----------------------------------------------------------------------===//
19 #include "AMDGPUAsmPrinter.h"
20 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
21 #include "InstPrinter/AMDGPUInstPrinter.h"
22 #include "Utils/AMDGPUBaseInfo.h"
24 #include "AMDKernelCodeT.h"
25 #include "AMDGPUSubtarget.h"
26 #include "R600Defines.h"
27 #include "R600MachineFunctionInfo.h"
28 #include "R600RegisterInfo.h"
29 #include "SIDefines.h"
30 #include "SIMachineFunctionInfo.h"
31 #include "SIRegisterInfo.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/MC/MCContext.h"
34 #include "llvm/MC/MCSectionELF.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/Support/ELF.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
43 // TODO: This should get the default rounding mode from the kernel. We just set
44 // the default here, but this could change if the OpenCL rounding mode pragmas
47 // The denormal mode here should match what is reported by the OpenCL runtime
48 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
49 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
51 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
52 // precision, and leaves single precision to flush all and does not report
53 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
54 // CL_FP_DENORM for both.
56 // FIXME: It seems some instructions do not support single precision denormals
57 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
58 // and sin_f32, cos_f32 on most parts).
60 // We want to use these instructions, and using fp32 denormals also causes
61 // instructions to run at the double precision rate for the device so it's
62 // probably best to just report no single precision denormals.
63 static uint32_t getFPMode(const MachineFunction &F) {
64 const AMDGPUSubtarget& ST = F.getSubtarget<AMDGPUSubtarget>();
65 // TODO: Is there any real use for the flush in only / flush out only modes?
67 uint32_t FP32Denormals =
68 ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
70 uint32_t FP64Denormals =
71 ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
73 return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
74 FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
75 FP_DENORM_MODE_SP(FP32Denormals) |
76 FP_DENORM_MODE_DP(FP64Denormals);
80 createAMDGPUAsmPrinterPass(TargetMachine &tm,
81 std::unique_ptr<MCStreamer> &&Streamer) {
82 return new AMDGPUAsmPrinter(tm, std::move(Streamer));
85 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
86 TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
87 TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass);
90 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
91 std::unique_ptr<MCStreamer> Streamer)
92 : AsmPrinter(TM, std::move(Streamer)) {}
94 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
95 const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
96 SIProgramInfo KernelInfo;
97 if (STM.isAmdHsaOS()) {
98 getSIProgramInfo(KernelInfo, *MF);
99 EmitAmdKernelCodeT(*MF, KernelInfo);
103 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
104 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
105 const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
106 if (MFI->isKernel() && STM.isAmdHsaOS()) {
107 AMDGPUTargetStreamer *TS =
108 static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
109 TS->EmitAMDGPUSymbolType(CurrentFnSym->getName(),
110 ELF::STT_AMDGPU_HSA_KERNEL);
113 AsmPrinter::EmitFunctionEntryLabel();
116 static bool isModuleLinkage(const GlobalValue *GV) {
117 switch (GV->getLinkage()) {
118 case GlobalValue::InternalLinkage:
119 case GlobalValue::CommonLinkage:
121 case GlobalValue::ExternalLinkage:
123 default: llvm_unreachable("unknown linkage type");
127 void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
129 if (TM.getTargetTriple().getOS() != Triple::AMDHSA) {
130 AsmPrinter::EmitGlobalVariable(GV);
134 if (GV->isDeclaration() || GV->getLinkage() == GlobalValue::PrivateLinkage) {
135 AsmPrinter::EmitGlobalVariable(GV);
139 // Group segment variables aren't emitted in HSA.
140 if (AMDGPU::isGroupSegment(GV))
143 AMDGPUTargetStreamer *TS =
144 static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
145 if (isModuleLinkage(GV)) {
146 TS->EmitAMDGPUHsaModuleScopeGlobal(GV->getName());
148 TS->EmitAMDGPUHsaProgramScopeGlobal(GV->getName());
151 MCSymbolELF *GVSym = cast<MCSymbolELF>(getSymbol(GV));
152 const DataLayout &DL = getDataLayout();
155 uint64_t Size = DL.getTypeAllocSize(GV->getType()->getElementType());
156 OutStreamer->emitELFSize(GVSym, MCConstantExpr::create(Size, OutContext));
157 OutStreamer->PushSection();
158 OutStreamer->SwitchSection(
159 getObjFileLowering().SectionForGlobal(GV, *Mang, TM));
160 const Constant *C = GV->getInitializer();
161 OutStreamer->EmitLabel(GVSym);
162 EmitGlobalConstant(DL, C);
163 OutStreamer->PopSection();
166 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
168 // The starting address of all shader programs must be 256 bytes aligned.
171 SetupMachineFunction(MF);
173 MCContext &Context = getObjFileLowering().getContext();
174 MCSectionELF *ConfigSection =
175 Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
176 OutStreamer->SwitchSection(ConfigSection);
178 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
179 SIProgramInfo KernelInfo;
180 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
181 getSIProgramInfo(KernelInfo, MF);
182 if (!STM.isAmdHsaOS()) {
183 EmitProgramInfoSI(MF, KernelInfo);
186 AMDGPUTargetStreamer *TS =
187 static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
188 TS->EmitDirectiveHSACodeObjectVersion(1, 0);
189 AMDGPU::IsaVersion ISA = STM.getIsaVersion();
190 TS->EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor, ISA.Stepping,
193 EmitProgramInfoR600(MF);
198 DisasmLineMaxLen = 0;
203 MCSectionELF *CommentSection =
204 Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
205 OutStreamer->SwitchSection(CommentSection);
207 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
208 OutStreamer->emitRawComment(" Kernel info:", false);
209 OutStreamer->emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
211 OutStreamer->emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
213 OutStreamer->emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
215 OutStreamer->emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
217 OutStreamer->emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
219 OutStreamer->emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
222 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:USER_SGPR: " +
223 Twine(G_00B84C_USER_SGPR(KernelInfo.ComputePGMRSrc2)),
225 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_X_EN: " +
226 Twine(G_00B84C_TGID_X_EN(KernelInfo.ComputePGMRSrc2)),
228 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
229 Twine(G_00B84C_TGID_Y_EN(KernelInfo.ComputePGMRSrc2)),
231 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
232 Twine(G_00B84C_TGID_Z_EN(KernelInfo.ComputePGMRSrc2)),
234 OutStreamer->emitRawComment(" COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
235 Twine(G_00B84C_TIDIG_COMP_CNT(KernelInfo.ComputePGMRSrc2)),
239 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
240 OutStreamer->emitRawComment(
241 Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
245 if (STM.dumpCode()) {
247 OutStreamer->SwitchSection(
248 Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
250 for (size_t i = 0; i < DisasmLines.size(); ++i) {
251 std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
252 Comment += " ; " + HexLines[i] + "\n";
254 OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
255 OutStreamer->EmitBytes(StringRef(Comment));
262 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
264 bool killPixel = false;
265 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
266 const R600RegisterInfo *RI =
267 static_cast<const R600RegisterInfo *>(STM.getRegisterInfo());
268 const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
270 for (const MachineBasicBlock &MBB : MF) {
271 for (const MachineInstr &MI : MBB) {
272 if (MI.getOpcode() == AMDGPU::KILLGT)
274 unsigned numOperands = MI.getNumOperands();
275 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
276 const MachineOperand &MO = MI.getOperand(op_idx);
279 unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
281 // Register with value > 127 aren't GPR
284 MaxGPR = std::max(MaxGPR, HWReg);
290 if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
291 // Evergreen / Northern Islands
292 switch (MFI->getShaderType()) {
293 default: // Fall through
294 case ShaderType::COMPUTE: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
295 case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
296 case ShaderType::PIXEL: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
297 case ShaderType::VERTEX: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
301 switch (MFI->getShaderType()) {
302 default: // Fall through
303 case ShaderType::GEOMETRY: // Fall through
304 case ShaderType::COMPUTE: // Fall through
305 case ShaderType::VERTEX: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
306 case ShaderType::PIXEL: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
310 OutStreamer->EmitIntValue(RsrcReg, 4);
311 OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
312 S_STACK_SIZE(MFI->StackSize), 4);
313 OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
314 OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
316 if (MFI->getShaderType() == ShaderType::COMPUTE) {
317 OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
318 OutStreamer->EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
322 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
323 const MachineFunction &MF) const {
324 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
325 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
326 uint64_t CodeSize = 0;
327 unsigned MaxSGPR = 0;
328 unsigned MaxVGPR = 0;
329 bool VCCUsed = false;
330 bool FlatUsed = false;
331 const SIRegisterInfo *RI =
332 static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
334 for (const MachineBasicBlock &MBB : MF) {
335 for (const MachineInstr &MI : MBB) {
336 // TODO: CodeSize should account for multiple functions.
338 // TODO: Should we count size of debug info?
339 if (MI.isDebugValue())
342 // FIXME: This is reporting 0 for many instructions.
343 CodeSize += MI.getDesc().Size;
345 unsigned numOperands = MI.getNumOperands();
346 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
347 const MachineOperand &MO = MI.getOperand(op_idx);
354 unsigned reg = MO.getReg();
367 case AMDGPU::FLAT_SCR:
368 case AMDGPU::FLAT_SCR_LO:
369 case AMDGPU::FLAT_SCR_HI:
377 if (AMDGPU::SReg_32RegClass.contains(reg)) {
380 } else if (AMDGPU::VGPR_32RegClass.contains(reg)) {
383 } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
386 } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
389 } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
392 } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
395 } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
398 } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
401 } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
404 } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
407 } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
411 llvm_unreachable("Unknown register class");
413 unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
414 unsigned maxUsed = hwReg + width - 1;
416 MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
418 MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
424 unsigned ExtraSGPRs = 0;
429 if (STM.getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS) {
433 if (STM.isXNACKEnabled())
440 MaxSGPR += ExtraSGPRs;
442 // We found the maximum register index. They start at 0, so add one to get the
443 // number of registers.
444 ProgInfo.NumVGPR = MaxVGPR + 1;
445 ProgInfo.NumSGPR = MaxSGPR + 1;
447 if (STM.hasSGPRInitBug()) {
448 if (ProgInfo.NumSGPR > AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG) {
449 LLVMContext &Ctx = MF.getFunction()->getContext();
450 Ctx.emitError("too many SGPRs used with the SGPR init bug");
453 ProgInfo.NumSGPR = AMDGPUSubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
456 if (MFI->NumUserSGPRs > STM.getMaxNumUserSGPRs()) {
457 LLVMContext &Ctx = MF.getFunction()->getContext();
458 Ctx.emitError("too many user SGPRs used");
461 ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
462 ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
463 // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
465 ProgInfo.FloatMode = getFPMode(MF);
467 // XXX: Not quite sure what this does, but sc seems to unset this.
468 ProgInfo.IEEEMode = 0;
470 // Do not clamp NAN to 0.
471 ProgInfo.DX10Clamp = 0;
473 const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
474 ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);
476 ProgInfo.FlatUsed = FlatUsed;
477 ProgInfo.VCCUsed = VCCUsed;
478 ProgInfo.CodeLen = CodeSize;
480 unsigned LDSAlignShift;
481 if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
482 // LDS is allocated in 64 dword blocks.
485 // LDS is allocated in 128 dword blocks.
489 unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
490 MFI->getMaximumWorkGroupSize(MF);
492 ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
494 RoundUpToAlignment(ProgInfo.LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
496 // Scratch is allocated in 256 dword blocks.
497 unsigned ScratchAlignShift = 10;
498 // We need to program the hardware with the amount of scratch memory that
499 // is used by the entire wave. ProgInfo.ScratchSize is the amount of
500 // scratch memory used per thread.
501 ProgInfo.ScratchBlocks =
502 RoundUpToAlignment(ProgInfo.ScratchSize * STM.getWavefrontSize(),
503 1 << ScratchAlignShift) >> ScratchAlignShift;
505 ProgInfo.ComputePGMRSrc1 =
506 S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
507 S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
508 S_00B848_PRIORITY(ProgInfo.Priority) |
509 S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
510 S_00B848_PRIV(ProgInfo.Priv) |
511 S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
512 S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
513 S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
515 // 0 = X, 1 = XY, 2 = XYZ
516 unsigned TIDIGCompCnt = 0;
517 if (MFI->hasWorkItemIDZ())
519 else if (MFI->hasWorkItemIDY())
522 ProgInfo.ComputePGMRSrc2 =
523 S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
524 S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
525 S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
526 S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
527 S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
528 S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
529 S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
530 S_00B84C_EXCP_EN_MSB(0) |
531 S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks) |
535 static unsigned getRsrcReg(unsigned ShaderType) {
536 switch (ShaderType) {
537 default: // Fall through
538 case ShaderType::COMPUTE: return R_00B848_COMPUTE_PGM_RSRC1;
539 case ShaderType::GEOMETRY: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
540 case ShaderType::PIXEL: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
541 case ShaderType::VERTEX: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
545 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
546 const SIProgramInfo &KernelInfo) {
547 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
548 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
549 unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
551 if (MFI->getShaderType() == ShaderType::COMPUTE) {
552 OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
554 OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
556 OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
557 OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
559 OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
560 OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
562 // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
563 // 0" comment but I don't see a corresponding field in the register spec.
565 OutStreamer->EmitIntValue(RsrcReg, 4);
566 OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
567 S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
568 if (STM.isVGPRSpillingEnabled(MFI)) {
569 OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
570 OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
574 if (MFI->getShaderType() == ShaderType::PIXEL) {
575 OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
576 OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
577 OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
578 OutStreamer->EmitIntValue(MFI->PSInputAddr, 4);
582 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
583 const SIProgramInfo &KernelInfo) const {
584 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
585 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>();
586 amd_kernel_code_t header;
588 AMDGPU::initDefaultAMDKernelCodeT(header, STM.getFeatureBits());
590 header.compute_pgm_resource_registers =
591 KernelInfo.ComputePGMRSrc1 |
592 (KernelInfo.ComputePGMRSrc2 << 32);
593 header.code_properties = AMD_CODE_PROPERTY_IS_PTR64;
595 if (MFI->hasPrivateSegmentBuffer()) {
596 header.code_properties |=
597 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
600 if (MFI->hasDispatchPtr())
601 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
603 if (MFI->hasQueuePtr())
604 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
606 if (MFI->hasKernargSegmentPtr())
607 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
609 if (MFI->hasDispatchID())
610 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
612 if (MFI->hasFlatScratchInit())
613 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
615 // TODO: Private segment size
617 if (MFI->hasGridWorkgroupCountX()) {
618 header.code_properties |=
619 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
622 if (MFI->hasGridWorkgroupCountY()) {
623 header.code_properties |=
624 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
627 if (MFI->hasGridWorkgroupCountZ()) {
628 header.code_properties |=
629 AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
632 if (MFI->hasDispatchPtr())
633 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
635 if (STM.isXNACKEnabled())
636 header.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
638 header.kernarg_segment_byte_size = MFI->ABIArgOffset;
639 header.wavefront_sgpr_count = KernelInfo.NumSGPR;
640 header.workitem_vgpr_count = KernelInfo.NumVGPR;
641 header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
642 header.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
644 AMDGPUTargetStreamer *TS =
645 static_cast<AMDGPUTargetStreamer *>(OutStreamer->getTargetStreamer());
646 TS->EmitAMDKernelCodeT(header);
649 bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
651 const char *ExtraCode, raw_ostream &O) {
652 if (ExtraCode && ExtraCode[0]) {
653 if (ExtraCode[1] != 0)
654 return true; // Unknown modifier.
656 switch (ExtraCode[0]) {
658 // See if this is a generic print operand
659 return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);
665 AMDGPUInstPrinter::printRegOperand(MI->getOperand(OpNo).getReg(), O,
666 *TM.getSubtargetImpl(*MF->getFunction())->getRegisterInfo());