1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "R600InstrInfo.h"
19 #include "SIDefines.h"
20 #include "SIISelLowering.h"
21 #include "SIMachineFunctionInfo.h"
22 #include "llvm/CodeGen/FunctionLoweringInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/IR/Function.h"
32 //===----------------------------------------------------------------------===//
33 // Instruction Selector Implementation
34 //===----------------------------------------------------------------------===//
37 /// AMDGPU specific code to select AMDGPU machine instructions for
38 /// SelectionDAG operations.
39 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
40 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
41 // make the right decision when generating code for different targets.
42 const AMDGPUSubtarget *Subtarget;
44 AMDGPUDAGToDAGISel(TargetMachine &TM);
45 virtual ~AMDGPUDAGToDAGISel();
46 bool runOnMachineFunction(MachineFunction &MF) override;
47 SDNode *Select(SDNode *N) override;
48 const char *getPassName() const override;
49 void PostprocessISelDAG() override;
52 bool isInlineImmediate(SDNode *N) const;
53 bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
54 const R600InstrInfo *TII);
55 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
56 bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
58 // Complex pattern selectors
59 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
60 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
61 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
63 static bool checkType(const Value *ptr, unsigned int addrspace);
64 static bool checkPrivateAddress(const MachineMemOperand *Op);
66 static bool isGlobalStore(const StoreSDNode *N);
67 static bool isFlatStore(const StoreSDNode *N);
68 static bool isPrivateStore(const StoreSDNode *N);
69 static bool isLocalStore(const StoreSDNode *N);
70 static bool isRegionStore(const StoreSDNode *N);
72 bool isCPLoad(const LoadSDNode *N) const;
73 bool isConstantLoad(const LoadSDNode *N, int cbID) const;
74 bool isGlobalLoad(const LoadSDNode *N) const;
75 bool isFlatLoad(const LoadSDNode *N) const;
76 bool isParamLoad(const LoadSDNode *N) const;
77 bool isPrivateLoad(const LoadSDNode *N) const;
78 bool isLocalLoad(const LoadSDNode *N) const;
79 bool isRegionLoad(const LoadSDNode *N) const;
81 SDNode *glueCopyToM0(SDNode *N) const;
83 const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
84 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
85 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
87 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
88 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
89 bool isDSOffsetLegal(const SDValue &Base, unsigned Offset,
90 unsigned OffsetBits) const;
91 bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
92 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
93 SDValue &Offset1) const;
94 void SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
95 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
96 SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
98 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
99 SDValue &SOffset, SDValue &Offset, SDValue &GLC,
100 SDValue &SLC, SDValue &TFE) const;
101 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
102 SDValue &VAddr, SDValue &SOffset, SDValue &Offset,
104 bool SelectMUBUFScratch(SDValue Addr, SDValue &RSrc, SDValue &VAddr,
105 SDValue &SOffset, SDValue &ImmOffset) const;
106 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
107 SDValue &Offset, SDValue &GLC, SDValue &SLC,
109 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
110 SDValue &Offset, SDValue &GLC) const;
111 SDNode *SelectAddrSpaceCast(SDNode *N);
112 bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
113 bool SelectVOP3NoMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
114 bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
115 SDValue &Clamp, SDValue &Omod) const;
116 bool SelectVOP3NoMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
117 SDValue &Clamp, SDValue &Omod) const;
119 bool SelectVOP3Mods0Clamp(SDValue In, SDValue &Src, SDValue &SrcMods,
120 SDValue &Omod) const;
121 bool SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src, SDValue &SrcMods,
123 SDValue &Omod) const;
125 SDNode *SelectADD_SUB_I64(SDNode *N);
126 SDNode *SelectDIV_SCALE(SDNode *N);
128 SDNode *getS_BFE(unsigned Opcode, SDLoc DL, SDValue Val,
129 uint32_t Offset, uint32_t Width);
130 SDNode *SelectS_BFEFromShifts(SDNode *N);
131 SDNode *SelectS_BFE(SDNode *N);
133 // Include the pieces autogenerated from the target description.
134 #include "AMDGPUGenDAGISel.inc"
136 } // end anonymous namespace
138 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
139 // DAG, ready for instruction scheduling.
140 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM) {
141 return new AMDGPUDAGToDAGISel(TM);
144 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM)
145 : SelectionDAGISel(TM) {}
147 bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
148 Subtarget = &static_cast<const AMDGPUSubtarget &>(MF.getSubtarget());
149 return SelectionDAGISel::runOnMachineFunction(MF);
152 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
155 bool AMDGPUDAGToDAGISel::isInlineImmediate(SDNode *N) const {
156 const SITargetLowering *TL
157 = static_cast<const SITargetLowering *>(getTargetLowering());
158 return TL->analyzeImmediate(N) == 0;
161 /// \brief Determine the register class for \p OpNo
162 /// \returns The register class of the virtual register that will be used for
163 /// the given operand number \OpNo or NULL if the register class cannot be
165 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
166 unsigned OpNo) const {
167 if (!N->isMachineOpcode())
170 switch (N->getMachineOpcode()) {
172 const MCInstrDesc &Desc =
173 Subtarget->getInstrInfo()->get(N->getMachineOpcode());
174 unsigned OpIdx = Desc.getNumDefs() + OpNo;
175 if (OpIdx >= Desc.getNumOperands())
177 int RegClass = Desc.OpInfo[OpIdx].RegClass;
181 return Subtarget->getRegisterInfo()->getRegClass(RegClass);
183 case AMDGPU::REG_SEQUENCE: {
184 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
185 const TargetRegisterClass *SuperRC =
186 Subtarget->getRegisterInfo()->getRegClass(RCID);
188 SDValue SubRegOp = N->getOperand(OpNo + 1);
189 unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
190 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
196 bool AMDGPUDAGToDAGISel::SelectADDRParam(
197 SDValue Addr, SDValue& R1, SDValue& R2) {
199 if (Addr.getOpcode() == ISD::FrameIndex) {
200 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
201 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
202 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
205 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
207 } else if (Addr.getOpcode() == ISD::ADD) {
208 R1 = Addr.getOperand(0);
209 R2 = Addr.getOperand(1);
212 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
217 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
218 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
219 Addr.getOpcode() == ISD::TargetGlobalAddress) {
222 return SelectADDRParam(Addr, R1, R2);
226 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
227 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
228 Addr.getOpcode() == ISD::TargetGlobalAddress) {
232 if (Addr.getOpcode() == ISD::FrameIndex) {
233 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
234 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
235 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i64);
238 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i64);
240 } else if (Addr.getOpcode() == ISD::ADD) {
241 R1 = Addr.getOperand(0);
242 R2 = Addr.getOperand(1);
245 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i64);
250 SDNode *AMDGPUDAGToDAGISel::glueCopyToM0(SDNode *N) const {
251 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
252 !checkType(cast<MemSDNode>(N)->getMemOperand()->getValue(),
253 AMDGPUAS::LOCAL_ADDRESS))
256 const SITargetLowering& Lowering =
257 *static_cast<const SITargetLowering*>(getTargetLowering());
259 // Write max value to m0 before each load operation
261 SDValue M0 = Lowering.copyToM0(*CurDAG, CurDAG->getEntryNode(), SDLoc(N),
262 CurDAG->getTargetConstant(-1, SDLoc(N), MVT::i32));
264 SDValue Glue = M0.getValue(1);
266 SmallVector <SDValue, 8> Ops;
267 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
268 Ops.push_back(N->getOperand(i));
271 CurDAG->MorphNodeTo(N, N->getOpcode(), N->getVTList(), Ops);
276 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
277 unsigned int Opc = N->getOpcode();
278 if (N->isMachineOpcode()) {
280 return nullptr; // Already selected.
283 if (isa<AtomicSDNode>(N))
288 // We are selecting i64 ADD here instead of custom lower it during
289 // DAG legalization, so we can fold some i64 ADDs used for address
290 // calculation into the LOAD and STORE instructions.
293 if (N->getValueType(0) != MVT::i64 ||
294 Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
297 return SelectADD_SUB_I64(N);
299 case ISD::SCALAR_TO_VECTOR:
300 case AMDGPUISD::BUILD_VERTICAL_VECTOR:
301 case ISD::BUILD_VECTOR: {
303 const AMDGPURegisterInfo *TRI = Subtarget->getRegisterInfo();
304 EVT VT = N->getValueType(0);
305 unsigned NumVectorElts = VT.getVectorNumElements();
306 EVT EltVT = VT.getVectorElementType();
307 assert(EltVT.bitsEq(MVT::i32));
308 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
310 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
312 if (!U->isMachineOpcode()) {
315 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
319 if (static_cast<const SIRegisterInfo *>(TRI)->isSGPRClass(RC)) {
323 switch(NumVectorElts) {
324 case 1: RegClassID = UseVReg ? AMDGPU::VGPR_32RegClassID :
325 AMDGPU::SReg_32RegClassID;
327 case 2: RegClassID = UseVReg ? AMDGPU::VReg_64RegClassID :
328 AMDGPU::SReg_64RegClassID;
330 case 4: RegClassID = UseVReg ? AMDGPU::VReg_128RegClassID :
331 AMDGPU::SReg_128RegClassID;
333 case 8: RegClassID = UseVReg ? AMDGPU::VReg_256RegClassID :
334 AMDGPU::SReg_256RegClassID;
336 case 16: RegClassID = UseVReg ? AMDGPU::VReg_512RegClassID :
337 AMDGPU::SReg_512RegClassID;
339 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
342 // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
343 // that adds a 128 bits reg copy when going through TwoAddressInstructions
344 // pass. We want to avoid 128 bits copies as much as possible because they
345 // can't be bundled by our scheduler.
346 switch(NumVectorElts) {
347 case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
349 if (Opc == AMDGPUISD::BUILD_VERTICAL_VECTOR)
350 RegClassID = AMDGPU::R600_Reg128VerticalRegClassID;
352 RegClassID = AMDGPU::R600_Reg128RegClassID;
354 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
359 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
361 if (NumVectorElts == 1) {
362 return CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT,
363 N->getOperand(0), RegClass);
366 assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
368 // 16 = Max Num Vector Elements
369 // 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
370 // 1 = Vector Register Class
371 SmallVector<SDValue, 16 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);
373 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
374 bool IsRegSeq = true;
375 unsigned NOps = N->getNumOperands();
376 for (unsigned i = 0; i < NOps; i++) {
377 // XXX: Why is this here?
378 if (isa<RegisterSDNode>(N->getOperand(i))) {
382 RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
383 RegSeqArgs[1 + (2 * i) + 1] =
384 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL,
388 if (NOps != NumVectorElts) {
389 // Fill in the missing undef elements if this was a scalar_to_vector.
390 assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
392 MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
394 for (unsigned i = NOps; i < NumVectorElts; ++i) {
395 RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0);
396 RegSeqArgs[1 + (2 * i) + 1] =
397 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, MVT::i32);
403 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
406 case ISD::BUILD_PAIR: {
407 SDValue RC, SubReg0, SubReg1;
408 if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
412 if (N->getValueType(0) == MVT::i128) {
413 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32);
414 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32);
415 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32);
416 } else if (N->getValueType(0) == MVT::i64) {
417 RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32);
418 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
419 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
421 llvm_unreachable("Unhandled value type for BUILD_PAIR");
423 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
424 N->getOperand(1), SubReg1 };
425 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
426 DL, N->getValueType(0), Ops);
430 case ISD::ConstantFP: {
431 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
432 N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N))
436 if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
437 Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
439 ConstantSDNode *C = cast<ConstantSDNode>(N);
440 Imm = C->getZExtValue();
444 SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
445 CurDAG->getConstant(Imm & 0xFFFFFFFF, DL,
447 SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
448 CurDAG->getConstant(Imm >> 32, DL, MVT::i32));
449 const SDValue Ops[] = {
450 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
451 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
452 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
455 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
456 N->getValueType(0), Ops);
460 LoadSDNode *LD = cast<LoadSDNode>(N);
462 EVT VT = N->getValueType(0);
464 if (VT != MVT::i64 || LD->getExtensionType() != ISD::NON_EXTLOAD) {
469 // To simplify the TableGen patters, we replace all i64 loads with
470 // v2i32 loads. Alternatively, we could promote i64 loads to v2i32
471 // during DAG legalization, however, so places (ExpandUnalignedLoad)
472 // in the DAG legalizer assume that if i64 is legal, so doing this
473 // promotion early can cause problems.
475 SDValue NewLoad = CurDAG->getLoad(MVT::v2i32, SDLoc(N), LD->getChain(),
476 LD->getBasePtr(), LD->getMemOperand());
477 SDValue BitCast = CurDAG->getNode(ISD::BITCAST, SL,
479 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLoad.getValue(1));
480 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), BitCast);
481 SDNode *Load = glueCopyToM0(NewLoad.getNode());
483 N = BitCast.getNode();
488 // Handle i64 stores here for the same reason mentioned above for loads.
489 StoreSDNode *ST = cast<StoreSDNode>(N);
490 SDValue Value = ST->getValue();
491 if (Value.getValueType() == MVT::i64 && !ST->isTruncatingStore()) {
493 SDValue NewValue = CurDAG->getNode(ISD::BITCAST, SDLoc(N),
495 SDValue NewStore = CurDAG->getStore(ST->getChain(), SDLoc(N), NewValue,
496 ST->getBasePtr(), ST->getMemOperand());
498 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), NewStore);
500 if (NewValue.getOpcode() == ISD::BITCAST) {
501 Select(NewStore.getNode());
502 return SelectCode(NewValue.getNode());
505 // getNode() may fold the bitcast if its input was another bitcast. If that
506 // happens we should only select the new store.
507 N = NewStore.getNode();
514 case AMDGPUISD::REGISTER_LOAD: {
515 if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
517 SDValue Addr, Offset;
520 SelectADDRIndirect(N->getOperand(1), Addr, Offset);
521 const SDValue Ops[] = {
524 CurDAG->getTargetConstant(0, DL, MVT::i32),
527 return CurDAG->getMachineNode(AMDGPU::SI_RegisterLoad, DL,
528 CurDAG->getVTList(MVT::i32, MVT::i64,
532 case AMDGPUISD::REGISTER_STORE: {
533 if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
535 SDValue Addr, Offset;
536 SelectADDRIndirect(N->getOperand(2), Addr, Offset);
538 const SDValue Ops[] = {
542 CurDAG->getTargetConstant(0, DL, MVT::i32),
545 return CurDAG->getMachineNode(AMDGPU::SI_RegisterStorePseudo, DL,
546 CurDAG->getVTList(MVT::Other),
550 case AMDGPUISD::BFE_I32:
551 case AMDGPUISD::BFE_U32: {
552 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
555 // There is a scalar version available, but unlike the vector version which
556 // has a separate operand for the offset and width, the scalar version packs
557 // the width and offset into a single operand. Try to move to the scalar
558 // version if the offsets are constant, so that we can try to keep extended
559 // loads of kernel arguments in SGPRs.
561 // TODO: Technically we could try to pattern match scalar bitshifts of
562 // dynamic values, but it's probably not useful.
563 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
567 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
571 bool Signed = Opc == AMDGPUISD::BFE_I32;
573 uint32_t OffsetVal = Offset->getZExtValue();
574 uint32_t WidthVal = Width->getZExtValue();
576 return getS_BFE(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32, SDLoc(N),
577 N->getOperand(0), OffsetVal, WidthVal);
580 case AMDGPUISD::DIV_SCALE: {
581 return SelectDIV_SCALE(N);
583 case ISD::CopyToReg: {
584 const SITargetLowering& Lowering =
585 *static_cast<const SITargetLowering*>(getTargetLowering());
586 Lowering.legalizeTargetIndependentNode(N, *CurDAG);
589 case ISD::ADDRSPACECAST:
590 return SelectAddrSpaceCast(N);
594 if (N->getValueType(0) != MVT::i32 ||
595 Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
598 return SelectS_BFE(N);
601 return SelectCode(N);
605 bool AMDGPUDAGToDAGISel::checkType(const Value *Ptr, unsigned AS) {
606 assert(AS != 0 && "Use checkPrivateAddress instead.");
610 return Ptr->getType()->getPointerAddressSpace() == AS;
613 bool AMDGPUDAGToDAGISel::checkPrivateAddress(const MachineMemOperand *Op) {
614 if (Op->getPseudoValue())
617 if (PointerType *PT = dyn_cast<PointerType>(Op->getValue()->getType()))
618 return PT->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
623 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
624 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
627 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
628 const Value *MemVal = N->getMemOperand()->getValue();
629 return (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
630 !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
631 !checkType(MemVal, AMDGPUAS::REGION_ADDRESS));
634 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
635 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
638 bool AMDGPUDAGToDAGISel::isFlatStore(const StoreSDNode *N) {
639 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
642 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
643 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
646 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int CbId) const {
647 const Value *MemVal = N->getMemOperand()->getValue();
649 return checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS);
651 return checkType(MemVal, AMDGPUAS::CONSTANT_BUFFER_0 + CbId);
654 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const {
655 if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS)
656 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
657 N->getMemoryVT().bitsLT(MVT::i32))
660 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
663 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) const {
664 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::PARAM_I_ADDRESS);
667 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) const {
668 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
671 bool AMDGPUDAGToDAGISel::isFlatLoad(const LoadSDNode *N) const {
672 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
675 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) const {
676 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
679 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) const {
680 MachineMemOperand *MMO = N->getMemOperand();
681 if (checkPrivateAddress(N->getMemOperand())) {
683 const PseudoSourceValue *PSV = MMO->getPseudoValue();
684 if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
692 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
693 if (checkPrivateAddress(N->getMemOperand())) {
694 // Check to make sure we are not a constant pool load or a constant load
695 // that is marked as a private load
696 if (isCPLoad(N) || isConstantLoad(N, -1)) {
701 const Value *MemVal = N->getMemOperand()->getValue();
702 if (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
703 !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
704 !checkType(MemVal, AMDGPUAS::FLAT_ADDRESS) &&
705 !checkType(MemVal, AMDGPUAS::REGION_ADDRESS) &&
706 !checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS) &&
707 !checkType(MemVal, AMDGPUAS::PARAM_D_ADDRESS) &&
708 !checkType(MemVal, AMDGPUAS::PARAM_I_ADDRESS)) {
714 const char *AMDGPUDAGToDAGISel::getPassName() const {
715 return "AMDGPU DAG->DAG Pattern Instruction Selection";
723 //===----------------------------------------------------------------------===//
725 //===----------------------------------------------------------------------===//
727 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
729 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
730 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, SDLoc(Addr),
737 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
738 SDValue& BaseReg, SDValue &Offset) {
739 if (!isa<ConstantSDNode>(Addr)) {
741 Offset = CurDAG->getIntPtrConstant(0, SDLoc(Addr), true);
747 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
749 ConstantSDNode *IMMOffset;
751 if (Addr.getOpcode() == ISD::ADD
752 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
753 && isInt<16>(IMMOffset->getZExtValue())) {
755 Base = Addr.getOperand(0);
756 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
759 // If the pointer address is constant, we can move it to the offset field.
760 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
761 && isInt<16>(IMMOffset->getZExtValue())) {
762 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
763 SDLoc(CurDAG->getEntryNode()),
764 AMDGPU::ZERO, MVT::i32);
765 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
770 // Default case, no offset
772 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
776 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
781 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
782 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
783 Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
784 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
785 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
786 Base = Addr.getOperand(0);
787 Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
790 Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
796 SDNode *AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
798 SDValue LHS = N->getOperand(0);
799 SDValue RHS = N->getOperand(1);
801 bool IsAdd = (N->getOpcode() == ISD::ADD);
803 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
804 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
806 SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
807 DL, MVT::i32, LHS, Sub0);
808 SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
809 DL, MVT::i32, LHS, Sub1);
811 SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
812 DL, MVT::i32, RHS, Sub0);
813 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
814 DL, MVT::i32, RHS, Sub1);
816 SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
817 SDValue AddLoArgs[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) };
820 unsigned Opc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
821 unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
823 SDNode *AddLo = CurDAG->getMachineNode( Opc, DL, VTList, AddLoArgs);
824 SDValue Carry(AddLo, 1);
826 = CurDAG->getMachineNode(CarryOpc, DL, MVT::i32,
827 SDValue(Hi0, 0), SDValue(Hi1, 0), Carry);
830 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
836 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args);
839 // We need to handle this here because tablegen doesn't support matching
840 // instructions with multiple outputs.
841 SDNode *AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
843 EVT VT = N->getValueType(0);
845 assert(VT == MVT::f32 || VT == MVT::f64);
848 = (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64 : AMDGPU::V_DIV_SCALE_F32;
850 // src0_modifiers, src0, src1_modifiers, src1, src2_modifiers, src2, clamp, omod
853 SelectVOP3Mods0(N->getOperand(0), Ops[1], Ops[0], Ops[6], Ops[7]);
854 SelectVOP3Mods(N->getOperand(1), Ops[3], Ops[2]);
855 SelectVOP3Mods(N->getOperand(2), Ops[5], Ops[4]);
856 return CurDAG->SelectNodeTo(N, Opc, VT, MVT::i1, Ops);
859 bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset,
860 unsigned OffsetBits) const {
861 if ((OffsetBits == 16 && !isUInt<16>(Offset)) ||
862 (OffsetBits == 8 && !isUInt<8>(Offset)))
865 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS ||
866 Subtarget->unsafeDSOffsetFoldingEnabled())
869 // On Southern Islands instruction with a negative base value and an offset
870 // don't seem to work.
871 return CurDAG->SignBitIsZero(Base);
874 bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
875 SDValue &Offset) const {
876 if (CurDAG->isBaseWithConstantOffset(Addr)) {
877 SDValue N0 = Addr.getOperand(0);
878 SDValue N1 = Addr.getOperand(1);
879 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
880 if (isDSOffsetLegal(N0, C1->getSExtValue(), 16)) {
890 // If we have a constant address, prefer to put the constant into the
891 // offset. This can save moves to load the constant address since multiple
892 // operations can share the zero base address register, and enables merging
893 // into read2 / write2 instructions.
894 if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
895 if (isUInt<16>(CAddr->getZExtValue())) {
896 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
897 MachineSDNode *MovZero = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
899 Base = SDValue(MovZero, 0);
907 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
911 bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
913 SDValue &Offset1) const {
916 if (CurDAG->isBaseWithConstantOffset(Addr)) {
917 SDValue N0 = Addr.getOperand(0);
918 SDValue N1 = Addr.getOperand(1);
919 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
920 unsigned DWordOffset0 = C1->getZExtValue() / 4;
921 unsigned DWordOffset1 = DWordOffset0 + 1;
923 if (isDSOffsetLegal(N0, DWordOffset1, 8)) {
925 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
926 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
931 if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
932 unsigned DWordOffset0 = CAddr->getZExtValue() / 4;
933 unsigned DWordOffset1 = DWordOffset0 + 1;
934 assert(4 * DWordOffset0 == CAddr->getZExtValue());
936 if (isUInt<8>(DWordOffset0) && isUInt<8>(DWordOffset1)) {
937 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
938 MachineSDNode *MovZero
939 = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
941 Base = SDValue(MovZero, 0);
942 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
943 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
950 Offset0 = CurDAG->getTargetConstant(0, DL, MVT::i8);
951 Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i8);
955 static bool isLegalMUBUFImmOffset(const ConstantSDNode *Imm) {
956 return isUInt<12>(Imm->getZExtValue());
959 void AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
960 SDValue &VAddr, SDValue &SOffset,
961 SDValue &Offset, SDValue &Offen,
962 SDValue &Idxen, SDValue &Addr64,
963 SDValue &GLC, SDValue &SLC,
964 SDValue &TFE) const {
967 GLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
968 SLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
969 TFE = CurDAG->getTargetConstant(0, DL, MVT::i1);
971 Idxen = CurDAG->getTargetConstant(0, DL, MVT::i1);
972 Offen = CurDAG->getTargetConstant(0, DL, MVT::i1);
973 Addr64 = CurDAG->getTargetConstant(0, DL, MVT::i1);
974 SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);
976 if (CurDAG->isBaseWithConstantOffset(Addr)) {
977 SDValue N0 = Addr.getOperand(0);
978 SDValue N1 = Addr.getOperand(1);
979 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
981 if (N0.getOpcode() == ISD::ADD) {
982 // (add (add N2, N3), C1) -> addr64
983 SDValue N2 = N0.getOperand(0);
984 SDValue N3 = N0.getOperand(1);
985 Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
990 // (add N0, C1) -> offset
991 VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
995 if (isLegalMUBUFImmOffset(C1)) {
996 Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
998 } else if (isUInt<32>(C1->getZExtValue())) {
999 // Illegal offset, store it in soffset.
1000 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1001 SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
1002 CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32)),
1008 if (Addr.getOpcode() == ISD::ADD) {
1009 // (add N0, N1) -> addr64
1010 SDValue N0 = Addr.getOperand(0);
1011 SDValue N1 = Addr.getOperand(1);
1012 Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
1015 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1019 // default case -> offset
1020 VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
1022 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1026 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
1027 SDValue &VAddr, SDValue &SOffset,
1028 SDValue &Offset, SDValue &GLC,
1029 SDValue &SLC, SDValue &TFE) const {
1030 SDValue Ptr, Offen, Idxen, Addr64;
1032 SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
1035 ConstantSDNode *C = cast<ConstantSDNode>(Addr64);
1036 if (C->getSExtValue()) {
1039 const SITargetLowering& Lowering =
1040 *static_cast<const SITargetLowering*>(getTargetLowering());
1042 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0);
1049 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
1050 SDValue &VAddr, SDValue &SOffset,
1052 SDValue &SLC) const {
1053 SLC = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i1);
1056 return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset, GLC, SLC, TFE);
1059 bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
1060 SDValue &VAddr, SDValue &SOffset,
1061 SDValue &ImmOffset) const {
1064 MachineFunction &MF = CurDAG->getMachineFunction();
1065 const SIRegisterInfo *TRI =
1066 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
1067 MachineRegisterInfo &MRI = MF.getRegInfo();
1068 const SITargetLowering& Lowering =
1069 *static_cast<const SITargetLowering*>(getTargetLowering());
1071 unsigned ScratchOffsetReg =
1072 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET);
1073 Lowering.CreateLiveInRegister(*CurDAG, &AMDGPU::SReg_32RegClass,
1074 ScratchOffsetReg, MVT::i32);
1075 SDValue Sym0 = CurDAG->getExternalSymbol("SCRATCH_RSRC_DWORD0", MVT::i32);
1076 SDValue ScratchRsrcDword0 =
1077 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, Sym0), 0);
1079 SDValue Sym1 = CurDAG->getExternalSymbol("SCRATCH_RSRC_DWORD1", MVT::i32);
1080 SDValue ScratchRsrcDword1 =
1081 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, Sym1), 0);
1083 const SDValue RsrcOps[] = {
1084 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
1086 CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
1088 CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32),
1090 SDValue ScratchPtr = SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
1091 MVT::v2i32, RsrcOps), 0);
1092 Rsrc = SDValue(Lowering.buildScratchRSRC(*CurDAG, DL, ScratchPtr), 0);
1093 SOffset = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
1094 MRI.getLiveInVirtReg(ScratchOffsetReg), MVT::i32);
1097 if (CurDAG->isBaseWithConstantOffset(Addr)) {
1098 SDValue N0 = Addr.getOperand(0);
1099 SDValue N1 = Addr.getOperand(1);
1100 // Offsets in vaddr must be positive.
1101 if (CurDAG->SignBitIsZero(N0)) {
1102 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
1103 if (isLegalMUBUFImmOffset(C1)) {
1105 ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
1113 ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1117 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1118 SDValue &SOffset, SDValue &Offset,
1119 SDValue &GLC, SDValue &SLC,
1120 SDValue &TFE) const {
1121 SDValue Ptr, VAddr, Offen, Idxen, Addr64;
1122 const SIInstrInfo *TII =
1123 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
1125 SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
1128 if (!cast<ConstantSDNode>(Offen)->getSExtValue() &&
1129 !cast<ConstantSDNode>(Idxen)->getSExtValue() &&
1130 !cast<ConstantSDNode>(Addr64)->getSExtValue()) {
1131 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() |
1132 APInt::getAllOnesValue(32).getZExtValue(); // Size
1135 const SITargetLowering& Lowering =
1136 *static_cast<const SITargetLowering*>(getTargetLowering());
1138 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0);
1144 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1145 SDValue &Soffset, SDValue &Offset,
1146 SDValue &GLC) const {
1149 return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
1152 // FIXME: This is incorrect and only enough to be able to compile.
1153 SDNode *AMDGPUDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
1154 AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(N);
1157 assert(Subtarget->hasFlatAddressSpace() &&
1158 "addrspacecast only supported with flat address space!");
1160 assert((ASC->getSrcAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS &&
1161 ASC->getDestAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS) &&
1162 "Cannot cast address space to / from constant address!");
1164 assert((ASC->getSrcAddressSpace() == AMDGPUAS::FLAT_ADDRESS ||
1165 ASC->getDestAddressSpace() == AMDGPUAS::FLAT_ADDRESS) &&
1166 "Can only cast to / from flat address space!");
1168 // The flat instructions read the address as the index of the VGPR holding the
1169 // address, so casting should just be reinterpreting the base VGPR, so just
1170 // insert trunc / bitcast / zext.
1172 SDValue Src = ASC->getOperand(0);
1173 EVT DestVT = ASC->getValueType(0);
1174 EVT SrcVT = Src.getValueType();
1176 unsigned SrcSize = SrcVT.getSizeInBits();
1177 unsigned DestSize = DestVT.getSizeInBits();
1179 if (SrcSize > DestSize) {
1180 assert(SrcSize == 64 && DestSize == 32);
1181 return CurDAG->getMachineNode(
1182 TargetOpcode::EXTRACT_SUBREG,
1186 CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32));
1190 if (DestSize > SrcSize) {
1191 assert(SrcSize == 32 && DestSize == 64);
1193 // FIXME: This is probably wrong, we should never be defining
1194 // a register class with both VGPRs and SGPRs
1195 SDValue RC = CurDAG->getTargetConstant(AMDGPU::VS_64RegClassID, DL,
1198 const SDValue Ops[] = {
1201 CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
1202 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
1203 CurDAG->getConstant(0, DL, MVT::i32)), 0),
1204 CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
1207 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
1208 DL, N->getValueType(0), Ops);
1211 assert(SrcSize == 64 && DestSize == 64);
1212 return CurDAG->getNode(ISD::BITCAST, DL, DestVT, Src).getNode();
1215 SDNode *AMDGPUDAGToDAGISel::getS_BFE(unsigned Opcode, SDLoc DL, SDValue Val,
1216 uint32_t Offset, uint32_t Width) {
1217 // Transformation function, pack the offset and width of a BFE into
1218 // the format expected by the S_BFE_I32 / S_BFE_U32. In the second
1219 // source, bits [5:0] contain the offset and bits [22:16] the width.
1220 uint32_t PackedVal = Offset | (Width << 16);
1221 SDValue PackedConst = CurDAG->getTargetConstant(PackedVal, DL, MVT::i32);
1223 return CurDAG->getMachineNode(Opcode, DL, MVT::i32, Val, PackedConst);
1226 SDNode *AMDGPUDAGToDAGISel::SelectS_BFEFromShifts(SDNode *N) {
1227 // "(a << b) srl c)" ---> "BFE_U32 a, (c-b), (32-c)
1228 // "(a << b) sra c)" ---> "BFE_I32 a, (c-b), (32-c)
1229 // Predicate: 0 < b <= c < 32
1231 const SDValue &Shl = N->getOperand(0);
1232 ConstantSDNode *B = dyn_cast<ConstantSDNode>(Shl->getOperand(1));
1233 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1236 uint32_t BVal = B->getZExtValue();
1237 uint32_t CVal = C->getZExtValue();
1239 if (0 < BVal && BVal <= CVal && CVal < 32) {
1240 bool Signed = N->getOpcode() == ISD::SRA;
1241 unsigned Opcode = Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32;
1243 return getS_BFE(Opcode, SDLoc(N), Shl.getOperand(0),
1244 CVal - BVal, 32 - CVal);
1247 return SelectCode(N);
1250 SDNode *AMDGPUDAGToDAGISel::SelectS_BFE(SDNode *N) {
1251 switch (N->getOpcode()) {
1253 if (N->getOperand(0).getOpcode() == ISD::SRL) {
1254 // "(a srl b) & mask" ---> "BFE_U32 a, b, popcount(mask)"
1255 // Predicate: isMask(mask)
1256 const SDValue &Srl = N->getOperand(0);
1257 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1));
1258 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));
1260 if (Shift && Mask) {
1261 uint32_t ShiftVal = Shift->getZExtValue();
1262 uint32_t MaskVal = Mask->getZExtValue();
1264 if (isMask_32(MaskVal)) {
1265 uint32_t WidthVal = countPopulation(MaskVal);
1267 return getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N), Srl.getOperand(0),
1268 ShiftVal, WidthVal);
1274 if (N->getOperand(0).getOpcode() == ISD::AND) {
1275 // "(a & mask) srl b)" ---> "BFE_U32 a, b, popcount(mask >> b)"
1276 // Predicate: isMask(mask >> b)
1277 const SDValue &And = N->getOperand(0);
1278 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(N->getOperand(1));
1279 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(And->getOperand(1));
1281 if (Shift && Mask) {
1282 uint32_t ShiftVal = Shift->getZExtValue();
1283 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal;
1285 if (isMask_32(MaskVal)) {
1286 uint32_t WidthVal = countPopulation(MaskVal);
1288 return getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N), And.getOperand(0),
1289 ShiftVal, WidthVal);
1292 } else if (N->getOperand(0).getOpcode() == ISD::SHL)
1293 return SelectS_BFEFromShifts(N);
1296 if (N->getOperand(0).getOpcode() == ISD::SHL)
1297 return SelectS_BFEFromShifts(N);
1301 return SelectCode(N);
1304 bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
1305 SDValue &SrcMods) const {
1311 if (Src.getOpcode() == ISD::FNEG) {
1312 Mods |= SISrcMods::NEG;
1313 Src = Src.getOperand(0);
1316 if (Src.getOpcode() == ISD::FABS) {
1317 Mods |= SISrcMods::ABS;
1318 Src = Src.getOperand(0);
1321 SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
1326 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods(SDValue In, SDValue &Src,
1327 SDValue &SrcMods) const {
1328 bool Res = SelectVOP3Mods(In, Src, SrcMods);
1329 return Res && cast<ConstantSDNode>(SrcMods)->isNullValue();
1332 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
1333 SDValue &SrcMods, SDValue &Clamp,
1334 SDValue &Omod) const {
1336 // FIXME: Handle Clamp and Omod
1337 Clamp = CurDAG->getTargetConstant(0, DL, MVT::i32);
1338 Omod = CurDAG->getTargetConstant(0, DL, MVT::i32);
1340 return SelectVOP3Mods(In, Src, SrcMods);
1343 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods0(SDValue In, SDValue &Src,
1344 SDValue &SrcMods, SDValue &Clamp,
1345 SDValue &Omod) const {
1346 bool Res = SelectVOP3Mods0(In, Src, SrcMods, Clamp, Omod);
1348 return Res && cast<ConstantSDNode>(SrcMods)->isNullValue() &&
1349 cast<ConstantSDNode>(Clamp)->isNullValue() &&
1350 cast<ConstantSDNode>(Omod)->isNullValue();
1353 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp(SDValue In, SDValue &Src,
1355 SDValue &Omod) const {
1356 // FIXME: Handle Omod
1357 Omod = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
1359 return SelectVOP3Mods(In, Src, SrcMods);
1362 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src,
1365 SDValue &Omod) const {
1366 Clamp = Omod = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
1367 return SelectVOP3Mods(In, Src, SrcMods);
1370 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
1371 const AMDGPUTargetLowering& Lowering =
1372 *static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
1373 bool IsModified = false;
1376 // Go over all selected nodes and try to fold them a bit more
1377 for (SDNode &Node : CurDAG->allnodes()) {
1378 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(&Node);
1382 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
1383 if (ResNode != &Node) {
1384 ReplaceUses(&Node, ResNode);
1388 CurDAG->RemoveDeadNodes();
1389 } while (IsModified);