1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "R600InstrInfo.h"
19 #include "SIDefines.h"
20 #include "SIISelLowering.h"
21 #include "SIMachineFunctionInfo.h"
22 #include "llvm/CodeGen/FunctionLoweringInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/IR/Function.h"
32 //===----------------------------------------------------------------------===//
33 // Instruction Selector Implementation
34 //===----------------------------------------------------------------------===//
37 /// AMDGPU specific code to select AMDGPU machine instructions for
38 /// SelectionDAG operations.
39 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
40 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
41 // make the right decision when generating code for different targets.
42 const AMDGPUSubtarget *Subtarget;
45 AMDGPUDAGToDAGISel(TargetMachine &TM);
46 virtual ~AMDGPUDAGToDAGISel();
47 bool runOnMachineFunction(MachineFunction &MF) override;
48 SDNode *Select(SDNode *N) override;
49 const char *getPassName() const override;
50 void PostprocessISelDAG() override;
53 bool isInlineImmediate(SDNode *N) const;
54 bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
55 const R600InstrInfo *TII);
56 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
57 bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
59 // Complex pattern selectors
60 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
61 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
62 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
64 static bool checkType(const Value *ptr, unsigned int addrspace);
65 static bool checkPrivateAddress(const MachineMemOperand *Op);
67 static bool isGlobalStore(const StoreSDNode *N);
68 static bool isFlatStore(const StoreSDNode *N);
69 static bool isPrivateStore(const StoreSDNode *N);
70 static bool isLocalStore(const StoreSDNode *N);
71 static bool isRegionStore(const StoreSDNode *N);
73 bool isCPLoad(const LoadSDNode *N) const;
74 bool isConstantLoad(const LoadSDNode *N, int cbID) const;
75 bool isGlobalLoad(const LoadSDNode *N) const;
76 bool isFlatLoad(const LoadSDNode *N) const;
77 bool isParamLoad(const LoadSDNode *N) const;
78 bool isPrivateLoad(const LoadSDNode *N) const;
79 bool isLocalLoad(const LoadSDNode *N) const;
80 bool isRegionLoad(const LoadSDNode *N) const;
82 SDNode *glueCopyToM0(SDNode *N) const;
84 const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
85 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
86 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
88 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
89 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
90 bool isDSOffsetLegal(const SDValue &Base, unsigned Offset,
91 unsigned OffsetBits) const;
92 bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
93 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
94 SDValue &Offset1) const;
95 void SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
96 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
97 SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
99 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
100 SDValue &SOffset, SDValue &Offset, SDValue &GLC,
101 SDValue &SLC, SDValue &TFE) const;
102 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
103 SDValue &VAddr, SDValue &SOffset, SDValue &Offset,
105 bool SelectMUBUFScratch(SDValue Addr, SDValue &RSrc, SDValue &VAddr,
106 SDValue &SOffset, SDValue &ImmOffset) const;
107 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
108 SDValue &Offset, SDValue &GLC, SDValue &SLC,
110 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
111 SDValue &Offset, SDValue &GLC) const;
112 bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset,
114 bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset,
116 bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
117 bool SelectSMRDImm32(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
118 bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
119 bool SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const;
120 bool SelectSMRDBufferImm32(SDValue Addr, SDValue &Offset) const;
121 bool SelectSMRDBufferSgpr(SDValue Addr, SDValue &Offset) const;
122 SDNode *SelectAddrSpaceCast(SDNode *N);
123 bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
124 bool SelectVOP3NoMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
125 bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
126 SDValue &Clamp, SDValue &Omod) const;
127 bool SelectVOP3NoMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
128 SDValue &Clamp, SDValue &Omod) const;
130 bool SelectVOP3Mods0Clamp(SDValue In, SDValue &Src, SDValue &SrcMods,
131 SDValue &Omod) const;
132 bool SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src, SDValue &SrcMods,
134 SDValue &Omod) const;
136 SDNode *SelectADD_SUB_I64(SDNode *N);
137 SDNode *SelectDIV_SCALE(SDNode *N);
139 SDNode *getS_BFE(unsigned Opcode, SDLoc DL, SDValue Val,
140 uint32_t Offset, uint32_t Width);
141 SDNode *SelectS_BFEFromShifts(SDNode *N);
142 SDNode *SelectS_BFE(SDNode *N);
144 // Include the pieces autogenerated from the target description.
145 #include "AMDGPUGenDAGISel.inc"
147 } // end anonymous namespace
149 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
150 // DAG, ready for instruction scheduling.
151 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM) {
152 return new AMDGPUDAGToDAGISel(TM);
155 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM)
156 : SelectionDAGISel(TM) {}
158 bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
159 Subtarget = &static_cast<const AMDGPUSubtarget &>(MF.getSubtarget());
160 return SelectionDAGISel::runOnMachineFunction(MF);
163 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
166 bool AMDGPUDAGToDAGISel::isInlineImmediate(SDNode *N) const {
167 const SITargetLowering *TL
168 = static_cast<const SITargetLowering *>(getTargetLowering());
169 return TL->analyzeImmediate(N) == 0;
172 /// \brief Determine the register class for \p OpNo
173 /// \returns The register class of the virtual register that will be used for
174 /// the given operand number \OpNo or NULL if the register class cannot be
176 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
177 unsigned OpNo) const {
178 if (!N->isMachineOpcode())
181 switch (N->getMachineOpcode()) {
183 const MCInstrDesc &Desc =
184 Subtarget->getInstrInfo()->get(N->getMachineOpcode());
185 unsigned OpIdx = Desc.getNumDefs() + OpNo;
186 if (OpIdx >= Desc.getNumOperands())
188 int RegClass = Desc.OpInfo[OpIdx].RegClass;
192 return Subtarget->getRegisterInfo()->getRegClass(RegClass);
194 case AMDGPU::REG_SEQUENCE: {
195 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
196 const TargetRegisterClass *SuperRC =
197 Subtarget->getRegisterInfo()->getRegClass(RCID);
199 SDValue SubRegOp = N->getOperand(OpNo + 1);
200 unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
201 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
207 bool AMDGPUDAGToDAGISel::SelectADDRParam(
208 SDValue Addr, SDValue& R1, SDValue& R2) {
210 if (Addr.getOpcode() == ISD::FrameIndex) {
211 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
212 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
213 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
216 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
218 } else if (Addr.getOpcode() == ISD::ADD) {
219 R1 = Addr.getOperand(0);
220 R2 = Addr.getOperand(1);
223 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
228 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
229 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
230 Addr.getOpcode() == ISD::TargetGlobalAddress) {
233 return SelectADDRParam(Addr, R1, R2);
237 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
238 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
239 Addr.getOpcode() == ISD::TargetGlobalAddress) {
243 if (Addr.getOpcode() == ISD::FrameIndex) {
244 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
245 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
246 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i64);
249 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i64);
251 } else if (Addr.getOpcode() == ISD::ADD) {
252 R1 = Addr.getOperand(0);
253 R2 = Addr.getOperand(1);
256 R2 = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i64);
261 SDNode *AMDGPUDAGToDAGISel::glueCopyToM0(SDNode *N) const {
262 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
263 !checkType(cast<MemSDNode>(N)->getMemOperand()->getValue(),
264 AMDGPUAS::LOCAL_ADDRESS))
267 const SITargetLowering& Lowering =
268 *static_cast<const SITargetLowering*>(getTargetLowering());
270 // Write max value to m0 before each load operation
272 SDValue M0 = Lowering.copyToM0(*CurDAG, CurDAG->getEntryNode(), SDLoc(N),
273 CurDAG->getTargetConstant(-1, SDLoc(N), MVT::i32));
275 SDValue Glue = M0.getValue(1);
277 SmallVector <SDValue, 8> Ops;
278 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
279 Ops.push_back(N->getOperand(i));
282 CurDAG->MorphNodeTo(N, N->getOpcode(), N->getVTList(), Ops);
287 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
288 unsigned int Opc = N->getOpcode();
289 if (N->isMachineOpcode()) {
291 return nullptr; // Already selected.
294 if (isa<AtomicSDNode>(N))
299 // We are selecting i64 ADD here instead of custom lower it during
300 // DAG legalization, so we can fold some i64 ADDs used for address
301 // calculation into the LOAD and STORE instructions.
304 if (N->getValueType(0) != MVT::i64 ||
305 Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
308 return SelectADD_SUB_I64(N);
310 case ISD::SCALAR_TO_VECTOR:
311 case AMDGPUISD::BUILD_VERTICAL_VECTOR:
312 case ISD::BUILD_VECTOR: {
314 const AMDGPURegisterInfo *TRI = Subtarget->getRegisterInfo();
315 EVT VT = N->getValueType(0);
316 unsigned NumVectorElts = VT.getVectorNumElements();
317 EVT EltVT = VT.getVectorElementType();
318 assert(EltVT.bitsEq(MVT::i32));
319 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
321 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
323 if (!U->isMachineOpcode()) {
326 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
330 if (static_cast<const SIRegisterInfo *>(TRI)->isSGPRClass(RC)) {
334 switch(NumVectorElts) {
335 case 1: RegClassID = UseVReg ? AMDGPU::VGPR_32RegClassID :
336 AMDGPU::SReg_32RegClassID;
338 case 2: RegClassID = UseVReg ? AMDGPU::VReg_64RegClassID :
339 AMDGPU::SReg_64RegClassID;
341 case 4: RegClassID = UseVReg ? AMDGPU::VReg_128RegClassID :
342 AMDGPU::SReg_128RegClassID;
344 case 8: RegClassID = UseVReg ? AMDGPU::VReg_256RegClassID :
345 AMDGPU::SReg_256RegClassID;
347 case 16: RegClassID = UseVReg ? AMDGPU::VReg_512RegClassID :
348 AMDGPU::SReg_512RegClassID;
350 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
353 // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
354 // that adds a 128 bits reg copy when going through TwoAddressInstructions
355 // pass. We want to avoid 128 bits copies as much as possible because they
356 // can't be bundled by our scheduler.
357 switch(NumVectorElts) {
358 case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
360 if (Opc == AMDGPUISD::BUILD_VERTICAL_VECTOR)
361 RegClassID = AMDGPU::R600_Reg128VerticalRegClassID;
363 RegClassID = AMDGPU::R600_Reg128RegClassID;
365 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
370 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
372 if (NumVectorElts == 1) {
373 return CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT,
374 N->getOperand(0), RegClass);
377 assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
379 // 16 = Max Num Vector Elements
380 // 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
381 // 1 = Vector Register Class
382 SmallVector<SDValue, 16 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);
384 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
385 bool IsRegSeq = true;
386 unsigned NOps = N->getNumOperands();
387 for (unsigned i = 0; i < NOps; i++) {
388 // XXX: Why is this here?
389 if (isa<RegisterSDNode>(N->getOperand(i))) {
393 RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
394 RegSeqArgs[1 + (2 * i) + 1] =
395 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL,
399 if (NOps != NumVectorElts) {
400 // Fill in the missing undef elements if this was a scalar_to_vector.
401 assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
403 MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
405 for (unsigned i = NOps; i < NumVectorElts; ++i) {
406 RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0);
407 RegSeqArgs[1 + (2 * i) + 1] =
408 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, MVT::i32);
414 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
417 case ISD::BUILD_PAIR: {
418 SDValue RC, SubReg0, SubReg1;
419 if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
423 if (N->getValueType(0) == MVT::i128) {
424 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32);
425 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32);
426 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32);
427 } else if (N->getValueType(0) == MVT::i64) {
428 RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32);
429 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
430 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
432 llvm_unreachable("Unhandled value type for BUILD_PAIR");
434 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
435 N->getOperand(1), SubReg1 };
436 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
437 DL, N->getValueType(0), Ops);
441 case ISD::ConstantFP: {
442 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
443 N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N))
447 if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
448 Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
450 ConstantSDNode *C = cast<ConstantSDNode>(N);
451 Imm = C->getZExtValue();
455 SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
456 CurDAG->getConstant(Imm & 0xFFFFFFFF, DL,
458 SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
459 CurDAG->getConstant(Imm >> 32, DL, MVT::i32));
460 const SDValue Ops[] = {
461 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
462 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
463 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
466 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
467 N->getValueType(0), Ops);
471 LoadSDNode *LD = cast<LoadSDNode>(N);
473 EVT VT = N->getValueType(0);
475 if (VT != MVT::i64 || LD->getExtensionType() != ISD::NON_EXTLOAD) {
480 // To simplify the TableGen patters, we replace all i64 loads with
481 // v2i32 loads. Alternatively, we could promote i64 loads to v2i32
482 // during DAG legalization, however, so places (ExpandUnalignedLoad)
483 // in the DAG legalizer assume that if i64 is legal, so doing this
484 // promotion early can cause problems.
486 SDValue NewLoad = CurDAG->getLoad(MVT::v2i32, SDLoc(N), LD->getChain(),
487 LD->getBasePtr(), LD->getMemOperand());
488 SDValue BitCast = CurDAG->getNode(ISD::BITCAST, SL,
490 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLoad.getValue(1));
491 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), BitCast);
492 SDNode *Load = glueCopyToM0(NewLoad.getNode());
494 N = BitCast.getNode();
499 // Handle i64 stores here for the same reason mentioned above for loads.
500 StoreSDNode *ST = cast<StoreSDNode>(N);
501 SDValue Value = ST->getValue();
502 if (Value.getValueType() == MVT::i64 && !ST->isTruncatingStore()) {
504 SDValue NewValue = CurDAG->getNode(ISD::BITCAST, SDLoc(N),
506 SDValue NewStore = CurDAG->getStore(ST->getChain(), SDLoc(N), NewValue,
507 ST->getBasePtr(), ST->getMemOperand());
509 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), NewStore);
511 if (NewValue.getOpcode() == ISD::BITCAST) {
512 Select(NewStore.getNode());
513 return SelectCode(NewValue.getNode());
516 // getNode() may fold the bitcast if its input was another bitcast. If
517 // that happens we should only select the new store.
518 N = NewStore.getNode();
525 case AMDGPUISD::REGISTER_LOAD: {
526 if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
528 SDValue Addr, Offset;
531 SelectADDRIndirect(N->getOperand(1), Addr, Offset);
532 const SDValue Ops[] = {
535 CurDAG->getTargetConstant(0, DL, MVT::i32),
538 return CurDAG->getMachineNode(AMDGPU::SI_RegisterLoad, DL,
539 CurDAG->getVTList(MVT::i32, MVT::i64,
543 case AMDGPUISD::REGISTER_STORE: {
544 if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
546 SDValue Addr, Offset;
547 SelectADDRIndirect(N->getOperand(2), Addr, Offset);
549 const SDValue Ops[] = {
553 CurDAG->getTargetConstant(0, DL, MVT::i32),
556 return CurDAG->getMachineNode(AMDGPU::SI_RegisterStorePseudo, DL,
557 CurDAG->getVTList(MVT::Other),
561 case AMDGPUISD::BFE_I32:
562 case AMDGPUISD::BFE_U32: {
563 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
566 // There is a scalar version available, but unlike the vector version which
567 // has a separate operand for the offset and width, the scalar version packs
568 // the width and offset into a single operand. Try to move to the scalar
569 // version if the offsets are constant, so that we can try to keep extended
570 // loads of kernel arguments in SGPRs.
572 // TODO: Technically we could try to pattern match scalar bitshifts of
573 // dynamic values, but it's probably not useful.
574 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
578 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
582 bool Signed = Opc == AMDGPUISD::BFE_I32;
584 uint32_t OffsetVal = Offset->getZExtValue();
585 uint32_t WidthVal = Width->getZExtValue();
587 return getS_BFE(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32, SDLoc(N),
588 N->getOperand(0), OffsetVal, WidthVal);
590 case AMDGPUISD::DIV_SCALE: {
591 return SelectDIV_SCALE(N);
593 case ISD::CopyToReg: {
594 const SITargetLowering& Lowering =
595 *static_cast<const SITargetLowering*>(getTargetLowering());
596 Lowering.legalizeTargetIndependentNode(N, *CurDAG);
599 case ISD::ADDRSPACECAST:
600 return SelectAddrSpaceCast(N);
604 if (N->getValueType(0) != MVT::i32 ||
605 Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
608 return SelectS_BFE(N);
611 return SelectCode(N);
614 bool AMDGPUDAGToDAGISel::checkType(const Value *Ptr, unsigned AS) {
615 assert(AS != 0 && "Use checkPrivateAddress instead.");
619 return Ptr->getType()->getPointerAddressSpace() == AS;
622 bool AMDGPUDAGToDAGISel::checkPrivateAddress(const MachineMemOperand *Op) {
623 if (Op->getPseudoValue())
626 if (PointerType *PT = dyn_cast<PointerType>(Op->getValue()->getType()))
627 return PT->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
632 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
633 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
636 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
637 const Value *MemVal = N->getMemOperand()->getValue();
638 return (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
639 !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
640 !checkType(MemVal, AMDGPUAS::REGION_ADDRESS));
643 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
644 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
647 bool AMDGPUDAGToDAGISel::isFlatStore(const StoreSDNode *N) {
648 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
651 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
652 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
655 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int CbId) const {
656 const Value *MemVal = N->getMemOperand()->getValue();
658 return checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS);
660 return checkType(MemVal, AMDGPUAS::CONSTANT_BUFFER_0 + CbId);
663 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const {
664 if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS)
665 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
666 N->getMemoryVT().bitsLT(MVT::i32))
669 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
672 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) const {
673 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::PARAM_I_ADDRESS);
676 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) const {
677 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
680 bool AMDGPUDAGToDAGISel::isFlatLoad(const LoadSDNode *N) const {
681 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
684 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) const {
685 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
688 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) const {
689 MachineMemOperand *MMO = N->getMemOperand();
690 if (checkPrivateAddress(N->getMemOperand())) {
692 const PseudoSourceValue *PSV = MMO->getPseudoValue();
693 if (PSV && PSV->isConstantPool()) {
701 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
702 if (checkPrivateAddress(N->getMemOperand())) {
703 // Check to make sure we are not a constant pool load or a constant load
704 // that is marked as a private load
705 if (isCPLoad(N) || isConstantLoad(N, -1)) {
710 const Value *MemVal = N->getMemOperand()->getValue();
711 if (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
712 !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
713 !checkType(MemVal, AMDGPUAS::FLAT_ADDRESS) &&
714 !checkType(MemVal, AMDGPUAS::REGION_ADDRESS) &&
715 !checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS) &&
716 !checkType(MemVal, AMDGPUAS::PARAM_D_ADDRESS) &&
717 !checkType(MemVal, AMDGPUAS::PARAM_I_ADDRESS)) {
723 const char *AMDGPUDAGToDAGISel::getPassName() const {
724 return "AMDGPU DAG->DAG Pattern Instruction Selection";
732 //===----------------------------------------------------------------------===//
734 //===----------------------------------------------------------------------===//
736 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
738 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
739 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, SDLoc(Addr),
746 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
747 SDValue& BaseReg, SDValue &Offset) {
748 if (!isa<ConstantSDNode>(Addr)) {
750 Offset = CurDAG->getIntPtrConstant(0, SDLoc(Addr), true);
756 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
758 ConstantSDNode *IMMOffset;
760 if (Addr.getOpcode() == ISD::ADD
761 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
762 && isInt<16>(IMMOffset->getZExtValue())) {
764 Base = Addr.getOperand(0);
765 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
768 // If the pointer address is constant, we can move it to the offset field.
769 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
770 && isInt<16>(IMMOffset->getZExtValue())) {
771 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
772 SDLoc(CurDAG->getEntryNode()),
773 AMDGPU::ZERO, MVT::i32);
774 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
779 // Default case, no offset
781 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
785 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
790 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
791 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
792 Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
793 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
794 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
795 Base = Addr.getOperand(0);
796 Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
799 Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
805 SDNode *AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
807 SDValue LHS = N->getOperand(0);
808 SDValue RHS = N->getOperand(1);
810 bool IsAdd = (N->getOpcode() == ISD::ADD);
812 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
813 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
815 SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
816 DL, MVT::i32, LHS, Sub0);
817 SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
818 DL, MVT::i32, LHS, Sub1);
820 SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
821 DL, MVT::i32, RHS, Sub0);
822 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
823 DL, MVT::i32, RHS, Sub1);
825 SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
826 SDValue AddLoArgs[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) };
829 unsigned Opc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
830 unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
832 SDNode *AddLo = CurDAG->getMachineNode( Opc, DL, VTList, AddLoArgs);
833 SDValue Carry(AddLo, 1);
835 = CurDAG->getMachineNode(CarryOpc, DL, MVT::i32,
836 SDValue(Hi0, 0), SDValue(Hi1, 0), Carry);
839 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
845 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args);
848 // We need to handle this here because tablegen doesn't support matching
849 // instructions with multiple outputs.
850 SDNode *AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
852 EVT VT = N->getValueType(0);
854 assert(VT == MVT::f32 || VT == MVT::f64);
857 = (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64 : AMDGPU::V_DIV_SCALE_F32;
859 // src0_modifiers, src0, src1_modifiers, src1, src2_modifiers, src2, clamp,
863 SelectVOP3Mods0(N->getOperand(0), Ops[1], Ops[0], Ops[6], Ops[7]);
864 SelectVOP3Mods(N->getOperand(1), Ops[3], Ops[2]);
865 SelectVOP3Mods(N->getOperand(2), Ops[5], Ops[4]);
866 return CurDAG->SelectNodeTo(N, Opc, VT, MVT::i1, Ops);
869 bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset,
870 unsigned OffsetBits) const {
871 if ((OffsetBits == 16 && !isUInt<16>(Offset)) ||
872 (OffsetBits == 8 && !isUInt<8>(Offset)))
875 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS ||
876 Subtarget->unsafeDSOffsetFoldingEnabled())
879 // On Southern Islands instruction with a negative base value and an offset
880 // don't seem to work.
881 return CurDAG->SignBitIsZero(Base);
884 bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
885 SDValue &Offset) const {
886 if (CurDAG->isBaseWithConstantOffset(Addr)) {
887 SDValue N0 = Addr.getOperand(0);
888 SDValue N1 = Addr.getOperand(1);
889 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
890 if (isDSOffsetLegal(N0, C1->getSExtValue(), 16)) {
896 } else if (Addr.getOpcode() == ISD::SUB) {
897 // sub C, x -> add (sub 0, x), C
898 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
899 int64_t ByteOffset = C->getSExtValue();
900 if (isUInt<16>(ByteOffset)) {
902 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
904 // XXX - This is kind of hacky. Create a dummy sub node so we can check
905 // the known bits in isDSOffsetLegal. We need to emit the selected node
906 // here, so this is thrown away.
907 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
908 Zero, Addr.getOperand(1));
910 if (isDSOffsetLegal(Sub, ByteOffset, 16)) {
911 MachineSDNode *MachineSub
912 = CurDAG->getMachineNode(AMDGPU::V_SUB_I32_e32, DL, MVT::i32,
913 Zero, Addr.getOperand(1));
915 Base = SDValue(MachineSub, 0);
916 Offset = Addr.getOperand(0);
921 } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
922 // If we have a constant address, prefer to put the constant into the
923 // offset. This can save moves to load the constant address since multiple
924 // operations can share the zero base address register, and enables merging
925 // into read2 / write2 instructions.
929 if (isUInt<16>(CAddr->getZExtValue())) {
930 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
931 MachineSDNode *MovZero = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
933 Base = SDValue(MovZero, 0);
941 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i16);
945 // TODO: If offset is too big, put low 16-bit into offset.
946 bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
948 SDValue &Offset1) const {
951 if (CurDAG->isBaseWithConstantOffset(Addr)) {
952 SDValue N0 = Addr.getOperand(0);
953 SDValue N1 = Addr.getOperand(1);
954 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
955 unsigned DWordOffset0 = C1->getZExtValue() / 4;
956 unsigned DWordOffset1 = DWordOffset0 + 1;
958 if (isDSOffsetLegal(N0, DWordOffset1, 8)) {
960 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
961 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
964 } else if (Addr.getOpcode() == ISD::SUB) {
965 // sub C, x -> add (sub 0, x), C
966 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
967 unsigned DWordOffset0 = C->getZExtValue() / 4;
968 unsigned DWordOffset1 = DWordOffset0 + 1;
970 if (isUInt<8>(DWordOffset0)) {
972 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
974 // XXX - This is kind of hacky. Create a dummy sub node so we can check
975 // the known bits in isDSOffsetLegal. We need to emit the selected node
976 // here, so this is thrown away.
977 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
978 Zero, Addr.getOperand(1));
980 if (isDSOffsetLegal(Sub, DWordOffset1, 8)) {
981 MachineSDNode *MachineSub
982 = CurDAG->getMachineNode(AMDGPU::V_SUB_I32_e32, DL, MVT::i32,
983 Zero, Addr.getOperand(1));
985 Base = SDValue(MachineSub, 0);
986 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
987 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
992 } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
993 unsigned DWordOffset0 = CAddr->getZExtValue() / 4;
994 unsigned DWordOffset1 = DWordOffset0 + 1;
995 assert(4 * DWordOffset0 == CAddr->getZExtValue());
997 if (isUInt<8>(DWordOffset0) && isUInt<8>(DWordOffset1)) {
998 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
999 MachineSDNode *MovZero
1000 = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
1001 DL, MVT::i32, Zero);
1002 Base = SDValue(MovZero, 0);
1003 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
1004 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8);
1011 Offset0 = CurDAG->getTargetConstant(0, DL, MVT::i8);
1012 Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i8);
1016 static bool isLegalMUBUFImmOffset(const ConstantSDNode *Imm) {
1017 return isUInt<12>(Imm->getZExtValue());
1020 void AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
1021 SDValue &VAddr, SDValue &SOffset,
1022 SDValue &Offset, SDValue &Offen,
1023 SDValue &Idxen, SDValue &Addr64,
1024 SDValue &GLC, SDValue &SLC,
1025 SDValue &TFE) const {
1028 GLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
1029 SLC = CurDAG->getTargetConstant(0, DL, MVT::i1);
1030 TFE = CurDAG->getTargetConstant(0, DL, MVT::i1);
1032 Idxen = CurDAG->getTargetConstant(0, DL, MVT::i1);
1033 Offen = CurDAG->getTargetConstant(0, DL, MVT::i1);
1034 Addr64 = CurDAG->getTargetConstant(0, DL, MVT::i1);
1035 SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);
1037 if (CurDAG->isBaseWithConstantOffset(Addr)) {
1038 SDValue N0 = Addr.getOperand(0);
1039 SDValue N1 = Addr.getOperand(1);
1040 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
1042 if (N0.getOpcode() == ISD::ADD) {
1043 // (add (add N2, N3), C1) -> addr64
1044 SDValue N2 = N0.getOperand(0);
1045 SDValue N3 = N0.getOperand(1);
1046 Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
1051 // (add N0, C1) -> offset
1052 VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
1056 if (isLegalMUBUFImmOffset(C1)) {
1057 Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
1059 } else if (isUInt<32>(C1->getZExtValue())) {
1060 // Illegal offset, store it in soffset.
1061 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1062 SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
1063 CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32)),
1069 if (Addr.getOpcode() == ISD::ADD) {
1070 // (add N0, N1) -> addr64
1071 SDValue N0 = Addr.getOperand(0);
1072 SDValue N1 = Addr.getOperand(1);
1073 Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
1076 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1080 // default case -> offset
1081 VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
1083 Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1086 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
1087 SDValue &VAddr, SDValue &SOffset,
1088 SDValue &Offset, SDValue &GLC,
1089 SDValue &SLC, SDValue &TFE) const {
1090 SDValue Ptr, Offen, Idxen, Addr64;
1092 // addr64 bit was removed for volcanic islands.
1093 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1096 SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
1099 ConstantSDNode *C = cast<ConstantSDNode>(Addr64);
1100 if (C->getSExtValue()) {
1103 const SITargetLowering& Lowering =
1104 *static_cast<const SITargetLowering*>(getTargetLowering());
1106 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0);
1113 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
1114 SDValue &VAddr, SDValue &SOffset,
1116 SDValue &SLC) const {
1117 SLC = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i1);
1120 return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset, GLC, SLC, TFE);
1123 bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
1124 SDValue &VAddr, SDValue &SOffset,
1125 SDValue &ImmOffset) const {
1128 MachineFunction &MF = CurDAG->getMachineFunction();
1129 const SIRegisterInfo *TRI =
1130 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
1131 MachineRegisterInfo &MRI = MF.getRegInfo();
1132 const SITargetLowering& Lowering =
1133 *static_cast<const SITargetLowering*>(getTargetLowering());
1135 unsigned ScratchOffsetReg =
1136 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET);
1137 Lowering.CreateLiveInRegister(*CurDAG, &AMDGPU::SReg_32RegClass,
1138 ScratchOffsetReg, MVT::i32);
1139 SDValue Sym0 = CurDAG->getExternalSymbol("SCRATCH_RSRC_DWORD0", MVT::i32);
1140 SDValue ScratchRsrcDword0 =
1141 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, Sym0), 0);
1143 SDValue Sym1 = CurDAG->getExternalSymbol("SCRATCH_RSRC_DWORD1", MVT::i32);
1144 SDValue ScratchRsrcDword1 =
1145 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, Sym1), 0);
1147 const SDValue RsrcOps[] = {
1148 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
1150 CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
1152 CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32),
1154 SDValue ScratchPtr = SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
1155 MVT::v2i32, RsrcOps), 0);
1156 Rsrc = SDValue(Lowering.buildScratchRSRC(*CurDAG, DL, ScratchPtr), 0);
1157 SOffset = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
1158 MRI.getLiveInVirtReg(ScratchOffsetReg), MVT::i32);
1161 if (CurDAG->isBaseWithConstantOffset(Addr)) {
1162 SDValue N0 = Addr.getOperand(0);
1163 SDValue N1 = Addr.getOperand(1);
1164 // Offsets in vaddr must be positive.
1165 if (CurDAG->SignBitIsZero(N0)) {
1166 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
1167 if (isLegalMUBUFImmOffset(C1)) {
1169 ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
1177 ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16);
1181 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1182 SDValue &SOffset, SDValue &Offset,
1183 SDValue &GLC, SDValue &SLC,
1184 SDValue &TFE) const {
1185 SDValue Ptr, VAddr, Offen, Idxen, Addr64;
1186 const SIInstrInfo *TII =
1187 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
1189 SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
1192 if (!cast<ConstantSDNode>(Offen)->getSExtValue() &&
1193 !cast<ConstantSDNode>(Idxen)->getSExtValue() &&
1194 !cast<ConstantSDNode>(Addr64)->getSExtValue()) {
1195 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() |
1196 APInt::getAllOnesValue(32).getZExtValue(); // Size
1199 const SITargetLowering& Lowering =
1200 *static_cast<const SITargetLowering*>(getTargetLowering());
1202 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0);
1208 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1209 SDValue &Soffset, SDValue &Offset,
1210 SDValue &GLC) const {
1213 return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
1217 /// \param EncodedOffset This is the immediate value that will be encoded
1218 /// directly into the instruction. On SI/CI the \p EncodedOffset
1219 /// will be in units of dwords and on VI+ it will be units of bytes.
1220 static bool isLegalSMRDImmOffset(const AMDGPUSubtarget *ST,
1221 int64_t EncodedOffset) {
1222 return ST->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS ?
1223 isUInt<8>(EncodedOffset) : isUInt<20>(EncodedOffset);
1226 bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
1227 SDValue &Offset, bool &Imm) const {
1229 // FIXME: Handle non-constant offsets.
1230 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ByteOffsetNode);
1234 SDLoc SL(ByteOffsetNode);
1235 AMDGPUSubtarget::Generation Gen = Subtarget->getGeneration();
1236 int64_t ByteOffset = C->getSExtValue();
1237 int64_t EncodedOffset = Gen < AMDGPUSubtarget::VOLCANIC_ISLANDS ?
1238 ByteOffset >> 2 : ByteOffset;
1240 if (isLegalSMRDImmOffset(Subtarget, EncodedOffset)) {
1241 Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
1246 if (!isUInt<32>(EncodedOffset) || !isUInt<32>(ByteOffset))
1249 if (Gen == AMDGPUSubtarget::SEA_ISLANDS && isUInt<32>(EncodedOffset)) {
1250 // 32-bit Immediates are supported on Sea Islands.
1251 Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
1253 SDValue C32Bit = CurDAG->getTargetConstant(ByteOffset, SL, MVT::i32);
1254 Offset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32,
1261 bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase,
1262 SDValue &Offset, bool &Imm) const {
1265 if (CurDAG->isBaseWithConstantOffset(Addr)) {
1266 SDValue N0 = Addr.getOperand(0);
1267 SDValue N1 = Addr.getOperand(1);
1269 if (SelectSMRDOffset(N1, Offset, Imm)) {
1275 Offset = CurDAG->getTargetConstant(0, SL, MVT::i32);
1280 bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase,
1281 SDValue &Offset) const {
1283 return SelectSMRD(Addr, SBase, Offset, Imm) && Imm;
1286 bool AMDGPUDAGToDAGISel::SelectSMRDImm32(SDValue Addr, SDValue &SBase,
1287 SDValue &Offset) const {
1289 if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS)
1293 if (!SelectSMRD(Addr, SBase, Offset, Imm))
1296 return !Imm && isa<ConstantSDNode>(Offset);
1299 bool AMDGPUDAGToDAGISel::SelectSMRDSgpr(SDValue Addr, SDValue &SBase,
1300 SDValue &Offset) const {
1302 return SelectSMRD(Addr, SBase, Offset, Imm) && !Imm &&
1303 !isa<ConstantSDNode>(Offset);
1306 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm(SDValue Addr,
1307 SDValue &Offset) const {
1309 return SelectSMRDOffset(Addr, Offset, Imm) && Imm;
1312 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm32(SDValue Addr,
1313 SDValue &Offset) const {
1314 if (Subtarget->getGeneration() != AMDGPUSubtarget::SEA_ISLANDS)
1318 if (!SelectSMRDOffset(Addr, Offset, Imm))
1321 return !Imm && isa<ConstantSDNode>(Offset);
1324 bool AMDGPUDAGToDAGISel::SelectSMRDBufferSgpr(SDValue Addr,
1325 SDValue &Offset) const {
1327 return SelectSMRDOffset(Addr, Offset, Imm) && !Imm &&
1328 !isa<ConstantSDNode>(Offset);
1331 // FIXME: This is incorrect and only enough to be able to compile.
1332 SDNode *AMDGPUDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
1333 AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(N);
1336 assert(Subtarget->hasFlatAddressSpace() &&
1337 "addrspacecast only supported with flat address space!");
1339 assert((ASC->getSrcAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS &&
1340 ASC->getDestAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS) &&
1341 "Cannot cast address space to / from constant address!");
1343 assert((ASC->getSrcAddressSpace() == AMDGPUAS::FLAT_ADDRESS ||
1344 ASC->getDestAddressSpace() == AMDGPUAS::FLAT_ADDRESS) &&
1345 "Can only cast to / from flat address space!");
1347 // The flat instructions read the address as the index of the VGPR holding the
1348 // address, so casting should just be reinterpreting the base VGPR, so just
1349 // insert trunc / bitcast / zext.
1351 SDValue Src = ASC->getOperand(0);
1352 EVT DestVT = ASC->getValueType(0);
1353 EVT SrcVT = Src.getValueType();
1355 unsigned SrcSize = SrcVT.getSizeInBits();
1356 unsigned DestSize = DestVT.getSizeInBits();
1358 if (SrcSize > DestSize) {
1359 assert(SrcSize == 64 && DestSize == 32);
1360 return CurDAG->getMachineNode(
1361 TargetOpcode::EXTRACT_SUBREG,
1365 CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32));
1368 if (DestSize > SrcSize) {
1369 assert(SrcSize == 32 && DestSize == 64);
1371 // FIXME: This is probably wrong, we should never be defining
1372 // a register class with both VGPRs and SGPRs
1373 SDValue RC = CurDAG->getTargetConstant(AMDGPU::VS_64RegClassID, DL,
1376 const SDValue Ops[] = {
1379 CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
1380 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
1381 CurDAG->getConstant(0, DL, MVT::i32)), 0),
1382 CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
1385 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
1386 DL, N->getValueType(0), Ops);
1389 assert(SrcSize == 64 && DestSize == 64);
1390 return CurDAG->getNode(ISD::BITCAST, DL, DestVT, Src).getNode();
1393 SDNode *AMDGPUDAGToDAGISel::getS_BFE(unsigned Opcode, SDLoc DL, SDValue Val,
1394 uint32_t Offset, uint32_t Width) {
1395 // Transformation function, pack the offset and width of a BFE into
1396 // the format expected by the S_BFE_I32 / S_BFE_U32. In the second
1397 // source, bits [5:0] contain the offset and bits [22:16] the width.
1398 uint32_t PackedVal = Offset | (Width << 16);
1399 SDValue PackedConst = CurDAG->getTargetConstant(PackedVal, DL, MVT::i32);
1401 return CurDAG->getMachineNode(Opcode, DL, MVT::i32, Val, PackedConst);
1404 SDNode *AMDGPUDAGToDAGISel::SelectS_BFEFromShifts(SDNode *N) {
1405 // "(a << b) srl c)" ---> "BFE_U32 a, (c-b), (32-c)
1406 // "(a << b) sra c)" ---> "BFE_I32 a, (c-b), (32-c)
1407 // Predicate: 0 < b <= c < 32
1409 const SDValue &Shl = N->getOperand(0);
1410 ConstantSDNode *B = dyn_cast<ConstantSDNode>(Shl->getOperand(1));
1411 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
1414 uint32_t BVal = B->getZExtValue();
1415 uint32_t CVal = C->getZExtValue();
1417 if (0 < BVal && BVal <= CVal && CVal < 32) {
1418 bool Signed = N->getOpcode() == ISD::SRA;
1419 unsigned Opcode = Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32;
1421 return getS_BFE(Opcode, SDLoc(N), Shl.getOperand(0),
1422 CVal - BVal, 32 - CVal);
1425 return SelectCode(N);
1428 SDNode *AMDGPUDAGToDAGISel::SelectS_BFE(SDNode *N) {
1429 switch (N->getOpcode()) {
1431 if (N->getOperand(0).getOpcode() == ISD::SRL) {
1432 // "(a srl b) & mask" ---> "BFE_U32 a, b, popcount(mask)"
1433 // Predicate: isMask(mask)
1434 const SDValue &Srl = N->getOperand(0);
1435 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1));
1436 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));
1438 if (Shift && Mask) {
1439 uint32_t ShiftVal = Shift->getZExtValue();
1440 uint32_t MaskVal = Mask->getZExtValue();
1442 if (isMask_32(MaskVal)) {
1443 uint32_t WidthVal = countPopulation(MaskVal);
1445 return getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N), Srl.getOperand(0),
1446 ShiftVal, WidthVal);
1452 if (N->getOperand(0).getOpcode() == ISD::AND) {
1453 // "(a & mask) srl b)" ---> "BFE_U32 a, b, popcount(mask >> b)"
1454 // Predicate: isMask(mask >> b)
1455 const SDValue &And = N->getOperand(0);
1456 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(N->getOperand(1));
1457 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(And->getOperand(1));
1459 if (Shift && Mask) {
1460 uint32_t ShiftVal = Shift->getZExtValue();
1461 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal;
1463 if (isMask_32(MaskVal)) {
1464 uint32_t WidthVal = countPopulation(MaskVal);
1466 return getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N), And.getOperand(0),
1467 ShiftVal, WidthVal);
1470 } else if (N->getOperand(0).getOpcode() == ISD::SHL)
1471 return SelectS_BFEFromShifts(N);
1474 if (N->getOperand(0).getOpcode() == ISD::SHL)
1475 return SelectS_BFEFromShifts(N);
1479 return SelectCode(N);
1482 bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
1483 SDValue &SrcMods) const {
1489 if (Src.getOpcode() == ISD::FNEG) {
1490 Mods |= SISrcMods::NEG;
1491 Src = Src.getOperand(0);
1494 if (Src.getOpcode() == ISD::FABS) {
1495 Mods |= SISrcMods::ABS;
1496 Src = Src.getOperand(0);
1499 SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
1504 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods(SDValue In, SDValue &Src,
1505 SDValue &SrcMods) const {
1506 bool Res = SelectVOP3Mods(In, Src, SrcMods);
1507 return Res && cast<ConstantSDNode>(SrcMods)->isNullValue();
1510 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
1511 SDValue &SrcMods, SDValue &Clamp,
1512 SDValue &Omod) const {
1514 // FIXME: Handle Clamp and Omod
1515 Clamp = CurDAG->getTargetConstant(0, DL, MVT::i32);
1516 Omod = CurDAG->getTargetConstant(0, DL, MVT::i32);
1518 return SelectVOP3Mods(In, Src, SrcMods);
1521 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods0(SDValue In, SDValue &Src,
1522 SDValue &SrcMods, SDValue &Clamp,
1523 SDValue &Omod) const {
1524 bool Res = SelectVOP3Mods0(In, Src, SrcMods, Clamp, Omod);
1526 return Res && cast<ConstantSDNode>(SrcMods)->isNullValue() &&
1527 cast<ConstantSDNode>(Clamp)->isNullValue() &&
1528 cast<ConstantSDNode>(Omod)->isNullValue();
1531 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp(SDValue In, SDValue &Src,
1533 SDValue &Omod) const {
1534 // FIXME: Handle Omod
1535 Omod = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
1537 return SelectVOP3Mods(In, Src, SrcMods);
1540 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src,
1543 SDValue &Omod) const {
1544 Clamp = Omod = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
1545 return SelectVOP3Mods(In, Src, SrcMods);
1548 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
1549 const AMDGPUTargetLowering& Lowering =
1550 *static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
1551 bool IsModified = false;
1554 // Go over all selected nodes and try to fold them a bit more
1555 for (SDNode &Node : CurDAG->allnodes()) {
1556 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(&Node);
1560 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
1561 if (ResNode != &Node) {
1562 ReplaceUses(&Node, ResNode);
1566 CurDAG->RemoveDeadNodes();
1567 } while (IsModified);