1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
40 const Twine &Description;
45 static int getKindID() {
47 KindID = llvm::getNextAvailablePluginDiagnosticKind();
52 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53 DiagnosticSeverity Severity = DS_Error)
54 : DiagnosticInfo(getKindID(), Severity),
58 const Function &getFunction() const { return Fn; }
59 const Twine &getDescription() const { return Description; }
61 void print(DiagnosticPrinter &DP) const override {
62 DP << "unsupported " << getDescription() << " in " << Fn.getName();
65 static bool classof(const DiagnosticInfo *DI) {
66 return DI->getKind() == getKindID();
70 int DiagnosticInfoUnsupported::KindID = 0;
74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75 CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State) {
77 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78 ArgFlags.getOrigAlign());
79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
84 #include "AMDGPUGenCallingConv.inc"
86 // Find a larger type to do a load / store of a vector with.
87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88 unsigned StoreSize = VT.getStoreSizeInBits();
90 return EVT::getIntegerVT(Ctx, StoreSize);
92 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
96 // Type for a vector that will be loaded to.
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98 unsigned StoreSize = VT.getStoreSizeInBits();
100 return EVT::getIntegerVT(Ctx, 32);
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
106 const AMDGPUSubtarget &STI)
107 : TargetLowering(TM), Subtarget(&STI) {
108 setOperationAction(ISD::Constant, MVT::i32, Legal);
109 setOperationAction(ISD::Constant, MVT::i64, Legal);
110 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
111 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
113 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
114 setOperationAction(ISD::BRIND, MVT::Other, Expand);
116 // This is totally unsupported, just custom lower to produce an error.
117 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
119 // We need to custom lower some of the intrinsics
120 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
122 // Library functions. These default to Expand, but we have instructions
124 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
125 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
126 setOperationAction(ISD::FPOW, MVT::f32, Legal);
127 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
128 setOperationAction(ISD::FABS, MVT::f32, Legal);
129 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
130 setOperationAction(ISD::FRINT, MVT::f32, Legal);
131 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
132 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
133 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
135 setOperationAction(ISD::FROUND, MVT::f32, Custom);
136 setOperationAction(ISD::FROUND, MVT::f64, Custom);
138 setOperationAction(ISD::FREM, MVT::f32, Custom);
139 setOperationAction(ISD::FREM, MVT::f64, Custom);
141 // v_mad_f32 does not support denormals according to some sources.
142 if (!Subtarget->hasFP32Denormals())
143 setOperationAction(ISD::FMAD, MVT::f32, Legal);
145 // Expand to fneg + fadd.
146 setOperationAction(ISD::FSUB, MVT::f64, Expand);
148 // Lower floating point store/load to integer store/load to reduce the number
149 // of patterns in tablegen.
150 setOperationAction(ISD::STORE, MVT::f32, Promote);
151 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
153 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
154 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
156 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
157 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
159 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
160 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
162 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
163 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
165 setOperationAction(ISD::STORE, MVT::f64, Promote);
166 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
168 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
169 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
171 // Custom lowering of vector stores is required for local address space
173 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
175 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
176 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
177 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
179 // XXX: This can be change to Custom, once ExpandVectorStores can
180 // handle 64-bit stores.
181 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
183 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
184 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
185 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
186 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
187 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
190 setOperationAction(ISD::LOAD, MVT::f32, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
193 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
196 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
197 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
199 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
200 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
202 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
203 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
205 setOperationAction(ISD::LOAD, MVT::f64, Promote);
206 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
208 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
209 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
211 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
212 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
213 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
214 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
216 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
217 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
218 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
219 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
220 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
222 // There are no 64-bit extloads. These should be done as a 32-bit extload and
223 // an extension to 64-bit.
224 for (MVT VT : MVT::integer_valuetypes()) {
225 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
226 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
227 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
230 for (MVT VT : MVT::integer_vector_valuetypes()) {
231 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
232 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
233 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
234 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
235 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
236 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
237 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
238 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
239 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
240 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
241 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
242 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
245 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
247 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
248 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
249 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
250 setOperationAction(ISD::FRINT, MVT::f64, Custom);
251 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
254 if (!Subtarget->hasBFI()) {
255 // fcopysign can be done in a single instruction with BFI.
256 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
257 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
260 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
262 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
263 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
264 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
265 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand);
267 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
268 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
269 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
270 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand);
272 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
273 setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand);
274 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
275 setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand);
277 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
278 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
280 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
281 for (MVT VT : ScalarIntVTs) {
282 setOperationAction(ISD::SREM, VT, Expand);
283 setOperationAction(ISD::SDIV, VT, Expand);
285 // GPU does not have divrem function for signed or unsigned.
286 setOperationAction(ISD::SDIVREM, VT, Custom);
287 setOperationAction(ISD::UDIVREM, VT, Custom);
289 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
290 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
291 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
293 setOperationAction(ISD::BSWAP, VT, Expand);
294 setOperationAction(ISD::CTTZ, VT, Expand);
295 setOperationAction(ISD::CTLZ, VT, Expand);
298 if (!Subtarget->hasBCNT(32))
299 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
301 if (!Subtarget->hasBCNT(64))
302 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
304 // The hardware supports 32-bit ROTR, but not ROTL.
305 setOperationAction(ISD::ROTL, MVT::i32, Expand);
306 setOperationAction(ISD::ROTL, MVT::i64, Expand);
307 setOperationAction(ISD::ROTR, MVT::i64, Expand);
309 setOperationAction(ISD::MUL, MVT::i64, Expand);
310 setOperationAction(ISD::MULHU, MVT::i64, Expand);
311 setOperationAction(ISD::MULHS, MVT::i64, Expand);
312 setOperationAction(ISD::UDIV, MVT::i32, Expand);
313 setOperationAction(ISD::UREM, MVT::i32, Expand);
314 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
315 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
316 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
317 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
318 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
320 setOperationAction(ISD::SMIN, MVT::i32, Legal);
321 setOperationAction(ISD::UMIN, MVT::i32, Legal);
322 setOperationAction(ISD::SMAX, MVT::i32, Legal);
323 setOperationAction(ISD::UMAX, MVT::i32, Legal);
325 if (!Subtarget->hasFFBH())
326 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
328 if (!Subtarget->hasFFBL())
329 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
331 static const MVT::SimpleValueType VectorIntTypes[] = {
332 MVT::v2i32, MVT::v4i32
335 for (MVT VT : VectorIntTypes) {
336 // Expand the following operations for the current type by default.
337 setOperationAction(ISD::ADD, VT, Expand);
338 setOperationAction(ISD::AND, VT, Expand);
339 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
340 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
341 setOperationAction(ISD::MUL, VT, Expand);
342 setOperationAction(ISD::OR, VT, Expand);
343 setOperationAction(ISD::SHL, VT, Expand);
344 setOperationAction(ISD::SRA, VT, Expand);
345 setOperationAction(ISD::SRL, VT, Expand);
346 setOperationAction(ISD::ROTL, VT, Expand);
347 setOperationAction(ISD::ROTR, VT, Expand);
348 setOperationAction(ISD::SUB, VT, Expand);
349 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
350 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
351 setOperationAction(ISD::SDIV, VT, Expand);
352 setOperationAction(ISD::UDIV, VT, Expand);
353 setOperationAction(ISD::SREM, VT, Expand);
354 setOperationAction(ISD::UREM, VT, Expand);
355 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
356 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
357 setOperationAction(ISD::SDIVREM, VT, Custom);
358 setOperationAction(ISD::UDIVREM, VT, Custom);
359 setOperationAction(ISD::ADDC, VT, Expand);
360 setOperationAction(ISD::SUBC, VT, Expand);
361 setOperationAction(ISD::ADDE, VT, Expand);
362 setOperationAction(ISD::SUBE, VT, Expand);
363 setOperationAction(ISD::SELECT, VT, Expand);
364 setOperationAction(ISD::VSELECT, VT, Expand);
365 setOperationAction(ISD::SELECT_CC, VT, Expand);
366 setOperationAction(ISD::XOR, VT, Expand);
367 setOperationAction(ISD::BSWAP, VT, Expand);
368 setOperationAction(ISD::CTPOP, VT, Expand);
369 setOperationAction(ISD::CTTZ, VT, Expand);
370 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
371 setOperationAction(ISD::CTLZ, VT, Expand);
372 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
373 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
376 static const MVT::SimpleValueType FloatVectorTypes[] = {
377 MVT::v2f32, MVT::v4f32
380 for (MVT VT : FloatVectorTypes) {
381 setOperationAction(ISD::FABS, VT, Expand);
382 setOperationAction(ISD::FMINNUM, VT, Expand);
383 setOperationAction(ISD::FMAXNUM, VT, Expand);
384 setOperationAction(ISD::FADD, VT, Expand);
385 setOperationAction(ISD::FCEIL, VT, Expand);
386 setOperationAction(ISD::FCOS, VT, Expand);
387 setOperationAction(ISD::FDIV, VT, Expand);
388 setOperationAction(ISD::FEXP2, VT, Expand);
389 setOperationAction(ISD::FLOG2, VT, Expand);
390 setOperationAction(ISD::FREM, VT, Expand);
391 setOperationAction(ISD::FPOW, VT, Expand);
392 setOperationAction(ISD::FFLOOR, VT, Expand);
393 setOperationAction(ISD::FTRUNC, VT, Expand);
394 setOperationAction(ISD::FMUL, VT, Expand);
395 setOperationAction(ISD::FMA, VT, Expand);
396 setOperationAction(ISD::FRINT, VT, Expand);
397 setOperationAction(ISD::FNEARBYINT, VT, Expand);
398 setOperationAction(ISD::FSQRT, VT, Expand);
399 setOperationAction(ISD::FSIN, VT, Expand);
400 setOperationAction(ISD::FSUB, VT, Expand);
401 setOperationAction(ISD::FNEG, VT, Expand);
402 setOperationAction(ISD::SELECT, VT, Expand);
403 setOperationAction(ISD::VSELECT, VT, Expand);
404 setOperationAction(ISD::SELECT_CC, VT, Expand);
405 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
406 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
409 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
410 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
412 setTargetDAGCombine(ISD::SHL);
413 setTargetDAGCombine(ISD::MUL);
414 setTargetDAGCombine(ISD::SELECT);
415 setTargetDAGCombine(ISD::SELECT_CC);
416 setTargetDAGCombine(ISD::STORE);
418 setTargetDAGCombine(ISD::FADD);
419 setTargetDAGCombine(ISD::FSUB);
421 setBooleanContents(ZeroOrNegativeOneBooleanContent);
422 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
424 setSchedulingPreference(Sched::RegPressure);
425 setJumpIsExpensive(true);
427 // SI at least has hardware support for floating point exceptions, but no way
428 // of using or handling them is implemented. They are also optional in OpenCL
430 setHasFloatingPointExceptions(false);
432 setSelectIsExpensive(false);
433 PredictableSelectIsExpensive = false;
435 setFsqrtIsCheap(true);
437 // FIXME: Need to really handle these.
438 MaxStoresPerMemcpy = 4096;
439 MaxStoresPerMemmove = 4096;
440 MaxStoresPerMemset = 4096;
443 //===----------------------------------------------------------------------===//
444 // Target Information
445 //===----------------------------------------------------------------------===//
447 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
451 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
455 // The backend supports 32 and 64 bit floating point immediates.
456 // FIXME: Why are we reporting vectors of FP immediates as legal?
457 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
458 EVT ScalarVT = VT.getScalarType();
459 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
462 // We don't want to shrink f64 / f32 constants.
463 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
464 EVT ScalarVT = VT.getScalarType();
465 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
468 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
472 unsigned NewSize = NewVT.getStoreSizeInBits();
474 // If we are reducing to a 32-bit load, this is always better.
478 EVT OldVT = N->getValueType(0);
479 unsigned OldSize = OldVT.getStoreSizeInBits();
481 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
482 // extloads, so doing one requires using a buffer_load. In cases where we
483 // still couldn't use a scalar load, using the wider load shouldn't really
486 // If the old size already had to be an extload, there's no harm in continuing
487 // to reduce the width.
488 return (OldSize < 32);
491 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
493 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
496 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
497 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
499 return ((LScalarSize <= CastScalarSize) ||
500 (CastScalarSize >= 32) ||
504 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
505 // profitable with the expansion for 64-bit since it's generally good to
507 // FIXME: These should really have the size as a parameter.
508 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
512 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
516 //===---------------------------------------------------------------------===//
518 //===---------------------------------------------------------------------===//
520 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
521 assert(VT.isFloatingPoint());
522 return VT == MVT::f32 || VT == MVT::f64;
525 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
526 assert(VT.isFloatingPoint());
527 return VT == MVT::f32 || VT == MVT::f64;
530 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
536 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
537 // Truncate is just accessing a subregister.
538 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
541 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
542 // Truncate is just accessing a subregister.
543 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
544 (Dest->getPrimitiveSizeInBits() % 32 == 0);
547 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
548 unsigned SrcSize = Src->getScalarSizeInBits();
549 unsigned DestSize = Dest->getScalarSizeInBits();
551 return SrcSize == 32 && DestSize == 64;
554 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
555 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
556 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
557 // this will enable reducing 64-bit operations the 32-bit, which is always
559 return Src == MVT::i32 && Dest == MVT::i64;
562 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
563 return isZExtFree(Val.getValueType(), VT2);
566 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
567 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
568 // limited number of native 64-bit operations. Shrinking an operation to fit
569 // in a single 32-bit register should always be helpful. As currently used,
570 // this is much less general than the name suggests, and is only used in
571 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
572 // not profitable, and may actually be harmful.
573 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
576 //===---------------------------------------------------------------------===//
577 // TargetLowering Callbacks
578 //===---------------------------------------------------------------------===//
580 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
581 const SmallVectorImpl<ISD::InputArg> &Ins) const {
583 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
586 SDValue AMDGPUTargetLowering::LowerReturn(
588 CallingConv::ID CallConv,
590 const SmallVectorImpl<ISD::OutputArg> &Outs,
591 const SmallVectorImpl<SDValue> &OutVals,
592 SDLoc DL, SelectionDAG &DAG) const {
593 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
596 //===---------------------------------------------------------------------===//
597 // Target specific lowering
598 //===---------------------------------------------------------------------===//
600 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
601 SmallVectorImpl<SDValue> &InVals) const {
602 SDValue Callee = CLI.Callee;
603 SelectionDAG &DAG = CLI.DAG;
605 const Function &Fn = *DAG.getMachineFunction().getFunction();
607 StringRef FuncName("<unknown>");
609 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
610 FuncName = G->getSymbol();
611 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
612 FuncName = G->getGlobal()->getName();
614 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
615 DAG.getContext()->diagnose(NoCalls);
619 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
620 SelectionDAG &DAG) const {
621 const Function &Fn = *DAG.getMachineFunction().getFunction();
623 DiagnosticInfoUnsupported NoDynamicAlloca(Fn, "dynamic alloca");
624 DAG.getContext()->diagnose(NoDynamicAlloca);
628 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
629 SelectionDAG &DAG) const {
630 switch (Op.getOpcode()) {
632 Op.getNode()->dump();
633 llvm_unreachable("Custom lowering code for this"
634 "instruction is not implemented yet!");
636 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
637 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
638 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
639 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
640 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
641 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
642 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
643 case ISD::FREM: return LowerFREM(Op, DAG);
644 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
645 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
646 case ISD::FRINT: return LowerFRINT(Op, DAG);
647 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
648 case ISD::FROUND: return LowerFROUND(Op, DAG);
649 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
650 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
651 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
652 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
653 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
654 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
659 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
660 SmallVectorImpl<SDValue> &Results,
661 SelectionDAG &DAG) const {
662 switch (N->getOpcode()) {
663 case ISD::SIGN_EXTEND_INREG:
664 // Different parts of legalization seem to interpret which type of
665 // sign_extend_inreg is the one to check for custom lowering. The extended
666 // from type is what really matters, but some places check for custom
667 // lowering of the result type. This results in trying to use
668 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
669 // nothing here and let the illegal result integer be handled normally.
672 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
676 Results.push_back(SDValue(Node, 0));
677 Results.push_back(SDValue(Node, 1));
678 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
680 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
684 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
685 if (Lowered.getNode())
686 Results.push_back(Lowered);
694 // FIXME: This implements accesses to initialized globals in the constant
695 // address space by copying them to private and accessing that. It does not
696 // properly handle illegal types or vectors. The private vector loads are not
697 // scalarized, and the illegal scalars hit an assertion. This technique will not
698 // work well with large initializers, and this should eventually be
699 // removed. Initialized globals should be placed into a data section that the
700 // runtime will load into a buffer before the kernel is executed. Uses of the
701 // global need to be replaced with a pointer loaded from an implicit kernel
702 // argument into this buffer holding the copy of the data, which will remove the
703 // need for any of this.
704 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
705 const GlobalValue *GV,
706 const SDValue &InitPtr,
708 SelectionDAG &DAG) const {
709 const DataLayout &TD = DAG.getDataLayout();
711 Type *InitTy = Init->getType();
713 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
714 EVT VT = EVT::getEVT(InitTy);
715 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
716 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, DL, VT), InitPtr,
717 MachinePointerInfo(UndefValue::get(PtrTy)), false,
718 false, TD.getPrefTypeAlignment(InitTy));
721 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
722 EVT VT = EVT::getEVT(CFP->getType());
723 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
724 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, DL, VT), InitPtr,
725 MachinePointerInfo(UndefValue::get(PtrTy)), false,
726 false, TD.getPrefTypeAlignment(CFP->getType()));
729 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
730 const StructLayout *SL = TD.getStructLayout(ST);
732 EVT PtrVT = InitPtr.getValueType();
733 SmallVector<SDValue, 8> Chains;
735 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
736 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), DL, PtrVT);
737 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
739 Constant *Elt = Init->getAggregateElement(I);
740 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
743 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
746 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
747 EVT PtrVT = InitPtr.getValueType();
749 unsigned NumElements;
750 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
751 NumElements = AT->getNumElements();
752 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
753 NumElements = VT->getNumElements();
755 llvm_unreachable("Unexpected type");
757 unsigned EltSize = TD.getTypeAllocSize(SeqTy->getElementType());
758 SmallVector<SDValue, 8> Chains;
759 for (unsigned i = 0; i < NumElements; ++i) {
760 SDValue Offset = DAG.getConstant(i * EltSize, DL, PtrVT);
761 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
763 Constant *Elt = Init->getAggregateElement(i);
764 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
767 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
770 if (isa<UndefValue>(Init)) {
771 EVT VT = EVT::getEVT(InitTy);
772 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
773 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
774 MachinePointerInfo(UndefValue::get(PtrTy)), false,
775 false, TD.getPrefTypeAlignment(InitTy));
779 llvm_unreachable("Unhandled constant initializer");
782 static bool hasDefinedInitializer(const GlobalValue *GV) {
783 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
784 if (!GVar || !GVar->hasInitializer())
787 if (isa<UndefValue>(GVar->getInitializer()))
793 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
795 SelectionDAG &DAG) const {
797 const DataLayout &DL = DAG.getDataLayout();
798 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
799 const GlobalValue *GV = G->getGlobal();
801 switch (G->getAddressSpace()) {
802 case AMDGPUAS::LOCAL_ADDRESS: {
803 // XXX: What does the value of G->getOffset() mean?
804 assert(G->getOffset() == 0 &&
805 "Do not know what to do with an non-zero offset");
807 // TODO: We could emit code to handle the initialization somewhere.
808 if (hasDefinedInitializer(GV))
812 if (MFI->LocalMemoryObjects.count(GV) == 0) {
813 uint64_t Size = DL.getTypeAllocSize(GV->getType()->getElementType());
814 Offset = MFI->LDSSize;
815 MFI->LocalMemoryObjects[GV] = Offset;
816 // XXX: Account for alignment?
817 MFI->LDSSize += Size;
819 Offset = MFI->LocalMemoryObjects[GV];
822 return DAG.getConstant(Offset, SDLoc(Op),
823 getPointerTy(DL, AMDGPUAS::LOCAL_ADDRESS));
825 case AMDGPUAS::CONSTANT_ADDRESS: {
826 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
827 Type *EltType = GV->getType()->getElementType();
828 unsigned Size = DL.getTypeAllocSize(EltType);
829 unsigned Alignment = DL.getPrefTypeAlignment(EltType);
831 MVT PrivPtrVT = getPointerTy(DL, AMDGPUAS::PRIVATE_ADDRESS);
832 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
834 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
835 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
837 const GlobalVariable *Var = cast<GlobalVariable>(GV);
838 if (!Var->hasInitializer()) {
839 // This has no use, but bugpoint will hit it.
840 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
843 const Constant *Init = Var->getInitializer();
844 SmallVector<SDNode*, 8> WorkList;
846 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
847 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
848 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
850 WorkList.push_back(*I);
852 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
853 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
854 E = WorkList.end(); I != E; ++I) {
855 SmallVector<SDValue, 8> Ops;
856 Ops.push_back(Chain);
857 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
858 Ops.push_back((*I)->getOperand(i));
860 DAG.UpdateNodeOperands(*I, Ops);
862 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
866 const Function &Fn = *DAG.getMachineFunction().getFunction();
867 DiagnosticInfoUnsupported BadInit(Fn,
868 "initializer for address space");
869 DAG.getContext()->diagnose(BadInit);
873 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
874 SelectionDAG &DAG) const {
875 SmallVector<SDValue, 8> Args;
877 for (const SDUse &U : Op->ops())
878 DAG.ExtractVectorElements(U.get(), Args);
880 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
883 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
884 SelectionDAG &DAG) const {
886 SmallVector<SDValue, 8> Args;
887 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
888 EVT VT = Op.getValueType();
889 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
890 VT.getVectorNumElements());
892 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
895 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
896 SelectionDAG &DAG) const {
898 MachineFunction &MF = DAG.getMachineFunction();
899 const AMDGPUFrameLowering *TFL = Subtarget->getFrameLowering();
901 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
903 unsigned FrameIndex = FIN->getIndex();
904 unsigned IgnoredFrameReg;
906 TFL->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
907 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), SDLoc(Op),
911 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
912 SelectionDAG &DAG) const {
913 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
915 EVT VT = Op.getValueType();
917 switch (IntrinsicID) {
919 case AMDGPUIntrinsic::AMDGPU_abs:
920 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
921 return LowerIntrinsicIABS(Op, DAG);
922 case AMDGPUIntrinsic::AMDGPU_lrp:
923 return LowerIntrinsicLRP(Op, DAG);
925 case AMDGPUIntrinsic::AMDGPU_clamp:
926 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
927 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
928 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
930 case Intrinsic::AMDGPU_div_scale: {
931 // 3rd parameter required to be a constant.
932 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
934 return DAG.getUNDEF(VT);
936 // Translate to the operands expected by the machine instruction. The
937 // first parameter must be the same as the first instruction.
938 SDValue Numerator = Op.getOperand(1);
939 SDValue Denominator = Op.getOperand(2);
941 // Note this order is opposite of the machine instruction's operations,
942 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
943 // intrinsic has the numerator as the first operand to match a normal
944 // division operation.
946 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
948 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
949 Denominator, Numerator);
952 case Intrinsic::AMDGPU_div_fmas:
953 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
954 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
957 case Intrinsic::AMDGPU_div_fixup:
958 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
959 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
961 case Intrinsic::AMDGPU_trig_preop:
962 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
963 Op.getOperand(1), Op.getOperand(2));
965 case Intrinsic::AMDGPU_rcp:
966 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
968 case Intrinsic::AMDGPU_rsq:
969 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
971 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
972 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
974 case Intrinsic::AMDGPU_rsq_clamped:
975 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
976 Type *Type = VT.getTypeForEVT(*DAG.getContext());
977 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
978 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
980 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
981 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
982 DAG.getConstantFP(Max, DL, VT));
983 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
984 DAG.getConstantFP(Min, DL, VT));
986 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
989 case Intrinsic::AMDGPU_ldexp:
990 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
993 case AMDGPUIntrinsic::AMDGPU_imax:
994 return DAG.getNode(ISD::SMAX, DL, VT, Op.getOperand(1),
996 case AMDGPUIntrinsic::AMDGPU_umax:
997 return DAG.getNode(ISD::UMAX, DL, VT, Op.getOperand(1),
999 case AMDGPUIntrinsic::AMDGPU_imin:
1000 return DAG.getNode(ISD::SMIN, DL, VT, Op.getOperand(1),
1002 case AMDGPUIntrinsic::AMDGPU_umin:
1003 return DAG.getNode(ISD::UMIN, DL, VT, Op.getOperand(1),
1006 case AMDGPUIntrinsic::AMDGPU_umul24:
1007 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
1008 Op.getOperand(1), Op.getOperand(2));
1010 case AMDGPUIntrinsic::AMDGPU_imul24:
1011 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
1012 Op.getOperand(1), Op.getOperand(2));
1014 case AMDGPUIntrinsic::AMDGPU_umad24:
1015 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
1016 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
1018 case AMDGPUIntrinsic::AMDGPU_imad24:
1019 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
1020 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
1022 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
1023 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
1025 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
1026 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
1028 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
1029 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
1031 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
1032 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
1034 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
1035 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
1040 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
1041 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
1046 case AMDGPUIntrinsic::AMDGPU_bfi:
1047 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
1052 case AMDGPUIntrinsic::AMDGPU_bfm:
1053 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
1057 case AMDGPUIntrinsic::AMDGPU_brev:
1058 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
1060 case Intrinsic::AMDGPU_class:
1061 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
1062 Op.getOperand(1), Op.getOperand(2));
1064 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
1065 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
1067 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
1068 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
1069 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
1070 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
1074 ///IABS(a) = SMAX(sub(0, a), a)
1075 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
1076 SelectionDAG &DAG) const {
1078 EVT VT = Op.getValueType();
1079 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1082 return DAG.getNode(ISD::SMAX, DL, VT, Neg, Op.getOperand(1));
1085 /// Linear Interpolation
1086 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
1087 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
1088 SelectionDAG &DAG) const {
1090 EVT VT = Op.getValueType();
1091 // TODO: Should this propagate fast-math-flags?
1092 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
1093 DAG.getConstantFP(1.0f, DL, MVT::f32),
1095 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
1097 return DAG.getNode(ISD::FADD, DL, VT,
1098 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
1102 /// \brief Generate Min/Max node
1103 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,
1110 DAGCombinerInfo &DCI) const {
1111 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1114 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1117 SelectionDAG &DAG = DCI.DAG;
1118 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1127 case ISD::SETFALSE2:
1136 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1137 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1143 // Ordered. Assume ordered for undefined.
1145 // Only do this after legalization to avoid interfering with other combines
1146 // which might occur.
1147 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1148 !DCI.isCalledByLegalizer())
1151 // We need to permute the operands to get the correct NaN behavior. The
1152 // selected operand is the second one based on the failing compare with NaN,
1153 // so permute it based on the compare type the hardware uses.
1155 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1156 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1161 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1162 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1168 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1169 !DCI.isCalledByLegalizer())
1173 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1174 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1176 case ISD::SETCC_INVALID:
1177 llvm_unreachable("Invalid setcc condcode!");
1182 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1183 SelectionDAG &DAG) const {
1184 LoadSDNode *Load = cast<LoadSDNode>(Op);
1185 EVT MemVT = Load->getMemoryVT();
1186 EVT MemEltVT = MemVT.getVectorElementType();
1188 EVT LoadVT = Op.getValueType();
1189 EVT EltVT = LoadVT.getVectorElementType();
1190 EVT PtrVT = Load->getBasePtr().getValueType();
1192 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1193 SmallVector<SDValue, 8> Loads;
1194 SmallVector<SDValue, 8> Chains;
1197 unsigned MemEltSize = MemEltVT.getStoreSize();
1198 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1200 for (unsigned i = 0; i < NumElts; ++i) {
1201 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1202 DAG.getConstant(i * MemEltSize, SL, PtrVT));
1205 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1206 Load->getChain(), Ptr,
1207 SrcValue.getWithOffset(i * MemEltSize),
1208 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1209 Load->isInvariant(), Load->getAlignment());
1210 Loads.push_back(NewLoad.getValue(0));
1211 Chains.push_back(NewLoad.getValue(1));
1215 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1216 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1219 return DAG.getMergeValues(Ops, SL);
1222 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1223 SelectionDAG &DAG) const {
1224 EVT VT = Op.getValueType();
1226 // If this is a 2 element vector, we really want to scalarize and not create
1227 // weird 1 element vectors.
1228 if (VT.getVectorNumElements() == 2)
1229 return ScalarizeVectorLoad(Op, DAG);
1231 LoadSDNode *Load = cast<LoadSDNode>(Op);
1232 SDValue BasePtr = Load->getBasePtr();
1233 EVT PtrVT = BasePtr.getValueType();
1234 EVT MemVT = Load->getMemoryVT();
1236 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1239 EVT LoMemVT, HiMemVT;
1242 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1243 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1244 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1246 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1247 Load->getChain(), BasePtr,
1249 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1250 Load->isInvariant(), Load->getAlignment());
1252 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1253 DAG.getConstant(LoMemVT.getStoreSize(), SL,
1257 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1258 Load->getChain(), HiPtr,
1259 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1260 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1261 Load->isInvariant(), Load->getAlignment());
1264 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1265 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1266 LoLoad.getValue(1), HiLoad.getValue(1))
1269 return DAG.getMergeValues(Ops, SL);
1272 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1273 SelectionDAG &DAG) const {
1274 StoreSDNode *Store = cast<StoreSDNode>(Op);
1275 EVT MemVT = Store->getMemoryVT();
1276 unsigned MemBits = MemVT.getSizeInBits();
1278 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1279 // truncating store into an i32 store.
1280 // XXX: We could also handle optimize other vector bitwidths.
1281 if (!MemVT.isVector() || MemBits > 32) {
1286 SDValue Value = Store->getValue();
1287 EVT VT = Value.getValueType();
1288 EVT ElemVT = VT.getVectorElementType();
1289 SDValue Ptr = Store->getBasePtr();
1290 EVT MemEltVT = MemVT.getVectorElementType();
1291 unsigned MemEltBits = MemEltVT.getSizeInBits();
1292 unsigned MemNumElements = MemVT.getVectorNumElements();
1293 unsigned PackedSize = MemVT.getStoreSizeInBits();
1294 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, DL, MVT::i32);
1296 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1298 SDValue PackedValue;
1299 for (unsigned i = 0; i < MemNumElements; ++i) {
1300 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1301 DAG.getConstant(i, DL, MVT::i32));
1302 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1303 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1305 SDValue Shift = DAG.getConstant(MemEltBits * i, DL, MVT::i32);
1306 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1311 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1315 if (PackedSize < 32) {
1316 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1317 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1318 Store->getMemOperand()->getPointerInfo(),
1320 Store->isNonTemporal(), Store->isVolatile(),
1321 Store->getAlignment());
1324 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1325 Store->getMemOperand()->getPointerInfo(),
1326 Store->isVolatile(), Store->isNonTemporal(),
1327 Store->getAlignment());
1330 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1331 SelectionDAG &DAG) const {
1332 StoreSDNode *Store = cast<StoreSDNode>(Op);
1333 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1334 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1335 EVT PtrVT = Store->getBasePtr().getValueType();
1336 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1339 SmallVector<SDValue, 8> Chains;
1341 unsigned EltSize = MemEltVT.getStoreSize();
1342 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1344 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1345 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1347 DAG.getConstant(i, SL, MVT::i32));
1349 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), SL, PtrVT);
1350 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1352 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1353 SrcValue.getWithOffset(i * EltSize),
1354 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1355 Store->getAlignment());
1356 Chains.push_back(NewStore);
1359 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1362 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1363 SelectionDAG &DAG) const {
1364 StoreSDNode *Store = cast<StoreSDNode>(Op);
1365 SDValue Val = Store->getValue();
1366 EVT VT = Val.getValueType();
1368 // If this is a 2 element vector, we really want to scalarize and not create
1369 // weird 1 element vectors.
1370 if (VT.getVectorNumElements() == 2)
1371 return ScalarizeVectorStore(Op, DAG);
1373 EVT MemVT = Store->getMemoryVT();
1374 SDValue Chain = Store->getChain();
1375 SDValue BasePtr = Store->getBasePtr();
1379 EVT LoMemVT, HiMemVT;
1382 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1383 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1384 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1386 EVT PtrVT = BasePtr.getValueType();
1387 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1388 DAG.getConstant(LoMemVT.getStoreSize(), SL,
1391 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1393 = DAG.getTruncStore(Chain, SL, Lo,
1397 Store->isNonTemporal(),
1398 Store->isVolatile(),
1399 Store->getAlignment());
1401 = DAG.getTruncStore(Chain, SL, Hi,
1403 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1405 Store->isNonTemporal(),
1406 Store->isVolatile(),
1407 Store->getAlignment());
1409 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1413 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1415 LoadSDNode *Load = cast<LoadSDNode>(Op);
1416 ISD::LoadExtType ExtType = Load->getExtensionType();
1417 EVT VT = Op.getValueType();
1418 EVT MemVT = Load->getMemoryVT();
1420 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1421 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1422 // FIXME: Copied from PPC
1423 // First, load into 32 bits, then truncate to 1 bit.
1425 SDValue Chain = Load->getChain();
1426 SDValue BasePtr = Load->getBasePtr();
1427 MachineMemOperand *MMO = Load->getMemOperand();
1429 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1430 BasePtr, MVT::i8, MMO);
1433 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1437 return DAG.getMergeValues(Ops, DL);
1440 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1441 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1442 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1445 // <SI && AS=PRIVATE && EXTLOAD && size < 32bit,
1446 // register (2-)byte extract.
1448 // Get Register holding the target.
1449 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1450 DAG.getConstant(2, DL, MVT::i32));
1451 // Load the Register.
1452 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1453 Load->getChain(), Ptr,
1454 DAG.getTargetConstant(0, DL, MVT::i32),
1457 // Get offset within the register.
1458 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1460 DAG.getConstant(0x3, DL, MVT::i32));
1462 // Bit offset of target byte (byteIdx * 8).
1463 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1464 DAG.getConstant(3, DL, MVT::i32));
1466 // Shift to the right.
1467 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1469 // Eliminate the upper bits by setting them to ...
1470 EVT MemEltVT = MemVT.getScalarType();
1473 if (ExtType == ISD::SEXTLOAD) {
1474 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1477 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1481 return DAG.getMergeValues(Ops, DL);
1486 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1490 return DAG.getMergeValues(Ops, DL);
1493 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1495 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1496 if (Result.getNode()) {
1500 StoreSDNode *Store = cast<StoreSDNode>(Op);
1501 SDValue Chain = Store->getChain();
1502 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1503 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1504 Store->getValue().getValueType().isVector()) {
1505 return ScalarizeVectorStore(Op, DAG);
1508 EVT MemVT = Store->getMemoryVT();
1509 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1510 MemVT.bitsLT(MVT::i32)) {
1512 if (Store->getMemoryVT() == MVT::i8) {
1514 } else if (Store->getMemoryVT() == MVT::i16) {
1517 SDValue BasePtr = Store->getBasePtr();
1518 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1519 DAG.getConstant(2, DL, MVT::i32));
1520 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1522 DAG.getTargetConstant(0, DL, MVT::i32));
1524 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1525 DAG.getConstant(0x3, DL, MVT::i32));
1527 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1528 DAG.getConstant(3, DL, MVT::i32));
1530 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1533 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1535 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1536 MaskedValue, ShiftAmt);
1538 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32,
1539 DAG.getConstant(Mask, DL, MVT::i32),
1541 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1542 DAG.getConstant(0xffffffff, DL, MVT::i32));
1543 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1545 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1546 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1548 DAG.getTargetConstant(0, DL, MVT::i32));
1553 // This is a shortcut for integer division because we have fast i32<->f32
1554 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1555 // float is enough to accurately represent up to a 24-bit integer.
1556 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1558 EVT VT = Op.getValueType();
1559 SDValue LHS = Op.getOperand(0);
1560 SDValue RHS = Op.getOperand(1);
1561 MVT IntVT = MVT::i32;
1562 MVT FltVT = MVT::f32;
1564 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1565 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1567 if (VT.isVector()) {
1568 unsigned NElts = VT.getVectorNumElements();
1569 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1570 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1573 unsigned BitSize = VT.getScalarType().getSizeInBits();
1575 SDValue jq = DAG.getConstant(1, DL, IntVT);
1578 // char|short jq = ia ^ ib;
1579 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1581 // jq = jq >> (bitsize - 2)
1582 jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1583 DAG.getConstant(BitSize - 2, DL, VT));
1586 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1589 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1592 // int ia = (int)LHS;
1594 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1596 // int ib, (int)RHS;
1598 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1600 // float fa = (float)ia;
1601 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1603 // float fb = (float)ib;
1604 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1606 // TODO: Should this propagate fast-math-flags?
1607 // float fq = native_divide(fa, fb);
1608 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1609 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1612 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1614 // float fqneg = -fq;
1615 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1617 // float fr = mad(fqneg, fb, fa);
1618 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1619 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1621 // int iq = (int)fq;
1622 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1625 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1628 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1630 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1632 // int cv = fr >= fb;
1633 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1635 // jq = (cv ? jq : 0);
1636 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1638 // dst = trunc/extend to legal type
1639 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1642 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1644 // Rem needs compensation, it's easier to recompute it
1645 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1646 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1652 return DAG.getMergeValues(Res, DL);
1655 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1657 SmallVectorImpl<SDValue> &Results) const {
1658 assert(Op.getValueType() == MVT::i64);
1661 EVT VT = Op.getValueType();
1662 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1664 SDValue one = DAG.getConstant(1, DL, HalfVT);
1665 SDValue zero = DAG.getConstant(0, DL, HalfVT);
1668 SDValue LHS = Op.getOperand(0);
1669 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
1670 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
1672 SDValue RHS = Op.getOperand(1);
1673 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
1674 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
1676 if (VT == MVT::i64 &&
1677 DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1678 DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1680 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1683 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(0), zero);
1684 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(1), zero);
1685 Results.push_back(DIV);
1686 Results.push_back(REM);
1690 // Get Speculative values
1691 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1692 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1694 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
1695 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, zero);
1697 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
1698 SDValue DIV_Lo = zero;
1700 const unsigned halfBitWidth = HalfVT.getSizeInBits();
1702 for (unsigned i = 0; i < halfBitWidth; ++i) {
1703 const unsigned bitPos = halfBitWidth - i - 1;
1704 SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
1705 // Get value of high bit
1706 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1707 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
1708 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1711 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
1713 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1715 SDValue BIT = DAG.getConstant(1 << bitPos, DL, HalfVT);
1716 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
1718 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1721 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1722 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1725 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
1726 Results.push_back(DIV);
1727 Results.push_back(REM);
1730 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1731 SelectionDAG &DAG) const {
1733 EVT VT = Op.getValueType();
1735 if (VT == MVT::i64) {
1736 SmallVector<SDValue, 2> Results;
1737 LowerUDIVREM64(Op, DAG, Results);
1738 return DAG.getMergeValues(Results, DL);
1741 SDValue Num = Op.getOperand(0);
1742 SDValue Den = Op.getOperand(1);
1744 if (VT == MVT::i32) {
1745 if (DAG.MaskedValueIsZero(Num, APInt::getHighBitsSet(32, 8)) &&
1746 DAG.MaskedValueIsZero(Den, APInt::getHighBitsSet(32, 8))) {
1747 // TODO: We technically could do this for i64, but shouldn't that just be
1748 // handled by something generally reducing 64-bit division on 32-bit
1749 // values to 32-bit?
1750 return LowerDIVREM24(Op, DAG, false);
1754 // RCP = URECIP(Den) = 2^32 / Den + e
1755 // e is rounding error.
1756 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1758 // RCP_LO = mul(RCP, Den) */
1759 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1761 // RCP_HI = mulhu (RCP, Den) */
1762 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1764 // NEG_RCP_LO = -RCP_LO
1765 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1768 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1769 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1772 // Calculate the rounding error from the URECIP instruction
1773 // E = mulhu(ABS_RCP_LO, RCP)
1774 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1776 // RCP_A_E = RCP + E
1777 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1779 // RCP_S_E = RCP - E
1780 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1782 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1783 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1786 // Quotient = mulhu(Tmp0, Num)
1787 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1789 // Num_S_Remainder = Quotient * Den
1790 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1792 // Remainder = Num - Num_S_Remainder
1793 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1795 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1796 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1797 DAG.getConstant(-1, DL, VT),
1798 DAG.getConstant(0, DL, VT),
1800 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1801 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1803 DAG.getConstant(-1, DL, VT),
1804 DAG.getConstant(0, DL, VT),
1806 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1807 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1810 // Calculate Division result:
1812 // Quotient_A_One = Quotient + 1
1813 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1814 DAG.getConstant(1, DL, VT));
1816 // Quotient_S_One = Quotient - 1
1817 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1818 DAG.getConstant(1, DL, VT));
1820 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1821 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1822 Quotient, Quotient_A_One, ISD::SETEQ);
1824 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1825 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1826 Quotient_S_One, Div, ISD::SETEQ);
1828 // Calculate Rem result:
1830 // Remainder_S_Den = Remainder - Den
1831 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1833 // Remainder_A_Den = Remainder + Den
1834 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1836 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1837 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1838 Remainder, Remainder_S_Den, ISD::SETEQ);
1840 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1841 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1842 Remainder_A_Den, Rem, ISD::SETEQ);
1847 return DAG.getMergeValues(Ops, DL);
1850 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1851 SelectionDAG &DAG) const {
1853 EVT VT = Op.getValueType();
1855 SDValue LHS = Op.getOperand(0);
1856 SDValue RHS = Op.getOperand(1);
1858 SDValue Zero = DAG.getConstant(0, DL, VT);
1859 SDValue NegOne = DAG.getConstant(-1, DL, VT);
1861 if (VT == MVT::i32 &&
1862 DAG.ComputeNumSignBits(LHS) > 8 &&
1863 DAG.ComputeNumSignBits(RHS) > 8) {
1864 return LowerDIVREM24(Op, DAG, true);
1866 if (VT == MVT::i64 &&
1867 DAG.ComputeNumSignBits(LHS) > 32 &&
1868 DAG.ComputeNumSignBits(RHS) > 32) {
1869 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1872 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1873 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1874 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1877 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1878 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1880 return DAG.getMergeValues(Res, DL);
1883 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1884 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1885 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1886 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1888 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1889 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1891 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1892 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1894 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1895 SDValue Rem = Div.getValue(1);
1897 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1898 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1900 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1901 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1907 return DAG.getMergeValues(Res, DL);
1910 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1911 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1913 EVT VT = Op.getValueType();
1914 SDValue X = Op.getOperand(0);
1915 SDValue Y = Op.getOperand(1);
1917 // TODO: Should this propagate fast-math-flags?
1919 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1920 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1921 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1923 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1926 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1928 SDValue Src = Op.getOperand(0);
1930 // result = trunc(src)
1931 // if (src > 0.0 && src != result)
1934 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1936 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
1937 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1940 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
1942 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1943 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1944 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1946 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1947 // TODO: Should this propagate fast-math-flags?
1948 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1951 static SDValue extractF64Exponent(SDValue Hi, SDLoc SL, SelectionDAG &DAG) {
1952 const unsigned FractBits = 52;
1953 const unsigned ExpBits = 11;
1955 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1957 DAG.getConstant(FractBits - 32, SL, MVT::i32),
1958 DAG.getConstant(ExpBits, SL, MVT::i32));
1959 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1960 DAG.getConstant(1023, SL, MVT::i32));
1965 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1967 SDValue Src = Op.getOperand(0);
1969 assert(Op.getValueType() == MVT::f64);
1971 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1972 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1974 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1976 // Extract the upper half, since this is where we will find the sign and
1978 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1980 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
1982 const unsigned FractBits = 52;
1984 // Extract the sign bit.
1985 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32);
1986 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1988 // Extend back to to 64-bits.
1989 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1991 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1993 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1994 const SDValue FractMask
1995 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64);
1997 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1998 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1999 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
2002 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2004 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
2006 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2007 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2009 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
2010 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
2012 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
2015 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
2017 SDValue Src = Op.getOperand(0);
2019 assert(Op.getValueType() == MVT::f64);
2021 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
2022 SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
2023 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2025 // TODO: Should this propagate fast-math-flags?
2027 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2028 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2030 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2032 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
2033 SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
2036 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2037 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2039 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2042 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2043 // FNEARBYINT and FRINT are the same, except in their handling of FP
2044 // exceptions. Those aren't really meaningful for us, and OpenCL only has
2045 // rint, so just treat them as equivalent.
2046 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2049 // XXX - May require not supporting f32 denormals?
2050 SDValue AMDGPUTargetLowering::LowerFROUND32(SDValue Op, SelectionDAG &DAG) const {
2052 SDValue X = Op.getOperand(0);
2054 SDValue T = DAG.getNode(ISD::FTRUNC, SL, MVT::f32, X);
2056 // TODO: Should this propagate fast-math-flags?
2058 SDValue Diff = DAG.getNode(ISD::FSUB, SL, MVT::f32, X, T);
2060 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff);
2062 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f32);
2063 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
2064 const SDValue Half = DAG.getConstantFP(0.5, SL, MVT::f32);
2066 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f32, One, X);
2069 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
2071 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2073 SDValue Sel = DAG.getNode(ISD::SELECT, SL, MVT::f32, Cmp, SignOne, Zero);
2075 return DAG.getNode(ISD::FADD, SL, MVT::f32, T, Sel);
2078 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
2080 SDValue X = Op.getOperand(0);
2082 SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
2084 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2085 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2086 const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
2087 const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
2089 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2091 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2093 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
2095 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2097 const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL,
2100 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2101 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2102 DAG.getConstant(INT64_C(0x0008000000000000), SL,
2106 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2107 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
2108 DAG.getConstant(0, SL, MVT::i64), Tmp0,
2111 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2112 D, DAG.getConstant(0, SL, MVT::i64));
2113 SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
2115 K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2116 K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
2118 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2119 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2120 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
2122 SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
2124 DAG.getConstantFP(1.0, SL, MVT::f64),
2125 DAG.getConstantFP(0.0, SL, MVT::f64));
2127 SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
2129 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
2130 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
2135 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2136 EVT VT = Op.getValueType();
2139 return LowerFROUND32(Op, DAG);
2142 return LowerFROUND64(Op, DAG);
2144 llvm_unreachable("unhandled type");
2147 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2149 SDValue Src = Op.getOperand(0);
2151 // result = trunc(src);
2152 // if (src < 0.0 && src != result)
2155 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2157 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2158 const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
2161 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2163 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2164 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2165 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2167 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2168 // TODO: Should this propagate fast-math-flags?
2169 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2172 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2173 bool Signed) const {
2175 SDValue Src = Op.getOperand(0);
2177 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2179 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2180 DAG.getConstant(0, SL, MVT::i32));
2181 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2182 DAG.getConstant(1, SL, MVT::i32));
2184 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2187 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2189 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2190 DAG.getConstant(32, SL, MVT::i32));
2191 // TODO: Should this propagate fast-math-flags?
2192 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2195 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2196 SelectionDAG &DAG) const {
2197 SDValue S0 = Op.getOperand(0);
2198 if (S0.getValueType() != MVT::i64)
2201 EVT DestVT = Op.getValueType();
2202 if (DestVT == MVT::f64)
2203 return LowerINT_TO_FP64(Op, DAG, false);
2205 assert(DestVT == MVT::f32);
2209 // f32 uint_to_fp i64
2210 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2211 DAG.getConstant(0, DL, MVT::i32));
2212 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
2213 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2214 DAG.getConstant(1, DL, MVT::i32));
2215 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
2216 // TODO: Should this propagate fast-math-flags?
2217 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
2218 DAG.getConstantFP(4294967296.0f, DL, MVT::f32)); // 2^32
2219 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
2222 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2223 SelectionDAG &DAG) const {
2224 SDValue Src = Op.getOperand(0);
2225 if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64)
2226 return LowerINT_TO_FP64(Op, DAG, true);
2231 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2232 bool Signed) const {
2235 SDValue Src = Op.getOperand(0);
2237 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2239 SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL,
2241 SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL,
2243 // TODO: Should this propagate fast-math-flags?
2244 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2246 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2249 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2251 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2252 MVT::i32, FloorMul);
2253 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2255 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
2257 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2260 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2261 SelectionDAG &DAG) const {
2262 SDValue Src = Op.getOperand(0);
2264 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2265 return LowerFP64_TO_INT(Op, DAG, true);
2270 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2271 SelectionDAG &DAG) const {
2272 SDValue Src = Op.getOperand(0);
2274 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2275 return LowerFP64_TO_INT(Op, DAG, false);
2280 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2281 SelectionDAG &DAG) const {
2282 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2283 MVT VT = Op.getSimpleValueType();
2284 MVT ScalarVT = VT.getScalarType();
2289 SDValue Src = Op.getOperand(0);
2292 // TODO: Don't scalarize on Evergreen?
2293 unsigned NElts = VT.getVectorNumElements();
2294 SmallVector<SDValue, 8> Args;
2295 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2297 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2298 for (unsigned I = 0; I < NElts; ++I)
2299 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2301 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
2304 //===----------------------------------------------------------------------===//
2305 // Custom DAG optimizations
2306 //===----------------------------------------------------------------------===//
2308 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2309 APInt KnownZero, KnownOne;
2310 EVT VT = Op.getValueType();
2311 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2313 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2316 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2317 EVT VT = Op.getValueType();
2319 // In order for this to be a signed 24-bit value, bit 23, must
2321 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2322 // as unsigned 24-bit values.
2323 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2326 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2328 SelectionDAG &DAG = DCI.DAG;
2329 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2330 EVT VT = Op.getValueType();
2332 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2333 APInt KnownZero, KnownOne;
2334 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2335 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2336 DCI.CommitTargetLoweringOpt(TLO);
2339 template <typename IntTy>
2340 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
2341 uint32_t Offset, uint32_t Width, SDLoc DL) {
2342 if (Width + Offset < 32) {
2343 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2344 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2345 return DAG.getConstant(Result, DL, MVT::i32);
2348 return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2351 static bool usesAllNormalStores(SDNode *LoadVal) {
2352 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2353 if (!ISD::isNormalStore(*I))
2360 // If we have a copy of an illegal type, replace it with a load / store of an
2361 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2362 // instructions emitted when handling extloads and truncstores. Ideally we could
2363 // recognize the pack / unpack pattern to eliminate it.
2364 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2365 DAGCombinerInfo &DCI) const {
2366 if (!DCI.isBeforeLegalize())
2369 StoreSDNode *SN = cast<StoreSDNode>(N);
2370 SDValue Value = SN->getValue();
2371 EVT VT = Value.getValueType();
2373 if (isTypeLegal(VT) || SN->isVolatile() ||
2374 !ISD::isNormalLoad(Value.getNode()) || VT.getSizeInBits() < 8)
2377 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2378 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2381 EVT MemVT = LoadVal->getMemoryVT();
2384 SelectionDAG &DAG = DCI.DAG;
2385 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2387 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2389 LoadVal->getChain(),
2390 LoadVal->getBasePtr(),
2391 LoadVal->getOffset(),
2393 LoadVal->getMemOperand());
2395 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2396 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2398 return DAG.getStore(SN->getChain(), SL, NewLoad,
2399 SN->getBasePtr(), SN->getMemOperand());
2402 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
2403 DAGCombinerInfo &DCI) const {
2404 if (N->getValueType(0) != MVT::i64)
2407 // i64 (shl x, 32) -> (build_pair 0, x)
2409 // Doing this with moves theoretically helps MI optimizations that understand
2410 // copies. 2 v_mov_b32_e32 will have the same code size / cycle count as
2411 // v_lshl_b64. In the SALU case, I think this is slightly worse since it
2412 // doubles the code size and I'm unsure about cycle count.
2413 const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2414 if (!RHS || RHS->getZExtValue() != 32)
2417 SDValue LHS = N->getOperand(0);
2420 SelectionDAG &DAG = DCI.DAG;
2422 // Extract low 32-bits.
2423 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
2425 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2426 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, Zero, Lo);
2429 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2430 DAGCombinerInfo &DCI) const {
2431 EVT VT = N->getValueType(0);
2433 if (VT.isVector() || VT.getSizeInBits() > 32)
2436 SelectionDAG &DAG = DCI.DAG;
2439 SDValue N0 = N->getOperand(0);
2440 SDValue N1 = N->getOperand(1);
2443 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2444 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2445 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2446 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2447 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2448 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2449 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2450 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2455 // We need to use sext even for MUL_U24, because MUL_U24 is used
2456 // for signed multiply of 8 and 16-bit types.
2457 return DAG.getSExtOrTrunc(Mul, DL, VT);
2460 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2461 DAGCombinerInfo &DCI) const {
2462 SelectionDAG &DAG = DCI.DAG;
2465 switch(N->getOpcode()) {
2469 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2472 return performShlCombine(N, DCI);
2475 return performMulCombine(N, DCI);
2476 case AMDGPUISD::MUL_I24:
2477 case AMDGPUISD::MUL_U24: {
2478 SDValue N0 = N->getOperand(0);
2479 SDValue N1 = N->getOperand(1);
2480 simplifyI24(N0, DCI);
2481 simplifyI24(N1, DCI);
2485 SDValue Cond = N->getOperand(0);
2486 if (Cond.getOpcode() == ISD::SETCC && Cond.hasOneUse()) {
2487 EVT VT = N->getValueType(0);
2488 SDValue LHS = Cond.getOperand(0);
2489 SDValue RHS = Cond.getOperand(1);
2490 SDValue CC = Cond.getOperand(2);
2492 SDValue True = N->getOperand(1);
2493 SDValue False = N->getOperand(2);
2496 return CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
2501 case AMDGPUISD::BFE_I32:
2502 case AMDGPUISD::BFE_U32: {
2503 assert(!N->getValueType(0).isVector() &&
2504 "Vector handling of BFE not implemented");
2505 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2509 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2511 return DAG.getConstant(0, DL, MVT::i32);
2513 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2517 SDValue BitsFrom = N->getOperand(0);
2518 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2520 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2522 if (OffsetVal == 0) {
2523 // This is already sign / zero extended, so try to fold away extra BFEs.
2524 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2526 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2527 if (OpSignBits >= SignBits)
2530 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2532 // This is a sign_extend_inreg. Replace it to take advantage of existing
2533 // DAG Combines. If not eliminated, we will match back to BFE during
2536 // TODO: The sext_inreg of extended types ends, although we can could
2537 // handle them in a single BFE.
2538 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2539 DAG.getValueType(SmallVT));
2542 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2545 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2547 return constantFoldBFE<int32_t>(DAG,
2548 CVal->getSExtValue(),
2554 return constantFoldBFE<uint32_t>(DAG,
2555 CVal->getZExtValue(),
2561 if ((OffsetVal + WidthVal) >= 32) {
2562 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
2563 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2564 BitsFrom, ShiftVal);
2567 if (BitsFrom.hasOneUse()) {
2568 APInt Demanded = APInt::getBitsSet(32,
2570 OffsetVal + WidthVal);
2572 APInt KnownZero, KnownOne;
2573 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2574 !DCI.isBeforeLegalizeOps());
2575 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2576 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2577 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2578 KnownZero, KnownOne, TLO)) {
2579 DCI.CommitTargetLoweringOpt(TLO);
2587 return performStoreCombine(N, DCI);
2592 //===----------------------------------------------------------------------===//
2594 //===----------------------------------------------------------------------===//
2596 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2599 const SmallVectorImpl<ISD::InputArg> &Ins,
2600 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2602 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2603 if (Ins[i].ArgVT == Ins[i].VT) {
2604 OrigIns.push_back(Ins[i]);
2609 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2610 // Vector has been split into scalars.
2611 VT = Ins[i].ArgVT.getVectorElementType();
2612 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2613 Ins[i].ArgVT.getVectorElementType() !=
2614 Ins[i].VT.getVectorElementType()) {
2615 // Vector elements have been promoted
2618 // Vector has been spilt into smaller vectors.
2622 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2623 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2624 OrigIns.push_back(Arg);
2628 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2629 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2630 return CFP->isExactlyValue(1.0);
2632 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2633 return C->isAllOnesValue();
2638 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2639 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2640 return CFP->getValueAPF().isZero();
2642 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2643 return C->isNullValue();
2648 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2649 const TargetRegisterClass *RC,
2650 unsigned Reg, EVT VT) const {
2651 MachineFunction &MF = DAG.getMachineFunction();
2652 MachineRegisterInfo &MRI = MF.getRegInfo();
2653 unsigned VirtualRegister;
2654 if (!MRI.isLiveIn(Reg)) {
2655 VirtualRegister = MRI.createVirtualRegister(RC);
2656 MRI.addLiveIn(Reg, VirtualRegister);
2658 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2660 return DAG.getRegister(VirtualRegister, VT);
2663 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
2664 const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const {
2665 uint64_t ArgOffset = MFI->ABIArgOffset;
2670 return ArgOffset + 4;
2672 llvm_unreachable("unexpected implicit parameter type");
2675 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2677 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2678 switch ((AMDGPUISD::NodeType)Opcode) {
2679 case AMDGPUISD::FIRST_NUMBER: break;
2681 NODE_NAME_CASE(CALL);
2682 NODE_NAME_CASE(UMUL);
2683 NODE_NAME_CASE(RET_FLAG);
2684 NODE_NAME_CASE(BRANCH_COND);
2687 NODE_NAME_CASE(DWORDADDR)
2688 NODE_NAME_CASE(FRACT)
2689 NODE_NAME_CASE(CLAMP)
2690 NODE_NAME_CASE(COS_HW)
2691 NODE_NAME_CASE(SIN_HW)
2692 NODE_NAME_CASE(FMAX_LEGACY)
2693 NODE_NAME_CASE(FMIN_LEGACY)
2694 NODE_NAME_CASE(FMAX3)
2695 NODE_NAME_CASE(SMAX3)
2696 NODE_NAME_CASE(UMAX3)
2697 NODE_NAME_CASE(FMIN3)
2698 NODE_NAME_CASE(SMIN3)
2699 NODE_NAME_CASE(UMIN3)
2700 NODE_NAME_CASE(URECIP)
2701 NODE_NAME_CASE(DIV_SCALE)
2702 NODE_NAME_CASE(DIV_FMAS)
2703 NODE_NAME_CASE(DIV_FIXUP)
2704 NODE_NAME_CASE(TRIG_PREOP)
2707 NODE_NAME_CASE(RSQ_LEGACY)
2708 NODE_NAME_CASE(RSQ_CLAMPED)
2709 NODE_NAME_CASE(LDEXP)
2710 NODE_NAME_CASE(FP_CLASS)
2711 NODE_NAME_CASE(DOT4)
2712 NODE_NAME_CASE(CARRY)
2713 NODE_NAME_CASE(BORROW)
2714 NODE_NAME_CASE(BFE_U32)
2715 NODE_NAME_CASE(BFE_I32)
2718 NODE_NAME_CASE(BREV)
2719 NODE_NAME_CASE(MUL_U24)
2720 NODE_NAME_CASE(MUL_I24)
2721 NODE_NAME_CASE(MAD_U24)
2722 NODE_NAME_CASE(MAD_I24)
2723 NODE_NAME_CASE(TEXTURE_FETCH)
2724 NODE_NAME_CASE(EXPORT)
2725 NODE_NAME_CASE(CONST_ADDRESS)
2726 NODE_NAME_CASE(REGISTER_LOAD)
2727 NODE_NAME_CASE(REGISTER_STORE)
2728 NODE_NAME_CASE(LOAD_CONSTANT)
2729 NODE_NAME_CASE(LOAD_INPUT)
2730 NODE_NAME_CASE(SAMPLE)
2731 NODE_NAME_CASE(SAMPLEB)
2732 NODE_NAME_CASE(SAMPLED)
2733 NODE_NAME_CASE(SAMPLEL)
2734 NODE_NAME_CASE(CVT_F32_UBYTE0)
2735 NODE_NAME_CASE(CVT_F32_UBYTE1)
2736 NODE_NAME_CASE(CVT_F32_UBYTE2)
2737 NODE_NAME_CASE(CVT_F32_UBYTE3)
2738 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2739 NODE_NAME_CASE(CONST_DATA_PTR)
2740 case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
2741 NODE_NAME_CASE(SENDMSG)
2742 NODE_NAME_CASE(INTERP_MOV)
2743 NODE_NAME_CASE(INTERP_P1)
2744 NODE_NAME_CASE(INTERP_P2)
2745 NODE_NAME_CASE(STORE_MSKOR)
2746 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2747 case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break;
2752 SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
2753 DAGCombinerInfo &DCI,
2754 unsigned &RefinementSteps,
2755 bool &UseOneConstNR) const {
2756 SelectionDAG &DAG = DCI.DAG;
2757 EVT VT = Operand.getValueType();
2759 if (VT == MVT::f32) {
2760 RefinementSteps = 0;
2761 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
2764 // TODO: There is also f64 rsq instruction, but the documentation is less
2765 // clear on its precision.
2770 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
2771 DAGCombinerInfo &DCI,
2772 unsigned &RefinementSteps) const {
2773 SelectionDAG &DAG = DCI.DAG;
2774 EVT VT = Operand.getValueType();
2776 if (VT == MVT::f32) {
2777 // Reciprocal, < 1 ulp error.
2779 // This reciprocal approximation converges to < 0.5 ulp error with one
2780 // newton rhapson performed with two fused multiple adds (FMAs).
2782 RefinementSteps = 0;
2783 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
2786 // TODO: There is also f64 rcp instruction, but the documentation is less
2787 // clear on its precision.
2792 static void computeKnownBitsForMinMax(const SDValue Op0,
2796 const SelectionDAG &DAG,
2798 APInt Op0Zero, Op0One;
2799 APInt Op1Zero, Op1One;
2800 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2801 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2803 KnownZero = Op0Zero & Op1Zero;
2804 KnownOne = Op0One & Op1One;
2807 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2811 const SelectionDAG &DAG,
2812 unsigned Depth) const {
2814 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2818 unsigned Opc = Op.getOpcode();
2823 case ISD::INTRINSIC_WO_CHAIN: {
2824 // FIXME: The intrinsic should just use the node.
2825 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2826 case AMDGPUIntrinsic::AMDGPU_imax:
2827 case AMDGPUIntrinsic::AMDGPU_umax:
2828 case AMDGPUIntrinsic::AMDGPU_imin:
2829 case AMDGPUIntrinsic::AMDGPU_umin:
2830 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2831 KnownZero, KnownOne, DAG, Depth);
2839 case AMDGPUISD::CARRY:
2840 case AMDGPUISD::BORROW: {
2841 KnownZero = APInt::getHighBitsSet(32, 31);
2845 case AMDGPUISD::BFE_I32:
2846 case AMDGPUISD::BFE_U32: {
2847 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2851 unsigned BitWidth = 32;
2852 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2854 if (Opc == AMDGPUISD::BFE_U32)
2855 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2862 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2864 const SelectionDAG &DAG,
2865 unsigned Depth) const {
2866 switch (Op.getOpcode()) {
2867 case AMDGPUISD::BFE_I32: {
2868 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2872 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2873 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2874 if (!Offset || !Offset->isNullValue())
2877 // TODO: Could probably figure something out with non-0 offsets.
2878 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2879 return std::max(SignBits, Op0SignBits);
2882 case AMDGPUISD::BFE_U32: {
2883 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2884 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
2887 case AMDGPUISD::CARRY:
2888 case AMDGPUISD::BORROW: