1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
40 const Twine &Description;
45 static int getKindID() {
47 KindID = llvm::getNextAvailablePluginDiagnosticKind();
52 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53 DiagnosticSeverity Severity = DS_Error)
54 : DiagnosticInfo(getKindID(), Severity),
58 const Function &getFunction() const { return Fn; }
59 const Twine &getDescription() const { return Description; }
61 void print(DiagnosticPrinter &DP) const override {
62 DP << "unsupported " << getDescription() << " in " << Fn.getName();
65 static bool classof(const DiagnosticInfo *DI) {
66 return DI->getKind() == getKindID();
70 int DiagnosticInfoUnsupported::KindID = 0;
74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75 CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State) {
77 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78 ArgFlags.getOrigAlign());
79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
84 #include "AMDGPUGenCallingConv.inc"
86 // Find a larger type to do a load / store of a vector with.
87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88 unsigned StoreSize = VT.getStoreSizeInBits();
90 return EVT::getIntegerVT(Ctx, StoreSize);
92 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
96 // Type for a vector that will be loaded to.
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98 unsigned StoreSize = VT.getStoreSizeInBits();
100 return EVT::getIntegerVT(Ctx, 32);
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
106 const AMDGPUSubtarget &STI)
107 : TargetLowering(TM), Subtarget(&STI) {
108 setOperationAction(ISD::Constant, MVT::i32, Legal);
109 setOperationAction(ISD::Constant, MVT::i64, Legal);
110 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
111 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
113 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
114 setOperationAction(ISD::BRIND, MVT::Other, Expand);
116 // This is totally unsupported, just custom lower to produce an error.
117 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
119 // We need to custom lower some of the intrinsics
120 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
122 // Library functions. These default to Expand, but we have instructions
124 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
125 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
126 setOperationAction(ISD::FPOW, MVT::f32, Legal);
127 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
128 setOperationAction(ISD::FABS, MVT::f32, Legal);
129 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
130 setOperationAction(ISD::FRINT, MVT::f32, Legal);
131 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
132 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
133 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
135 setOperationAction(ISD::FROUND, MVT::f32, Custom);
136 setOperationAction(ISD::FROUND, MVT::f64, Custom);
138 setOperationAction(ISD::FREM, MVT::f32, Custom);
139 setOperationAction(ISD::FREM, MVT::f64, Custom);
141 // v_mad_f32 does not support denormals according to some sources.
142 if (!Subtarget->hasFP32Denormals())
143 setOperationAction(ISD::FMAD, MVT::f32, Legal);
145 // Expand to fneg + fadd.
146 setOperationAction(ISD::FSUB, MVT::f64, Expand);
148 // Lower floating point store/load to integer store/load to reduce the number
149 // of patterns in tablegen.
150 setOperationAction(ISD::STORE, MVT::f32, Promote);
151 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
153 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
154 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
156 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
157 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
159 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
160 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
162 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
163 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
165 setOperationAction(ISD::STORE, MVT::f64, Promote);
166 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
168 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
169 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
171 // Custom lowering of vector stores is required for local address space
173 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
175 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
176 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
177 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
179 // XXX: This can be change to Custom, once ExpandVectorStores can
180 // handle 64-bit stores.
181 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
183 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
184 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
185 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
186 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
187 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
190 setOperationAction(ISD::LOAD, MVT::f32, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
193 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
196 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
197 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
199 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
200 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
202 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
203 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
205 setOperationAction(ISD::LOAD, MVT::f64, Promote);
206 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
208 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
209 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
211 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
212 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
213 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
214 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
216 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
217 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
218 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
219 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
220 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
222 // There are no 64-bit extloads. These should be done as a 32-bit extload and
223 // an extension to 64-bit.
224 for (MVT VT : MVT::integer_valuetypes()) {
225 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
226 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
227 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
230 for (MVT VT : MVT::integer_vector_valuetypes()) {
231 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
232 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
233 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
234 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
235 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
236 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
237 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
238 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
239 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
240 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
241 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
242 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
245 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
247 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
248 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
249 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
250 setOperationAction(ISD::FRINT, MVT::f64, Custom);
251 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
254 if (!Subtarget->hasBFI()) {
255 // fcopysign can be done in a single instruction with BFI.
256 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
257 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
260 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
262 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
263 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
264 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
265 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand);
267 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
268 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
269 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
270 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand);
272 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
273 setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand);
274 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
275 setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand);
277 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
278 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
280 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
281 for (MVT VT : ScalarIntVTs) {
282 setOperationAction(ISD::SREM, VT, Expand);
283 setOperationAction(ISD::SDIV, VT, Expand);
285 // GPU does not have divrem function for signed or unsigned.
286 setOperationAction(ISD::SDIVREM, VT, Custom);
287 setOperationAction(ISD::UDIVREM, VT, Custom);
289 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
290 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
291 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
293 setOperationAction(ISD::BSWAP, VT, Expand);
294 setOperationAction(ISD::CTTZ, VT, Expand);
295 setOperationAction(ISD::CTLZ, VT, Expand);
298 if (!Subtarget->hasBCNT(32))
299 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
301 if (!Subtarget->hasBCNT(64))
302 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
304 // The hardware supports 32-bit ROTR, but not ROTL.
305 setOperationAction(ISD::ROTL, MVT::i32, Expand);
306 setOperationAction(ISD::ROTL, MVT::i64, Expand);
307 setOperationAction(ISD::ROTR, MVT::i64, Expand);
309 setOperationAction(ISD::MUL, MVT::i64, Expand);
310 setOperationAction(ISD::MULHU, MVT::i64, Expand);
311 setOperationAction(ISD::MULHS, MVT::i64, Expand);
312 setOperationAction(ISD::UDIV, MVT::i32, Expand);
313 setOperationAction(ISD::UREM, MVT::i32, Expand);
314 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
315 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
316 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
317 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
318 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
320 setOperationAction(ISD::SMIN, MVT::i32, Legal);
321 setOperationAction(ISD::UMIN, MVT::i32, Legal);
322 setOperationAction(ISD::SMAX, MVT::i32, Legal);
323 setOperationAction(ISD::UMAX, MVT::i32, Legal);
325 if (!Subtarget->hasFFBH())
326 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
328 if (!Subtarget->hasFFBL())
329 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
331 static const MVT::SimpleValueType VectorIntTypes[] = {
332 MVT::v2i32, MVT::v4i32
335 for (MVT VT : VectorIntTypes) {
336 // Expand the following operations for the current type by default.
337 setOperationAction(ISD::ADD, VT, Expand);
338 setOperationAction(ISD::AND, VT, Expand);
339 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
340 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
341 setOperationAction(ISD::MUL, VT, Expand);
342 setOperationAction(ISD::OR, VT, Expand);
343 setOperationAction(ISD::SHL, VT, Expand);
344 setOperationAction(ISD::SRA, VT, Expand);
345 setOperationAction(ISD::SRL, VT, Expand);
346 setOperationAction(ISD::ROTL, VT, Expand);
347 setOperationAction(ISD::ROTR, VT, Expand);
348 setOperationAction(ISD::SUB, VT, Expand);
349 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
350 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
351 setOperationAction(ISD::SDIV, VT, Expand);
352 setOperationAction(ISD::UDIV, VT, Expand);
353 setOperationAction(ISD::SREM, VT, Expand);
354 setOperationAction(ISD::UREM, VT, Expand);
355 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
356 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
357 setOperationAction(ISD::SDIVREM, VT, Custom);
358 setOperationAction(ISD::UDIVREM, VT, Expand);
359 setOperationAction(ISD::ADDC, VT, Expand);
360 setOperationAction(ISD::SUBC, VT, Expand);
361 setOperationAction(ISD::ADDE, VT, Expand);
362 setOperationAction(ISD::SUBE, VT, Expand);
363 setOperationAction(ISD::SELECT, VT, Expand);
364 setOperationAction(ISD::VSELECT, VT, Expand);
365 setOperationAction(ISD::SELECT_CC, VT, Expand);
366 setOperationAction(ISD::XOR, VT, Expand);
367 setOperationAction(ISD::BSWAP, VT, Expand);
368 setOperationAction(ISD::CTPOP, VT, Expand);
369 setOperationAction(ISD::CTTZ, VT, Expand);
370 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
371 setOperationAction(ISD::CTLZ, VT, Expand);
372 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
373 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
376 static const MVT::SimpleValueType FloatVectorTypes[] = {
377 MVT::v2f32, MVT::v4f32
380 for (MVT VT : FloatVectorTypes) {
381 setOperationAction(ISD::FABS, VT, Expand);
382 setOperationAction(ISD::FMINNUM, VT, Expand);
383 setOperationAction(ISD::FMAXNUM, VT, Expand);
384 setOperationAction(ISD::FADD, VT, Expand);
385 setOperationAction(ISD::FCEIL, VT, Expand);
386 setOperationAction(ISD::FCOS, VT, Expand);
387 setOperationAction(ISD::FDIV, VT, Expand);
388 setOperationAction(ISD::FEXP2, VT, Expand);
389 setOperationAction(ISD::FLOG2, VT, Expand);
390 setOperationAction(ISD::FREM, VT, Expand);
391 setOperationAction(ISD::FPOW, VT, Expand);
392 setOperationAction(ISD::FFLOOR, VT, Expand);
393 setOperationAction(ISD::FTRUNC, VT, Expand);
394 setOperationAction(ISD::FMUL, VT, Expand);
395 setOperationAction(ISD::FMA, VT, Expand);
396 setOperationAction(ISD::FRINT, VT, Expand);
397 setOperationAction(ISD::FNEARBYINT, VT, Expand);
398 setOperationAction(ISD::FSQRT, VT, Expand);
399 setOperationAction(ISD::FSIN, VT, Expand);
400 setOperationAction(ISD::FSUB, VT, Expand);
401 setOperationAction(ISD::FNEG, VT, Expand);
402 setOperationAction(ISD::SELECT, VT, Expand);
403 setOperationAction(ISD::VSELECT, VT, Expand);
404 setOperationAction(ISD::SELECT_CC, VT, Expand);
405 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
406 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
409 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
410 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
412 setTargetDAGCombine(ISD::SHL);
413 setTargetDAGCombine(ISD::MUL);
414 setTargetDAGCombine(ISD::SELECT);
415 setTargetDAGCombine(ISD::SELECT_CC);
416 setTargetDAGCombine(ISD::STORE);
418 setTargetDAGCombine(ISD::FADD);
419 setTargetDAGCombine(ISD::FSUB);
421 setBooleanContents(ZeroOrNegativeOneBooleanContent);
422 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
424 setSchedulingPreference(Sched::RegPressure);
425 setJumpIsExpensive(true);
427 // SI at least has hardware support for floating point exceptions, but no way
428 // of using or handling them is implemented. They are also optional in OpenCL
430 setHasFloatingPointExceptions(false);
432 setSelectIsExpensive(false);
433 PredictableSelectIsExpensive = false;
435 setFsqrtIsCheap(true);
437 // FIXME: Need to really handle these.
438 MaxStoresPerMemcpy = 4096;
439 MaxStoresPerMemmove = 4096;
440 MaxStoresPerMemset = 4096;
443 //===----------------------------------------------------------------------===//
444 // Target Information
445 //===----------------------------------------------------------------------===//
447 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
451 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
455 // The backend supports 32 and 64 bit floating point immediates.
456 // FIXME: Why are we reporting vectors of FP immediates as legal?
457 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
458 EVT ScalarVT = VT.getScalarType();
459 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
462 // We don't want to shrink f64 / f32 constants.
463 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
464 EVT ScalarVT = VT.getScalarType();
465 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
468 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
472 unsigned NewSize = NewVT.getStoreSizeInBits();
474 // If we are reducing to a 32-bit load, this is always better.
478 EVT OldVT = N->getValueType(0);
479 unsigned OldSize = OldVT.getStoreSizeInBits();
481 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
482 // extloads, so doing one requires using a buffer_load. In cases where we
483 // still couldn't use a scalar load, using the wider load shouldn't really
486 // If the old size already had to be an extload, there's no harm in continuing
487 // to reduce the width.
488 return (OldSize < 32);
491 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
493 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
496 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
497 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
499 return ((LScalarSize <= CastScalarSize) ||
500 (CastScalarSize >= 32) ||
504 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
505 // profitable with the expansion for 64-bit since it's generally good to
507 // FIXME: These should really have the size as a parameter.
508 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
512 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
516 //===---------------------------------------------------------------------===//
518 //===---------------------------------------------------------------------===//
520 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
521 assert(VT.isFloatingPoint());
522 return VT == MVT::f32 || VT == MVT::f64;
525 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
526 assert(VT.isFloatingPoint());
527 return VT == MVT::f32 || VT == MVT::f64;
530 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
536 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {
537 // There are few operations which truly have vector input operands. Any vector
538 // operation is going to involve operations on each component, and a
539 // build_vector will be a copy per element, so it always makes sense to use a
540 // build_vector input in place of the extracted element to avoid a copy into a
543 // We should probably only do this if all users are extracts only, but this
544 // should be the common case.
548 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
549 // Truncate is just accessing a subregister.
550 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
553 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
554 // Truncate is just accessing a subregister.
555 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
556 (Dest->getPrimitiveSizeInBits() % 32 == 0);
559 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
560 unsigned SrcSize = Src->getScalarSizeInBits();
561 unsigned DestSize = Dest->getScalarSizeInBits();
563 return SrcSize == 32 && DestSize == 64;
566 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
567 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
568 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
569 // this will enable reducing 64-bit operations the 32-bit, which is always
571 return Src == MVT::i32 && Dest == MVT::i64;
574 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
575 return isZExtFree(Val.getValueType(), VT2);
578 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
579 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
580 // limited number of native 64-bit operations. Shrinking an operation to fit
581 // in a single 32-bit register should always be helpful. As currently used,
582 // this is much less general than the name suggests, and is only used in
583 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
584 // not profitable, and may actually be harmful.
585 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
588 //===---------------------------------------------------------------------===//
589 // TargetLowering Callbacks
590 //===---------------------------------------------------------------------===//
592 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
593 const SmallVectorImpl<ISD::InputArg> &Ins) const {
595 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
598 SDValue AMDGPUTargetLowering::LowerReturn(
600 CallingConv::ID CallConv,
602 const SmallVectorImpl<ISD::OutputArg> &Outs,
603 const SmallVectorImpl<SDValue> &OutVals,
604 SDLoc DL, SelectionDAG &DAG) const {
605 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
608 //===---------------------------------------------------------------------===//
609 // Target specific lowering
610 //===---------------------------------------------------------------------===//
612 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
613 SmallVectorImpl<SDValue> &InVals) const {
614 SDValue Callee = CLI.Callee;
615 SelectionDAG &DAG = CLI.DAG;
617 const Function &Fn = *DAG.getMachineFunction().getFunction();
619 StringRef FuncName("<unknown>");
621 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
622 FuncName = G->getSymbol();
623 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
624 FuncName = G->getGlobal()->getName();
626 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
627 DAG.getContext()->diagnose(NoCalls);
631 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
632 SelectionDAG &DAG) const {
633 const Function &Fn = *DAG.getMachineFunction().getFunction();
635 DiagnosticInfoUnsupported NoDynamicAlloca(Fn, "dynamic alloca");
636 DAG.getContext()->diagnose(NoDynamicAlloca);
640 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
641 SelectionDAG &DAG) const {
642 switch (Op.getOpcode()) {
644 Op.getNode()->dump();
645 llvm_unreachable("Custom lowering code for this"
646 "instruction is not implemented yet!");
648 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
649 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
650 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
651 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
652 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
653 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
654 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
655 case ISD::FREM: return LowerFREM(Op, DAG);
656 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
657 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
658 case ISD::FRINT: return LowerFRINT(Op, DAG);
659 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
660 case ISD::FROUND: return LowerFROUND(Op, DAG);
661 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
662 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
663 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
664 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
665 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
666 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
671 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
672 SmallVectorImpl<SDValue> &Results,
673 SelectionDAG &DAG) const {
674 switch (N->getOpcode()) {
675 case ISD::SIGN_EXTEND_INREG:
676 // Different parts of legalization seem to interpret which type of
677 // sign_extend_inreg is the one to check for custom lowering. The extended
678 // from type is what really matters, but some places check for custom
679 // lowering of the result type. This results in trying to use
680 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
681 // nothing here and let the illegal result integer be handled normally.
684 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
688 Results.push_back(SDValue(Node, 0));
689 Results.push_back(SDValue(Node, 1));
690 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
692 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
696 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
697 if (Lowered.getNode())
698 Results.push_back(Lowered);
706 // FIXME: This implements accesses to initialized globals in the constant
707 // address space by copying them to private and accessing that. It does not
708 // properly handle illegal types or vectors. The private vector loads are not
709 // scalarized, and the illegal scalars hit an assertion. This technique will not
710 // work well with large initializers, and this should eventually be
711 // removed. Initialized globals should be placed into a data section that the
712 // runtime will load into a buffer before the kernel is executed. Uses of the
713 // global need to be replaced with a pointer loaded from an implicit kernel
714 // argument into this buffer holding the copy of the data, which will remove the
715 // need for any of this.
716 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
717 const GlobalValue *GV,
718 const SDValue &InitPtr,
720 SelectionDAG &DAG) const {
721 const DataLayout &TD = DAG.getDataLayout();
723 Type *InitTy = Init->getType();
725 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
726 EVT VT = EVT::getEVT(InitTy);
727 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
728 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, DL, VT), InitPtr,
729 MachinePointerInfo(UndefValue::get(PtrTy)), false,
730 false, TD.getPrefTypeAlignment(InitTy));
733 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
734 EVT VT = EVT::getEVT(CFP->getType());
735 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
736 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, DL, VT), InitPtr,
737 MachinePointerInfo(UndefValue::get(PtrTy)), false,
738 false, TD.getPrefTypeAlignment(CFP->getType()));
741 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
742 const StructLayout *SL = TD.getStructLayout(ST);
744 EVT PtrVT = InitPtr.getValueType();
745 SmallVector<SDValue, 8> Chains;
747 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
748 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), DL, PtrVT);
749 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
751 Constant *Elt = Init->getAggregateElement(I);
752 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
755 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
758 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
759 EVT PtrVT = InitPtr.getValueType();
761 unsigned NumElements;
762 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
763 NumElements = AT->getNumElements();
764 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
765 NumElements = VT->getNumElements();
767 llvm_unreachable("Unexpected type");
769 unsigned EltSize = TD.getTypeAllocSize(SeqTy->getElementType());
770 SmallVector<SDValue, 8> Chains;
771 for (unsigned i = 0; i < NumElements; ++i) {
772 SDValue Offset = DAG.getConstant(i * EltSize, DL, PtrVT);
773 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
775 Constant *Elt = Init->getAggregateElement(i);
776 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
779 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
782 if (isa<UndefValue>(Init)) {
783 EVT VT = EVT::getEVT(InitTy);
784 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
785 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
786 MachinePointerInfo(UndefValue::get(PtrTy)), false,
787 false, TD.getPrefTypeAlignment(InitTy));
791 llvm_unreachable("Unhandled constant initializer");
794 static bool hasDefinedInitializer(const GlobalValue *GV) {
795 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
796 if (!GVar || !GVar->hasInitializer())
799 if (isa<UndefValue>(GVar->getInitializer()))
805 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
807 SelectionDAG &DAG) const {
809 const DataLayout &DL = DAG.getDataLayout();
810 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
811 const GlobalValue *GV = G->getGlobal();
813 switch (G->getAddressSpace()) {
814 case AMDGPUAS::LOCAL_ADDRESS: {
815 // XXX: What does the value of G->getOffset() mean?
816 assert(G->getOffset() == 0 &&
817 "Do not know what to do with an non-zero offset");
819 // TODO: We could emit code to handle the initialization somewhere.
820 if (hasDefinedInitializer(GV))
824 if (MFI->LocalMemoryObjects.count(GV) == 0) {
825 uint64_t Size = DL.getTypeAllocSize(GV->getType()->getElementType());
826 Offset = MFI->LDSSize;
827 MFI->LocalMemoryObjects[GV] = Offset;
828 // XXX: Account for alignment?
829 MFI->LDSSize += Size;
831 Offset = MFI->LocalMemoryObjects[GV];
834 return DAG.getConstant(Offset, SDLoc(Op),
835 getPointerTy(DL, AMDGPUAS::LOCAL_ADDRESS));
837 case AMDGPUAS::CONSTANT_ADDRESS: {
838 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
839 Type *EltType = GV->getType()->getElementType();
840 unsigned Size = DL.getTypeAllocSize(EltType);
841 unsigned Alignment = DL.getPrefTypeAlignment(EltType);
843 MVT PrivPtrVT = getPointerTy(DL, AMDGPUAS::PRIVATE_ADDRESS);
844 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
846 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
847 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
849 const GlobalVariable *Var = cast<GlobalVariable>(GV);
850 if (!Var->hasInitializer()) {
851 // This has no use, but bugpoint will hit it.
852 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
855 const Constant *Init = Var->getInitializer();
856 SmallVector<SDNode*, 8> WorkList;
858 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
859 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
860 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
862 WorkList.push_back(*I);
864 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
865 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
866 E = WorkList.end(); I != E; ++I) {
867 SmallVector<SDValue, 8> Ops;
868 Ops.push_back(Chain);
869 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
870 Ops.push_back((*I)->getOperand(i));
872 DAG.UpdateNodeOperands(*I, Ops);
874 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
878 const Function &Fn = *DAG.getMachineFunction().getFunction();
879 DiagnosticInfoUnsupported BadInit(Fn,
880 "initializer for address space");
881 DAG.getContext()->diagnose(BadInit);
885 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
886 SelectionDAG &DAG) const {
887 SmallVector<SDValue, 8> Args;
889 for (const SDUse &U : Op->ops())
890 DAG.ExtractVectorElements(U.get(), Args);
892 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
895 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
896 SelectionDAG &DAG) const {
898 SmallVector<SDValue, 8> Args;
899 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
900 EVT VT = Op.getValueType();
901 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
902 VT.getVectorNumElements());
904 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
907 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
908 SelectionDAG &DAG) const {
910 MachineFunction &MF = DAG.getMachineFunction();
911 const AMDGPUFrameLowering *TFL = Subtarget->getFrameLowering();
913 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
915 unsigned FrameIndex = FIN->getIndex();
916 unsigned IgnoredFrameReg;
918 TFL->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
919 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), SDLoc(Op),
923 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
924 SelectionDAG &DAG) const {
925 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
927 EVT VT = Op.getValueType();
929 switch (IntrinsicID) {
931 case AMDGPUIntrinsic::AMDGPU_abs:
932 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
933 return LowerIntrinsicIABS(Op, DAG);
934 case AMDGPUIntrinsic::AMDGPU_lrp:
935 return LowerIntrinsicLRP(Op, DAG);
937 case AMDGPUIntrinsic::AMDGPU_clamp:
938 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
939 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
940 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
942 case Intrinsic::AMDGPU_div_scale: {
943 // 3rd parameter required to be a constant.
944 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
946 return DAG.getUNDEF(VT);
948 // Translate to the operands expected by the machine instruction. The
949 // first parameter must be the same as the first instruction.
950 SDValue Numerator = Op.getOperand(1);
951 SDValue Denominator = Op.getOperand(2);
953 // Note this order is opposite of the machine instruction's operations,
954 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
955 // intrinsic has the numerator as the first operand to match a normal
956 // division operation.
958 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
960 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
961 Denominator, Numerator);
964 case Intrinsic::AMDGPU_div_fmas:
965 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
966 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
969 case Intrinsic::AMDGPU_div_fixup:
970 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
971 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
973 case Intrinsic::AMDGPU_trig_preop:
974 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
975 Op.getOperand(1), Op.getOperand(2));
977 case Intrinsic::AMDGPU_rcp:
978 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
980 case Intrinsic::AMDGPU_rsq:
981 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
983 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
984 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
986 case Intrinsic::AMDGPU_rsq_clamped:
987 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
988 Type *Type = VT.getTypeForEVT(*DAG.getContext());
989 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
990 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
992 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
993 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
994 DAG.getConstantFP(Max, DL, VT));
995 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
996 DAG.getConstantFP(Min, DL, VT));
998 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
1001 case Intrinsic::AMDGPU_ldexp:
1002 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
1005 case AMDGPUIntrinsic::AMDGPU_imax:
1006 return DAG.getNode(ISD::SMAX, DL, VT, Op.getOperand(1),
1008 case AMDGPUIntrinsic::AMDGPU_umax:
1009 return DAG.getNode(ISD::UMAX, DL, VT, Op.getOperand(1),
1011 case AMDGPUIntrinsic::AMDGPU_imin:
1012 return DAG.getNode(ISD::SMIN, DL, VT, Op.getOperand(1),
1014 case AMDGPUIntrinsic::AMDGPU_umin:
1015 return DAG.getNode(ISD::UMIN, DL, VT, Op.getOperand(1),
1018 case AMDGPUIntrinsic::AMDGPU_umul24:
1019 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
1020 Op.getOperand(1), Op.getOperand(2));
1022 case AMDGPUIntrinsic::AMDGPU_imul24:
1023 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
1024 Op.getOperand(1), Op.getOperand(2));
1026 case AMDGPUIntrinsic::AMDGPU_umad24:
1027 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
1028 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
1030 case AMDGPUIntrinsic::AMDGPU_imad24:
1031 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
1032 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
1034 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
1035 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
1037 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
1038 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
1040 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
1041 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
1043 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
1044 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
1046 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
1047 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
1052 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
1053 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
1058 case AMDGPUIntrinsic::AMDGPU_bfi:
1059 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
1064 case AMDGPUIntrinsic::AMDGPU_bfm:
1065 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
1069 case AMDGPUIntrinsic::AMDGPU_brev:
1070 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
1072 case Intrinsic::AMDGPU_class:
1073 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
1074 Op.getOperand(1), Op.getOperand(2));
1076 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
1077 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
1079 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
1080 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
1081 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
1082 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
1086 ///IABS(a) = SMAX(sub(0, a), a)
1087 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
1088 SelectionDAG &DAG) const {
1090 EVT VT = Op.getValueType();
1091 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1094 return DAG.getNode(ISD::SMAX, DL, VT, Neg, Op.getOperand(1));
1097 /// Linear Interpolation
1098 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
1099 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
1100 SelectionDAG &DAG) const {
1102 EVT VT = Op.getValueType();
1103 // TODO: Should this propagate fast-math-flags?
1104 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
1105 DAG.getConstantFP(1.0f, DL, MVT::f32),
1107 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
1109 return DAG.getNode(ISD::FADD, DL, VT,
1110 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
1114 /// \brief Generate Min/Max node
1115 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,
1122 DAGCombinerInfo &DCI) const {
1123 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1126 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1129 SelectionDAG &DAG = DCI.DAG;
1130 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1139 case ISD::SETFALSE2:
1148 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1149 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1155 // Ordered. Assume ordered for undefined.
1157 // Only do this after legalization to avoid interfering with other combines
1158 // which might occur.
1159 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1160 !DCI.isCalledByLegalizer())
1163 // We need to permute the operands to get the correct NaN behavior. The
1164 // selected operand is the second one based on the failing compare with NaN,
1165 // so permute it based on the compare type the hardware uses.
1167 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1168 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1173 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1174 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1180 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1181 !DCI.isCalledByLegalizer())
1185 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1186 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1188 case ISD::SETCC_INVALID:
1189 llvm_unreachable("Invalid setcc condcode!");
1194 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1195 SelectionDAG &DAG) const {
1196 LoadSDNode *Load = cast<LoadSDNode>(Op);
1197 EVT MemVT = Load->getMemoryVT();
1198 EVT MemEltVT = MemVT.getVectorElementType();
1200 EVT LoadVT = Op.getValueType();
1201 EVT EltVT = LoadVT.getVectorElementType();
1202 EVT PtrVT = Load->getBasePtr().getValueType();
1204 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1205 SmallVector<SDValue, 8> Loads;
1206 SmallVector<SDValue, 8> Chains;
1209 unsigned MemEltSize = MemEltVT.getStoreSize();
1210 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1212 for (unsigned i = 0; i < NumElts; ++i) {
1213 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1214 DAG.getConstant(i * MemEltSize, SL, PtrVT));
1217 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1218 Load->getChain(), Ptr,
1219 SrcValue.getWithOffset(i * MemEltSize),
1220 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1221 Load->isInvariant(), Load->getAlignment());
1222 Loads.push_back(NewLoad.getValue(0));
1223 Chains.push_back(NewLoad.getValue(1));
1227 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1228 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1231 return DAG.getMergeValues(Ops, SL);
1234 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1235 SelectionDAG &DAG) const {
1236 EVT VT = Op.getValueType();
1238 // If this is a 2 element vector, we really want to scalarize and not create
1239 // weird 1 element vectors.
1240 if (VT.getVectorNumElements() == 2)
1241 return ScalarizeVectorLoad(Op, DAG);
1243 LoadSDNode *Load = cast<LoadSDNode>(Op);
1244 SDValue BasePtr = Load->getBasePtr();
1245 EVT PtrVT = BasePtr.getValueType();
1246 EVT MemVT = Load->getMemoryVT();
1248 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1251 EVT LoMemVT, HiMemVT;
1254 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1255 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1256 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1258 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1259 Load->getChain(), BasePtr,
1261 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1262 Load->isInvariant(), Load->getAlignment());
1264 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1265 DAG.getConstant(LoMemVT.getStoreSize(), SL,
1269 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1270 Load->getChain(), HiPtr,
1271 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1272 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1273 Load->isInvariant(), Load->getAlignment());
1276 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1277 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1278 LoLoad.getValue(1), HiLoad.getValue(1))
1281 return DAG.getMergeValues(Ops, SL);
1284 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1285 SelectionDAG &DAG) const {
1286 StoreSDNode *Store = cast<StoreSDNode>(Op);
1287 EVT MemVT = Store->getMemoryVT();
1288 unsigned MemBits = MemVT.getSizeInBits();
1290 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1291 // truncating store into an i32 store.
1292 // XXX: We could also handle optimize other vector bitwidths.
1293 if (!MemVT.isVector() || MemBits > 32) {
1298 SDValue Value = Store->getValue();
1299 EVT VT = Value.getValueType();
1300 EVT ElemVT = VT.getVectorElementType();
1301 SDValue Ptr = Store->getBasePtr();
1302 EVT MemEltVT = MemVT.getVectorElementType();
1303 unsigned MemEltBits = MemEltVT.getSizeInBits();
1304 unsigned MemNumElements = MemVT.getVectorNumElements();
1305 unsigned PackedSize = MemVT.getStoreSizeInBits();
1306 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, DL, MVT::i32);
1308 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1310 SDValue PackedValue;
1311 for (unsigned i = 0; i < MemNumElements; ++i) {
1312 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1313 DAG.getConstant(i, DL, MVT::i32));
1314 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1315 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1317 SDValue Shift = DAG.getConstant(MemEltBits * i, DL, MVT::i32);
1318 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1323 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1327 if (PackedSize < 32) {
1328 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1329 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1330 Store->getMemOperand()->getPointerInfo(),
1332 Store->isNonTemporal(), Store->isVolatile(),
1333 Store->getAlignment());
1336 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1337 Store->getMemOperand()->getPointerInfo(),
1338 Store->isVolatile(), Store->isNonTemporal(),
1339 Store->getAlignment());
1342 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1343 SelectionDAG &DAG) const {
1344 StoreSDNode *Store = cast<StoreSDNode>(Op);
1345 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1346 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1347 EVT PtrVT = Store->getBasePtr().getValueType();
1348 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1351 SmallVector<SDValue, 8> Chains;
1353 unsigned EltSize = MemEltVT.getStoreSize();
1354 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1356 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1357 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1359 DAG.getConstant(i, SL, MVT::i32));
1361 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), SL, PtrVT);
1362 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1364 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1365 SrcValue.getWithOffset(i * EltSize),
1366 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1367 Store->getAlignment());
1368 Chains.push_back(NewStore);
1371 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1374 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1375 SelectionDAG &DAG) const {
1376 StoreSDNode *Store = cast<StoreSDNode>(Op);
1377 SDValue Val = Store->getValue();
1378 EVT VT = Val.getValueType();
1380 // If this is a 2 element vector, we really want to scalarize and not create
1381 // weird 1 element vectors.
1382 if (VT.getVectorNumElements() == 2)
1383 return ScalarizeVectorStore(Op, DAG);
1385 EVT MemVT = Store->getMemoryVT();
1386 SDValue Chain = Store->getChain();
1387 SDValue BasePtr = Store->getBasePtr();
1391 EVT LoMemVT, HiMemVT;
1394 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1395 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1396 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1398 EVT PtrVT = BasePtr.getValueType();
1399 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1400 DAG.getConstant(LoMemVT.getStoreSize(), SL,
1403 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1405 = DAG.getTruncStore(Chain, SL, Lo,
1409 Store->isNonTemporal(),
1410 Store->isVolatile(),
1411 Store->getAlignment());
1413 = DAG.getTruncStore(Chain, SL, Hi,
1415 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1417 Store->isNonTemporal(),
1418 Store->isVolatile(),
1419 Store->getAlignment());
1421 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1425 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1427 LoadSDNode *Load = cast<LoadSDNode>(Op);
1428 ISD::LoadExtType ExtType = Load->getExtensionType();
1429 EVT VT = Op.getValueType();
1430 EVT MemVT = Load->getMemoryVT();
1432 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1433 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1434 // FIXME: Copied from PPC
1435 // First, load into 32 bits, then truncate to 1 bit.
1437 SDValue Chain = Load->getChain();
1438 SDValue BasePtr = Load->getBasePtr();
1439 MachineMemOperand *MMO = Load->getMemOperand();
1441 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1442 BasePtr, MVT::i8, MMO);
1445 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1449 return DAG.getMergeValues(Ops, DL);
1452 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1453 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1454 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1457 // <SI && AS=PRIVATE && EXTLOAD && size < 32bit,
1458 // register (2-)byte extract.
1460 // Get Register holding the target.
1461 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1462 DAG.getConstant(2, DL, MVT::i32));
1463 // Load the Register.
1464 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1465 Load->getChain(), Ptr,
1466 DAG.getTargetConstant(0, DL, MVT::i32),
1469 // Get offset within the register.
1470 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1472 DAG.getConstant(0x3, DL, MVT::i32));
1474 // Bit offset of target byte (byteIdx * 8).
1475 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1476 DAG.getConstant(3, DL, MVT::i32));
1478 // Shift to the right.
1479 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1481 // Eliminate the upper bits by setting them to ...
1482 EVT MemEltVT = MemVT.getScalarType();
1485 if (ExtType == ISD::SEXTLOAD) {
1486 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1489 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1493 return DAG.getMergeValues(Ops, DL);
1498 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1502 return DAG.getMergeValues(Ops, DL);
1505 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1507 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1508 if (Result.getNode()) {
1512 StoreSDNode *Store = cast<StoreSDNode>(Op);
1513 SDValue Chain = Store->getChain();
1514 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1515 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1516 Store->getValue().getValueType().isVector()) {
1517 return ScalarizeVectorStore(Op, DAG);
1520 EVT MemVT = Store->getMemoryVT();
1521 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1522 MemVT.bitsLT(MVT::i32)) {
1524 if (Store->getMemoryVT() == MVT::i8) {
1526 } else if (Store->getMemoryVT() == MVT::i16) {
1529 SDValue BasePtr = Store->getBasePtr();
1530 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1531 DAG.getConstant(2, DL, MVT::i32));
1532 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1534 DAG.getTargetConstant(0, DL, MVT::i32));
1536 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1537 DAG.getConstant(0x3, DL, MVT::i32));
1539 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1540 DAG.getConstant(3, DL, MVT::i32));
1542 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1545 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1547 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1548 MaskedValue, ShiftAmt);
1550 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32,
1551 DAG.getConstant(Mask, DL, MVT::i32),
1553 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1554 DAG.getConstant(0xffffffff, DL, MVT::i32));
1555 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1557 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1558 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1560 DAG.getTargetConstant(0, DL, MVT::i32));
1565 // This is a shortcut for integer division because we have fast i32<->f32
1566 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1567 // float is enough to accurately represent up to a 24-bit integer.
1568 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1570 EVT VT = Op.getValueType();
1571 SDValue LHS = Op.getOperand(0);
1572 SDValue RHS = Op.getOperand(1);
1573 MVT IntVT = MVT::i32;
1574 MVT FltVT = MVT::f32;
1576 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1577 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1579 if (VT.isVector()) {
1580 unsigned NElts = VT.getVectorNumElements();
1581 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1582 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1585 unsigned BitSize = VT.getScalarType().getSizeInBits();
1587 SDValue jq = DAG.getConstant(1, DL, IntVT);
1590 // char|short jq = ia ^ ib;
1591 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1593 // jq = jq >> (bitsize - 2)
1594 jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1595 DAG.getConstant(BitSize - 2, DL, VT));
1598 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1601 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1604 // int ia = (int)LHS;
1606 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1608 // int ib, (int)RHS;
1610 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1612 // float fa = (float)ia;
1613 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1615 // float fb = (float)ib;
1616 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1618 // TODO: Should this propagate fast-math-flags?
1619 // float fq = native_divide(fa, fb);
1620 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1621 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1624 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1626 // float fqneg = -fq;
1627 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1629 // float fr = mad(fqneg, fb, fa);
1630 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1631 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1633 // int iq = (int)fq;
1634 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1637 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1640 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1642 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1644 // int cv = fr >= fb;
1645 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1647 // jq = (cv ? jq : 0);
1648 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1650 // dst = trunc/extend to legal type
1651 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1654 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1656 // Rem needs compensation, it's easier to recompute it
1657 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1658 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1664 return DAG.getMergeValues(Res, DL);
1667 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1669 SmallVectorImpl<SDValue> &Results) const {
1670 assert(Op.getValueType() == MVT::i64);
1673 EVT VT = Op.getValueType();
1674 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1676 SDValue one = DAG.getConstant(1, DL, HalfVT);
1677 SDValue zero = DAG.getConstant(0, DL, HalfVT);
1680 SDValue LHS = Op.getOperand(0);
1681 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
1682 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
1684 SDValue RHS = Op.getOperand(1);
1685 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
1686 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
1688 if (VT == MVT::i64 &&
1689 DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1690 DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1692 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1695 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(0), zero);
1696 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(1), zero);
1697 Results.push_back(DIV);
1698 Results.push_back(REM);
1702 // Get Speculative values
1703 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1704 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1706 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
1707 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, zero);
1709 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
1710 SDValue DIV_Lo = zero;
1712 const unsigned halfBitWidth = HalfVT.getSizeInBits();
1714 for (unsigned i = 0; i < halfBitWidth; ++i) {
1715 const unsigned bitPos = halfBitWidth - i - 1;
1716 SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
1717 // Get value of high bit
1718 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1719 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
1720 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1723 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
1725 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1727 SDValue BIT = DAG.getConstant(1 << bitPos, DL, HalfVT);
1728 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
1730 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1733 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1734 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1737 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
1738 Results.push_back(DIV);
1739 Results.push_back(REM);
1742 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1743 SelectionDAG &DAG) const {
1745 EVT VT = Op.getValueType();
1747 if (VT == MVT::i64) {
1748 SmallVector<SDValue, 2> Results;
1749 LowerUDIVREM64(Op, DAG, Results);
1750 return DAG.getMergeValues(Results, DL);
1753 SDValue Num = Op.getOperand(0);
1754 SDValue Den = Op.getOperand(1);
1756 if (VT == MVT::i32) {
1757 if (DAG.MaskedValueIsZero(Num, APInt::getHighBitsSet(32, 8)) &&
1758 DAG.MaskedValueIsZero(Den, APInt::getHighBitsSet(32, 8))) {
1759 // TODO: We technically could do this for i64, but shouldn't that just be
1760 // handled by something generally reducing 64-bit division on 32-bit
1761 // values to 32-bit?
1762 return LowerDIVREM24(Op, DAG, false);
1766 // RCP = URECIP(Den) = 2^32 / Den + e
1767 // e is rounding error.
1768 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1770 // RCP_LO = mul(RCP, Den) */
1771 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1773 // RCP_HI = mulhu (RCP, Den) */
1774 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1776 // NEG_RCP_LO = -RCP_LO
1777 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1780 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1781 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1784 // Calculate the rounding error from the URECIP instruction
1785 // E = mulhu(ABS_RCP_LO, RCP)
1786 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1788 // RCP_A_E = RCP + E
1789 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1791 // RCP_S_E = RCP - E
1792 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1794 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1795 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1798 // Quotient = mulhu(Tmp0, Num)
1799 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1801 // Num_S_Remainder = Quotient * Den
1802 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1804 // Remainder = Num - Num_S_Remainder
1805 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1807 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1808 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1809 DAG.getConstant(-1, DL, VT),
1810 DAG.getConstant(0, DL, VT),
1812 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1813 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1815 DAG.getConstant(-1, DL, VT),
1816 DAG.getConstant(0, DL, VT),
1818 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1819 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1822 // Calculate Division result:
1824 // Quotient_A_One = Quotient + 1
1825 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1826 DAG.getConstant(1, DL, VT));
1828 // Quotient_S_One = Quotient - 1
1829 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1830 DAG.getConstant(1, DL, VT));
1832 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1833 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1834 Quotient, Quotient_A_One, ISD::SETEQ);
1836 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1837 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1838 Quotient_S_One, Div, ISD::SETEQ);
1840 // Calculate Rem result:
1842 // Remainder_S_Den = Remainder - Den
1843 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1845 // Remainder_A_Den = Remainder + Den
1846 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1848 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1849 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1850 Remainder, Remainder_S_Den, ISD::SETEQ);
1852 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1853 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1854 Remainder_A_Den, Rem, ISD::SETEQ);
1859 return DAG.getMergeValues(Ops, DL);
1862 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1863 SelectionDAG &DAG) const {
1865 EVT VT = Op.getValueType();
1867 SDValue LHS = Op.getOperand(0);
1868 SDValue RHS = Op.getOperand(1);
1870 SDValue Zero = DAG.getConstant(0, DL, VT);
1871 SDValue NegOne = DAG.getConstant(-1, DL, VT);
1873 if (VT == MVT::i32 &&
1874 DAG.ComputeNumSignBits(LHS) > 8 &&
1875 DAG.ComputeNumSignBits(RHS) > 8) {
1876 return LowerDIVREM24(Op, DAG, true);
1878 if (VT == MVT::i64 &&
1879 DAG.ComputeNumSignBits(LHS) > 32 &&
1880 DAG.ComputeNumSignBits(RHS) > 32) {
1881 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1884 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1885 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1886 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1889 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1890 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1892 return DAG.getMergeValues(Res, DL);
1895 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1896 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1897 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1898 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1900 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1901 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1903 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1904 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1906 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1907 SDValue Rem = Div.getValue(1);
1909 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1910 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1912 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1913 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1919 return DAG.getMergeValues(Res, DL);
1922 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1923 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1925 EVT VT = Op.getValueType();
1926 SDValue X = Op.getOperand(0);
1927 SDValue Y = Op.getOperand(1);
1929 // TODO: Should this propagate fast-math-flags?
1931 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1932 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1933 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1935 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1938 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1940 SDValue Src = Op.getOperand(0);
1942 // result = trunc(src)
1943 // if (src > 0.0 && src != result)
1946 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1948 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
1949 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1952 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
1954 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1955 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1956 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1958 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1959 // TODO: Should this propagate fast-math-flags?
1960 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1963 static SDValue extractF64Exponent(SDValue Hi, SDLoc SL, SelectionDAG &DAG) {
1964 const unsigned FractBits = 52;
1965 const unsigned ExpBits = 11;
1967 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1969 DAG.getConstant(FractBits - 32, SL, MVT::i32),
1970 DAG.getConstant(ExpBits, SL, MVT::i32));
1971 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1972 DAG.getConstant(1023, SL, MVT::i32));
1977 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1979 SDValue Src = Op.getOperand(0);
1981 assert(Op.getValueType() == MVT::f64);
1983 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1984 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1986 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1988 // Extract the upper half, since this is where we will find the sign and
1990 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1992 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
1994 const unsigned FractBits = 52;
1996 // Extract the sign bit.
1997 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32);
1998 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
2000 // Extend back to to 64-bits.
2001 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
2003 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
2005 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
2006 const SDValue FractMask
2007 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64);
2009 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
2010 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
2011 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
2014 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2016 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
2018 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2019 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2021 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
2022 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
2024 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
2027 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
2029 SDValue Src = Op.getOperand(0);
2031 assert(Op.getValueType() == MVT::f64);
2033 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
2034 SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
2035 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2037 // TODO: Should this propagate fast-math-flags?
2039 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2040 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2042 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2044 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
2045 SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
2048 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2049 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2051 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2054 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2055 // FNEARBYINT and FRINT are the same, except in their handling of FP
2056 // exceptions. Those aren't really meaningful for us, and OpenCL only has
2057 // rint, so just treat them as equivalent.
2058 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2061 // XXX - May require not supporting f32 denormals?
2062 SDValue AMDGPUTargetLowering::LowerFROUND32(SDValue Op, SelectionDAG &DAG) const {
2064 SDValue X = Op.getOperand(0);
2066 SDValue T = DAG.getNode(ISD::FTRUNC, SL, MVT::f32, X);
2068 // TODO: Should this propagate fast-math-flags?
2070 SDValue Diff = DAG.getNode(ISD::FSUB, SL, MVT::f32, X, T);
2072 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff);
2074 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f32);
2075 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
2076 const SDValue Half = DAG.getConstantFP(0.5, SL, MVT::f32);
2078 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f32, One, X);
2081 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
2083 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2085 SDValue Sel = DAG.getNode(ISD::SELECT, SL, MVT::f32, Cmp, SignOne, Zero);
2087 return DAG.getNode(ISD::FADD, SL, MVT::f32, T, Sel);
2090 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
2092 SDValue X = Op.getOperand(0);
2094 SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
2096 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2097 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2098 const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
2099 const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
2101 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2103 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2105 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
2107 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2109 const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL,
2112 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2113 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2114 DAG.getConstant(INT64_C(0x0008000000000000), SL,
2118 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2119 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
2120 DAG.getConstant(0, SL, MVT::i64), Tmp0,
2123 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2124 D, DAG.getConstant(0, SL, MVT::i64));
2125 SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
2127 K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2128 K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
2130 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2131 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2132 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
2134 SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
2136 DAG.getConstantFP(1.0, SL, MVT::f64),
2137 DAG.getConstantFP(0.0, SL, MVT::f64));
2139 SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
2141 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
2142 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
2147 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2148 EVT VT = Op.getValueType();
2151 return LowerFROUND32(Op, DAG);
2154 return LowerFROUND64(Op, DAG);
2156 llvm_unreachable("unhandled type");
2159 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2161 SDValue Src = Op.getOperand(0);
2163 // result = trunc(src);
2164 // if (src < 0.0 && src != result)
2167 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2169 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2170 const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
2173 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2175 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2176 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2177 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2179 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2180 // TODO: Should this propagate fast-math-flags?
2181 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2184 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2185 bool Signed) const {
2187 SDValue Src = Op.getOperand(0);
2189 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2191 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2192 DAG.getConstant(0, SL, MVT::i32));
2193 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2194 DAG.getConstant(1, SL, MVT::i32));
2196 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2199 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2201 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2202 DAG.getConstant(32, SL, MVT::i32));
2203 // TODO: Should this propagate fast-math-flags?
2204 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2207 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2208 SelectionDAG &DAG) const {
2209 SDValue S0 = Op.getOperand(0);
2210 if (S0.getValueType() != MVT::i64)
2213 EVT DestVT = Op.getValueType();
2214 if (DestVT == MVT::f64)
2215 return LowerINT_TO_FP64(Op, DAG, false);
2217 assert(DestVT == MVT::f32);
2221 // f32 uint_to_fp i64
2222 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2223 DAG.getConstant(0, DL, MVT::i32));
2224 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
2225 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2226 DAG.getConstant(1, DL, MVT::i32));
2227 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
2228 // TODO: Should this propagate fast-math-flags?
2229 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
2230 DAG.getConstantFP(4294967296.0f, DL, MVT::f32)); // 2^32
2231 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
2234 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2235 SelectionDAG &DAG) const {
2236 SDValue Src = Op.getOperand(0);
2237 if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64)
2238 return LowerINT_TO_FP64(Op, DAG, true);
2243 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2244 bool Signed) const {
2247 SDValue Src = Op.getOperand(0);
2249 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2251 SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL,
2253 SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL,
2255 // TODO: Should this propagate fast-math-flags?
2256 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2258 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2261 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2263 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2264 MVT::i32, FloorMul);
2265 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2267 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
2269 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2272 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2273 SelectionDAG &DAG) const {
2274 SDValue Src = Op.getOperand(0);
2276 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2277 return LowerFP64_TO_INT(Op, DAG, true);
2282 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2283 SelectionDAG &DAG) const {
2284 SDValue Src = Op.getOperand(0);
2286 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2287 return LowerFP64_TO_INT(Op, DAG, false);
2292 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2293 SelectionDAG &DAG) const {
2294 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2295 MVT VT = Op.getSimpleValueType();
2296 MVT ScalarVT = VT.getScalarType();
2301 SDValue Src = Op.getOperand(0);
2304 // TODO: Don't scalarize on Evergreen?
2305 unsigned NElts = VT.getVectorNumElements();
2306 SmallVector<SDValue, 8> Args;
2307 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2309 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2310 for (unsigned I = 0; I < NElts; ++I)
2311 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2313 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
2316 //===----------------------------------------------------------------------===//
2317 // Custom DAG optimizations
2318 //===----------------------------------------------------------------------===//
2320 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2321 APInt KnownZero, KnownOne;
2322 EVT VT = Op.getValueType();
2323 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2325 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2328 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2329 EVT VT = Op.getValueType();
2331 // In order for this to be a signed 24-bit value, bit 23, must
2333 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2334 // as unsigned 24-bit values.
2335 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2338 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2340 SelectionDAG &DAG = DCI.DAG;
2341 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2342 EVT VT = Op.getValueType();
2344 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2345 APInt KnownZero, KnownOne;
2346 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2347 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2348 DCI.CommitTargetLoweringOpt(TLO);
2351 template <typename IntTy>
2352 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
2353 uint32_t Offset, uint32_t Width, SDLoc DL) {
2354 if (Width + Offset < 32) {
2355 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2356 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2357 return DAG.getConstant(Result, DL, MVT::i32);
2360 return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2363 static bool usesAllNormalStores(SDNode *LoadVal) {
2364 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2365 if (!ISD::isNormalStore(*I))
2372 // If we have a copy of an illegal type, replace it with a load / store of an
2373 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2374 // instructions emitted when handling extloads and truncstores. Ideally we could
2375 // recognize the pack / unpack pattern to eliminate it.
2376 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2377 DAGCombinerInfo &DCI) const {
2378 if (!DCI.isBeforeLegalize())
2381 StoreSDNode *SN = cast<StoreSDNode>(N);
2382 SDValue Value = SN->getValue();
2383 EVT VT = Value.getValueType();
2385 if (isTypeLegal(VT) || SN->isVolatile() ||
2386 !ISD::isNormalLoad(Value.getNode()) || VT.getSizeInBits() < 8)
2389 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2390 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2393 EVT MemVT = LoadVal->getMemoryVT();
2396 SelectionDAG &DAG = DCI.DAG;
2397 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2399 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2401 LoadVal->getChain(),
2402 LoadVal->getBasePtr(),
2403 LoadVal->getOffset(),
2405 LoadVal->getMemOperand());
2407 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2408 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2410 return DAG.getStore(SN->getChain(), SL, NewLoad,
2411 SN->getBasePtr(), SN->getMemOperand());
2414 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
2415 DAGCombinerInfo &DCI) const {
2416 if (N->getValueType(0) != MVT::i64)
2419 // i64 (shl x, 32) -> (build_pair 0, x)
2421 // Doing this with moves theoretically helps MI optimizations that understand
2422 // copies. 2 v_mov_b32_e32 will have the same code size / cycle count as
2423 // v_lshl_b64. In the SALU case, I think this is slightly worse since it
2424 // doubles the code size and I'm unsure about cycle count.
2425 const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2426 if (!RHS || RHS->getZExtValue() != 32)
2429 SDValue LHS = N->getOperand(0);
2432 SelectionDAG &DAG = DCI.DAG;
2434 // Extract low 32-bits.
2435 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
2437 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2438 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, Zero, Lo);
2441 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2442 DAGCombinerInfo &DCI) const {
2443 EVT VT = N->getValueType(0);
2445 if (VT.isVector() || VT.getSizeInBits() > 32)
2448 SelectionDAG &DAG = DCI.DAG;
2451 SDValue N0 = N->getOperand(0);
2452 SDValue N1 = N->getOperand(1);
2455 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2456 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2457 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2458 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2459 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2460 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2461 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2462 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2467 // We need to use sext even for MUL_U24, because MUL_U24 is used
2468 // for signed multiply of 8 and 16-bit types.
2469 return DAG.getSExtOrTrunc(Mul, DL, VT);
2472 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2473 DAGCombinerInfo &DCI) const {
2474 SelectionDAG &DAG = DCI.DAG;
2477 switch(N->getOpcode()) {
2481 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2484 return performShlCombine(N, DCI);
2487 return performMulCombine(N, DCI);
2488 case AMDGPUISD::MUL_I24:
2489 case AMDGPUISD::MUL_U24: {
2490 SDValue N0 = N->getOperand(0);
2491 SDValue N1 = N->getOperand(1);
2492 simplifyI24(N0, DCI);
2493 simplifyI24(N1, DCI);
2497 SDValue Cond = N->getOperand(0);
2498 if (Cond.getOpcode() == ISD::SETCC && Cond.hasOneUse()) {
2499 EVT VT = N->getValueType(0);
2500 SDValue LHS = Cond.getOperand(0);
2501 SDValue RHS = Cond.getOperand(1);
2502 SDValue CC = Cond.getOperand(2);
2504 SDValue True = N->getOperand(1);
2505 SDValue False = N->getOperand(2);
2508 return CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
2513 case AMDGPUISD::BFE_I32:
2514 case AMDGPUISD::BFE_U32: {
2515 assert(!N->getValueType(0).isVector() &&
2516 "Vector handling of BFE not implemented");
2517 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2521 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2523 return DAG.getConstant(0, DL, MVT::i32);
2525 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2529 SDValue BitsFrom = N->getOperand(0);
2530 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2532 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2534 if (OffsetVal == 0) {
2535 // This is already sign / zero extended, so try to fold away extra BFEs.
2536 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2538 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2539 if (OpSignBits >= SignBits)
2542 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2544 // This is a sign_extend_inreg. Replace it to take advantage of existing
2545 // DAG Combines. If not eliminated, we will match back to BFE during
2548 // TODO: The sext_inreg of extended types ends, although we can could
2549 // handle them in a single BFE.
2550 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2551 DAG.getValueType(SmallVT));
2554 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2557 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2559 return constantFoldBFE<int32_t>(DAG,
2560 CVal->getSExtValue(),
2566 return constantFoldBFE<uint32_t>(DAG,
2567 CVal->getZExtValue(),
2573 if ((OffsetVal + WidthVal) >= 32) {
2574 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
2575 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2576 BitsFrom, ShiftVal);
2579 if (BitsFrom.hasOneUse()) {
2580 APInt Demanded = APInt::getBitsSet(32,
2582 OffsetVal + WidthVal);
2584 APInt KnownZero, KnownOne;
2585 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2586 !DCI.isBeforeLegalizeOps());
2587 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2588 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2589 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2590 KnownZero, KnownOne, TLO)) {
2591 DCI.CommitTargetLoweringOpt(TLO);
2599 return performStoreCombine(N, DCI);
2604 //===----------------------------------------------------------------------===//
2606 //===----------------------------------------------------------------------===//
2608 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2611 const SmallVectorImpl<ISD::InputArg> &Ins,
2612 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2614 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2615 if (Ins[i].ArgVT == Ins[i].VT) {
2616 OrigIns.push_back(Ins[i]);
2621 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2622 // Vector has been split into scalars.
2623 VT = Ins[i].ArgVT.getVectorElementType();
2624 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2625 Ins[i].ArgVT.getVectorElementType() !=
2626 Ins[i].VT.getVectorElementType()) {
2627 // Vector elements have been promoted
2630 // Vector has been spilt into smaller vectors.
2634 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2635 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2636 OrigIns.push_back(Arg);
2640 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2641 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2642 return CFP->isExactlyValue(1.0);
2644 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2645 return C->isAllOnesValue();
2650 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2651 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2652 return CFP->getValueAPF().isZero();
2654 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2655 return C->isNullValue();
2660 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2661 const TargetRegisterClass *RC,
2662 unsigned Reg, EVT VT) const {
2663 MachineFunction &MF = DAG.getMachineFunction();
2664 MachineRegisterInfo &MRI = MF.getRegInfo();
2665 unsigned VirtualRegister;
2666 if (!MRI.isLiveIn(Reg)) {
2667 VirtualRegister = MRI.createVirtualRegister(RC);
2668 MRI.addLiveIn(Reg, VirtualRegister);
2670 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2672 return DAG.getRegister(VirtualRegister, VT);
2675 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
2676 const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const {
2677 uint64_t ArgOffset = MFI->ABIArgOffset;
2682 return ArgOffset + 4;
2684 llvm_unreachable("unexpected implicit parameter type");
2687 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2689 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2690 switch ((AMDGPUISD::NodeType)Opcode) {
2691 case AMDGPUISD::FIRST_NUMBER: break;
2693 NODE_NAME_CASE(CALL);
2694 NODE_NAME_CASE(UMUL);
2695 NODE_NAME_CASE(RET_FLAG);
2696 NODE_NAME_CASE(BRANCH_COND);
2699 NODE_NAME_CASE(DWORDADDR)
2700 NODE_NAME_CASE(FRACT)
2701 NODE_NAME_CASE(CLAMP)
2702 NODE_NAME_CASE(COS_HW)
2703 NODE_NAME_CASE(SIN_HW)
2704 NODE_NAME_CASE(FMAX_LEGACY)
2705 NODE_NAME_CASE(FMIN_LEGACY)
2706 NODE_NAME_CASE(FMAX3)
2707 NODE_NAME_CASE(SMAX3)
2708 NODE_NAME_CASE(UMAX3)
2709 NODE_NAME_CASE(FMIN3)
2710 NODE_NAME_CASE(SMIN3)
2711 NODE_NAME_CASE(UMIN3)
2712 NODE_NAME_CASE(URECIP)
2713 NODE_NAME_CASE(DIV_SCALE)
2714 NODE_NAME_CASE(DIV_FMAS)
2715 NODE_NAME_CASE(DIV_FIXUP)
2716 NODE_NAME_CASE(TRIG_PREOP)
2719 NODE_NAME_CASE(RSQ_LEGACY)
2720 NODE_NAME_CASE(RSQ_CLAMPED)
2721 NODE_NAME_CASE(LDEXP)
2722 NODE_NAME_CASE(FP_CLASS)
2723 NODE_NAME_CASE(DOT4)
2724 NODE_NAME_CASE(CARRY)
2725 NODE_NAME_CASE(BORROW)
2726 NODE_NAME_CASE(BFE_U32)
2727 NODE_NAME_CASE(BFE_I32)
2730 NODE_NAME_CASE(BREV)
2731 NODE_NAME_CASE(MUL_U24)
2732 NODE_NAME_CASE(MUL_I24)
2733 NODE_NAME_CASE(MAD_U24)
2734 NODE_NAME_CASE(MAD_I24)
2735 NODE_NAME_CASE(TEXTURE_FETCH)
2736 NODE_NAME_CASE(EXPORT)
2737 NODE_NAME_CASE(CONST_ADDRESS)
2738 NODE_NAME_CASE(REGISTER_LOAD)
2739 NODE_NAME_CASE(REGISTER_STORE)
2740 NODE_NAME_CASE(LOAD_CONSTANT)
2741 NODE_NAME_CASE(LOAD_INPUT)
2742 NODE_NAME_CASE(SAMPLE)
2743 NODE_NAME_CASE(SAMPLEB)
2744 NODE_NAME_CASE(SAMPLED)
2745 NODE_NAME_CASE(SAMPLEL)
2746 NODE_NAME_CASE(CVT_F32_UBYTE0)
2747 NODE_NAME_CASE(CVT_F32_UBYTE1)
2748 NODE_NAME_CASE(CVT_F32_UBYTE2)
2749 NODE_NAME_CASE(CVT_F32_UBYTE3)
2750 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2751 NODE_NAME_CASE(CONST_DATA_PTR)
2752 case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
2753 NODE_NAME_CASE(SENDMSG)
2754 NODE_NAME_CASE(INTERP_MOV)
2755 NODE_NAME_CASE(INTERP_P1)
2756 NODE_NAME_CASE(INTERP_P2)
2757 NODE_NAME_CASE(STORE_MSKOR)
2758 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2759 case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break;
2764 SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
2765 DAGCombinerInfo &DCI,
2766 unsigned &RefinementSteps,
2767 bool &UseOneConstNR) const {
2768 SelectionDAG &DAG = DCI.DAG;
2769 EVT VT = Operand.getValueType();
2771 if (VT == MVT::f32) {
2772 RefinementSteps = 0;
2773 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
2776 // TODO: There is also f64 rsq instruction, but the documentation is less
2777 // clear on its precision.
2782 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
2783 DAGCombinerInfo &DCI,
2784 unsigned &RefinementSteps) const {
2785 SelectionDAG &DAG = DCI.DAG;
2786 EVT VT = Operand.getValueType();
2788 if (VT == MVT::f32) {
2789 // Reciprocal, < 1 ulp error.
2791 // This reciprocal approximation converges to < 0.5 ulp error with one
2792 // newton rhapson performed with two fused multiple adds (FMAs).
2794 RefinementSteps = 0;
2795 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
2798 // TODO: There is also f64 rcp instruction, but the documentation is less
2799 // clear on its precision.
2804 static void computeKnownBitsForMinMax(const SDValue Op0,
2808 const SelectionDAG &DAG,
2810 APInt Op0Zero, Op0One;
2811 APInt Op1Zero, Op1One;
2812 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2813 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2815 KnownZero = Op0Zero & Op1Zero;
2816 KnownOne = Op0One & Op1One;
2819 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2823 const SelectionDAG &DAG,
2824 unsigned Depth) const {
2826 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2830 unsigned Opc = Op.getOpcode();
2835 case ISD::INTRINSIC_WO_CHAIN: {
2836 // FIXME: The intrinsic should just use the node.
2837 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2838 case AMDGPUIntrinsic::AMDGPU_imax:
2839 case AMDGPUIntrinsic::AMDGPU_umax:
2840 case AMDGPUIntrinsic::AMDGPU_imin:
2841 case AMDGPUIntrinsic::AMDGPU_umin:
2842 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2843 KnownZero, KnownOne, DAG, Depth);
2851 case AMDGPUISD::CARRY:
2852 case AMDGPUISD::BORROW: {
2853 KnownZero = APInt::getHighBitsSet(32, 31);
2857 case AMDGPUISD::BFE_I32:
2858 case AMDGPUISD::BFE_U32: {
2859 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2863 unsigned BitWidth = 32;
2864 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2866 if (Opc == AMDGPUISD::BFE_U32)
2867 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2874 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2876 const SelectionDAG &DAG,
2877 unsigned Depth) const {
2878 switch (Op.getOpcode()) {
2879 case AMDGPUISD::BFE_I32: {
2880 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2884 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2885 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2886 if (!Offset || !Offset->isNullValue())
2889 // TODO: Could probably figure something out with non-0 offsets.
2890 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2891 return std::max(SignBits, Op0SignBits);
2894 case AMDGPUISD::BFE_U32: {
2895 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2896 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
2899 case AMDGPUISD::CARRY:
2900 case AMDGPUISD::BORROW: