1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
40 const Twine &Description;
45 static int getKindID() {
47 KindID = llvm::getNextAvailablePluginDiagnosticKind();
52 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53 DiagnosticSeverity Severity = DS_Error)
54 : DiagnosticInfo(getKindID(), Severity),
58 const Function &getFunction() const { return Fn; }
59 const Twine &getDescription() const { return Description; }
61 void print(DiagnosticPrinter &DP) const override {
62 DP << "unsupported " << getDescription() << " in " << Fn.getName();
65 static bool classof(const DiagnosticInfo *DI) {
66 return DI->getKind() == getKindID();
70 int DiagnosticInfoUnsupported::KindID = 0;
74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75 CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State) {
77 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78 ArgFlags.getOrigAlign());
79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
84 #include "AMDGPUGenCallingConv.inc"
86 // Find a larger type to do a load / store of a vector with.
87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88 unsigned StoreSize = VT.getStoreSizeInBits();
90 return EVT::getIntegerVT(Ctx, StoreSize);
92 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
96 // Type for a vector that will be loaded to.
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98 unsigned StoreSize = VT.getStoreSizeInBits();
100 return EVT::getIntegerVT(Ctx, 32);
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
106 const AMDGPUSubtarget &STI)
107 : TargetLowering(TM), Subtarget(&STI) {
108 setOperationAction(ISD::Constant, MVT::i32, Legal);
109 setOperationAction(ISD::Constant, MVT::i64, Legal);
110 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
111 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
113 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
114 setOperationAction(ISD::BRIND, MVT::Other, Expand);
116 // We need to custom lower some of the intrinsics
117 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
119 // Library functions. These default to Expand, but we have instructions
121 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
122 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
123 setOperationAction(ISD::FPOW, MVT::f32, Legal);
124 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
125 setOperationAction(ISD::FABS, MVT::f32, Legal);
126 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
127 setOperationAction(ISD::FRINT, MVT::f32, Legal);
128 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
129 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
130 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
132 setOperationAction(ISD::FROUND, MVT::f32, Custom);
133 setOperationAction(ISD::FROUND, MVT::f64, Custom);
135 setOperationAction(ISD::FREM, MVT::f32, Custom);
136 setOperationAction(ISD::FREM, MVT::f64, Custom);
138 // v_mad_f32 does not support denormals according to some sources.
139 if (!Subtarget->hasFP32Denormals())
140 setOperationAction(ISD::FMAD, MVT::f32, Legal);
142 // Expand to fneg + fadd.
143 setOperationAction(ISD::FSUB, MVT::f64, Expand);
145 // Lower floating point store/load to integer store/load to reduce the number
146 // of patterns in tablegen.
147 setOperationAction(ISD::STORE, MVT::f32, Promote);
148 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
150 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
151 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
153 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
154 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
156 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
157 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
159 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
160 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
162 setOperationAction(ISD::STORE, MVT::f64, Promote);
163 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
165 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
166 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
168 // Custom lowering of vector stores is required for local address space
170 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
172 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
173 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
174 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
176 // XXX: This can be change to Custom, once ExpandVectorStores can
177 // handle 64-bit stores.
178 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
180 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
181 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
182 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
183 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
184 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
187 setOperationAction(ISD::LOAD, MVT::f32, Promote);
188 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
190 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
193 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
196 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
197 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
199 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
200 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
202 setOperationAction(ISD::LOAD, MVT::f64, Promote);
203 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
205 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
206 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
209 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
210 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
211 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
213 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
216 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
217 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
219 // There are no 64-bit extloads. These should be done as a 32-bit extload and
220 // an extension to 64-bit.
221 for (MVT VT : MVT::integer_valuetypes()) {
222 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
223 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
224 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
227 for (MVT VT : MVT::integer_vector_valuetypes()) {
228 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
229 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
230 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
231 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
232 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
233 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
234 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
235 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
236 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
237 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
238 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
239 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
242 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
244 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
245 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
246 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
247 setOperationAction(ISD::FRINT, MVT::f64, Custom);
248 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
251 if (!Subtarget->hasBFI()) {
252 // fcopysign can be done in a single instruction with BFI.
253 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
254 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
257 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
259 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
260 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
261 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
262 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand);
264 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
265 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
266 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
267 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand);
269 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
270 setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand);
271 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
272 setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand);
274 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
275 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
277 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
278 for (MVT VT : ScalarIntVTs) {
279 setOperationAction(ISD::SREM, VT, Expand);
280 setOperationAction(ISD::SDIV, VT, Expand);
282 // GPU does not have divrem function for signed or unsigned.
283 setOperationAction(ISD::SDIVREM, VT, Custom);
284 setOperationAction(ISD::UDIVREM, VT, Custom);
286 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
287 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
288 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
290 setOperationAction(ISD::BSWAP, VT, Expand);
291 setOperationAction(ISD::CTTZ, VT, Expand);
292 setOperationAction(ISD::CTLZ, VT, Expand);
295 if (!Subtarget->hasBCNT(32))
296 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
298 if (!Subtarget->hasBCNT(64))
299 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
301 // The hardware supports 32-bit ROTR, but not ROTL.
302 setOperationAction(ISD::ROTL, MVT::i32, Expand);
303 setOperationAction(ISD::ROTL, MVT::i64, Expand);
304 setOperationAction(ISD::ROTR, MVT::i64, Expand);
306 setOperationAction(ISD::MUL, MVT::i64, Expand);
307 setOperationAction(ISD::MULHU, MVT::i64, Expand);
308 setOperationAction(ISD::MULHS, MVT::i64, Expand);
309 setOperationAction(ISD::UDIV, MVT::i32, Expand);
310 setOperationAction(ISD::UREM, MVT::i32, Expand);
311 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
312 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
313 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
314 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
315 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
317 setOperationAction(ISD::SMIN, MVT::i32, Legal);
318 setOperationAction(ISD::UMIN, MVT::i32, Legal);
319 setOperationAction(ISD::SMAX, MVT::i32, Legal);
320 setOperationAction(ISD::UMAX, MVT::i32, Legal);
322 if (!Subtarget->hasFFBH())
323 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
325 if (!Subtarget->hasFFBL())
326 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
328 static const MVT::SimpleValueType VectorIntTypes[] = {
329 MVT::v2i32, MVT::v4i32
332 for (MVT VT : VectorIntTypes) {
333 // Expand the following operations for the current type by default.
334 setOperationAction(ISD::ADD, VT, Expand);
335 setOperationAction(ISD::AND, VT, Expand);
336 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
337 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
338 setOperationAction(ISD::MUL, VT, Expand);
339 setOperationAction(ISD::OR, VT, Expand);
340 setOperationAction(ISD::SHL, VT, Expand);
341 setOperationAction(ISD::SRA, VT, Expand);
342 setOperationAction(ISD::SRL, VT, Expand);
343 setOperationAction(ISD::ROTL, VT, Expand);
344 setOperationAction(ISD::ROTR, VT, Expand);
345 setOperationAction(ISD::SUB, VT, Expand);
346 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
347 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
348 setOperationAction(ISD::SDIV, VT, Expand);
349 setOperationAction(ISD::UDIV, VT, Expand);
350 setOperationAction(ISD::SREM, VT, Expand);
351 setOperationAction(ISD::UREM, VT, Expand);
352 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
353 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
354 setOperationAction(ISD::SDIVREM, VT, Custom);
355 setOperationAction(ISD::UDIVREM, VT, Custom);
356 setOperationAction(ISD::ADDC, VT, Expand);
357 setOperationAction(ISD::SUBC, VT, Expand);
358 setOperationAction(ISD::ADDE, VT, Expand);
359 setOperationAction(ISD::SUBE, VT, Expand);
360 setOperationAction(ISD::SELECT, VT, Expand);
361 setOperationAction(ISD::VSELECT, VT, Expand);
362 setOperationAction(ISD::SELECT_CC, VT, Expand);
363 setOperationAction(ISD::XOR, VT, Expand);
364 setOperationAction(ISD::BSWAP, VT, Expand);
365 setOperationAction(ISD::CTPOP, VT, Expand);
366 setOperationAction(ISD::CTTZ, VT, Expand);
367 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
368 setOperationAction(ISD::CTLZ, VT, Expand);
369 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
370 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
373 static const MVT::SimpleValueType FloatVectorTypes[] = {
374 MVT::v2f32, MVT::v4f32
377 for (MVT VT : FloatVectorTypes) {
378 setOperationAction(ISD::FABS, VT, Expand);
379 setOperationAction(ISD::FMINNUM, VT, Expand);
380 setOperationAction(ISD::FMAXNUM, VT, Expand);
381 setOperationAction(ISD::FADD, VT, Expand);
382 setOperationAction(ISD::FCEIL, VT, Expand);
383 setOperationAction(ISD::FCOS, VT, Expand);
384 setOperationAction(ISD::FDIV, VT, Expand);
385 setOperationAction(ISD::FEXP2, VT, Expand);
386 setOperationAction(ISD::FLOG2, VT, Expand);
387 setOperationAction(ISD::FREM, VT, Expand);
388 setOperationAction(ISD::FPOW, VT, Expand);
389 setOperationAction(ISD::FFLOOR, VT, Expand);
390 setOperationAction(ISD::FTRUNC, VT, Expand);
391 setOperationAction(ISD::FMUL, VT, Expand);
392 setOperationAction(ISD::FMA, VT, Expand);
393 setOperationAction(ISD::FRINT, VT, Expand);
394 setOperationAction(ISD::FNEARBYINT, VT, Expand);
395 setOperationAction(ISD::FSQRT, VT, Expand);
396 setOperationAction(ISD::FSIN, VT, Expand);
397 setOperationAction(ISD::FSUB, VT, Expand);
398 setOperationAction(ISD::FNEG, VT, Expand);
399 setOperationAction(ISD::SELECT, VT, Expand);
400 setOperationAction(ISD::VSELECT, VT, Expand);
401 setOperationAction(ISD::SELECT_CC, VT, Expand);
402 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
403 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
406 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
407 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
409 setTargetDAGCombine(ISD::MUL);
410 setTargetDAGCombine(ISD::SELECT);
411 setTargetDAGCombine(ISD::SELECT_CC);
412 setTargetDAGCombine(ISD::STORE);
414 setTargetDAGCombine(ISD::FADD);
415 setTargetDAGCombine(ISD::FSUB);
417 setBooleanContents(ZeroOrNegativeOneBooleanContent);
418 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
420 setSchedulingPreference(Sched::RegPressure);
421 setJumpIsExpensive(true);
423 // SI at least has hardware support for floating point exceptions, but no way
424 // of using or handling them is implemented. They are also optional in OpenCL
426 setHasFloatingPointExceptions(false);
428 setSelectIsExpensive(false);
429 PredictableSelectIsExpensive = false;
431 // There are no integer divide instructions, and these expand to a pretty
432 // large sequence of instructions.
433 setIntDivIsCheap(false);
434 setPow2SDivIsCheap(false);
435 setFsqrtIsCheap(true);
437 // FIXME: Need to really handle these.
438 MaxStoresPerMemcpy = 4096;
439 MaxStoresPerMemmove = 4096;
440 MaxStoresPerMemset = 4096;
443 //===----------------------------------------------------------------------===//
444 // Target Information
445 //===----------------------------------------------------------------------===//
447 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
451 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
455 // The backend supports 32 and 64 bit floating point immediates.
456 // FIXME: Why are we reporting vectors of FP immediates as legal?
457 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
458 EVT ScalarVT = VT.getScalarType();
459 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
462 // We don't want to shrink f64 / f32 constants.
463 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
464 EVT ScalarVT = VT.getScalarType();
465 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
468 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
472 unsigned NewSize = NewVT.getStoreSizeInBits();
474 // If we are reducing to a 32-bit load, this is always better.
478 EVT OldVT = N->getValueType(0);
479 unsigned OldSize = OldVT.getStoreSizeInBits();
481 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
482 // extloads, so doing one requires using a buffer_load. In cases where we
483 // still couldn't use a scalar load, using the wider load shouldn't really
486 // If the old size already had to be an extload, there's no harm in continuing
487 // to reduce the width.
488 return (OldSize < 32);
491 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
493 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
496 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
497 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
499 return ((LScalarSize <= CastScalarSize) ||
500 (CastScalarSize >= 32) ||
504 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
505 // profitable with the expansion for 64-bit since it's generally good to
507 // FIXME: These should really have the size as a parameter.
508 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
512 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
516 //===---------------------------------------------------------------------===//
518 //===---------------------------------------------------------------------===//
520 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
521 assert(VT.isFloatingPoint());
522 return VT == MVT::f32 || VT == MVT::f64;
525 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
526 assert(VT.isFloatingPoint());
527 return VT == MVT::f32 || VT == MVT::f64;
530 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
536 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
537 // Truncate is just accessing a subregister.
538 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
541 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
542 // Truncate is just accessing a subregister.
543 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
544 (Dest->getPrimitiveSizeInBits() % 32 == 0);
547 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
548 unsigned SrcSize = Src->getScalarSizeInBits();
549 unsigned DestSize = Dest->getScalarSizeInBits();
551 return SrcSize == 32 && DestSize == 64;
554 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
555 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
556 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
557 // this will enable reducing 64-bit operations the 32-bit, which is always
559 return Src == MVT::i32 && Dest == MVT::i64;
562 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
563 return isZExtFree(Val.getValueType(), VT2);
566 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
567 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
568 // limited number of native 64-bit operations. Shrinking an operation to fit
569 // in a single 32-bit register should always be helpful. As currently used,
570 // this is much less general than the name suggests, and is only used in
571 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
572 // not profitable, and may actually be harmful.
573 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
576 //===---------------------------------------------------------------------===//
577 // TargetLowering Callbacks
578 //===---------------------------------------------------------------------===//
580 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
581 const SmallVectorImpl<ISD::InputArg> &Ins) const {
583 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
586 SDValue AMDGPUTargetLowering::LowerReturn(
588 CallingConv::ID CallConv,
590 const SmallVectorImpl<ISD::OutputArg> &Outs,
591 const SmallVectorImpl<SDValue> &OutVals,
592 SDLoc DL, SelectionDAG &DAG) const {
593 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
596 //===---------------------------------------------------------------------===//
597 // Target specific lowering
598 //===---------------------------------------------------------------------===//
600 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
601 SmallVectorImpl<SDValue> &InVals) const {
602 SDValue Callee = CLI.Callee;
603 SelectionDAG &DAG = CLI.DAG;
605 const Function &Fn = *DAG.getMachineFunction().getFunction();
607 StringRef FuncName("<unknown>");
609 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
610 FuncName = G->getSymbol();
611 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
612 FuncName = G->getGlobal()->getName();
614 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
615 DAG.getContext()->diagnose(NoCalls);
619 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
620 SelectionDAG &DAG) const {
621 switch (Op.getOpcode()) {
623 Op.getNode()->dump();
624 llvm_unreachable("Custom lowering code for this"
625 "instruction is not implemented yet!");
627 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
628 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
629 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
630 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
631 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
632 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
633 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
634 case ISD::FREM: return LowerFREM(Op, DAG);
635 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
636 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
637 case ISD::FRINT: return LowerFRINT(Op, DAG);
638 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
639 case ISD::FROUND: return LowerFROUND(Op, DAG);
640 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
641 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
642 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
643 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
644 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
649 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
650 SmallVectorImpl<SDValue> &Results,
651 SelectionDAG &DAG) const {
652 switch (N->getOpcode()) {
653 case ISD::SIGN_EXTEND_INREG:
654 // Different parts of legalization seem to interpret which type of
655 // sign_extend_inreg is the one to check for custom lowering. The extended
656 // from type is what really matters, but some places check for custom
657 // lowering of the result type. This results in trying to use
658 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
659 // nothing here and let the illegal result integer be handled normally.
662 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
666 Results.push_back(SDValue(Node, 0));
667 Results.push_back(SDValue(Node, 1));
668 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
670 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
674 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
675 if (Lowered.getNode())
676 Results.push_back(Lowered);
684 // FIXME: This implements accesses to initialized globals in the constant
685 // address space by copying them to private and accessing that. It does not
686 // properly handle illegal types or vectors. The private vector loads are not
687 // scalarized, and the illegal scalars hit an assertion. This technique will not
688 // work well with large initializers, and this should eventually be
689 // removed. Initialized globals should be placed into a data section that the
690 // runtime will load into a buffer before the kernel is executed. Uses of the
691 // global need to be replaced with a pointer loaded from an implicit kernel
692 // argument into this buffer holding the copy of the data, which will remove the
693 // need for any of this.
694 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
695 const GlobalValue *GV,
696 const SDValue &InitPtr,
698 SelectionDAG &DAG) const {
699 const DataLayout &TD = DAG.getDataLayout();
701 Type *InitTy = Init->getType();
703 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
704 EVT VT = EVT::getEVT(InitTy);
705 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
706 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, DL, VT), InitPtr,
707 MachinePointerInfo(UndefValue::get(PtrTy)), false,
708 false, TD.getPrefTypeAlignment(InitTy));
711 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
712 EVT VT = EVT::getEVT(CFP->getType());
713 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
714 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, DL, VT), InitPtr,
715 MachinePointerInfo(UndefValue::get(PtrTy)), false,
716 false, TD.getPrefTypeAlignment(CFP->getType()));
719 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
720 const StructLayout *SL = TD.getStructLayout(ST);
722 EVT PtrVT = InitPtr.getValueType();
723 SmallVector<SDValue, 8> Chains;
725 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
726 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), DL, PtrVT);
727 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
729 Constant *Elt = Init->getAggregateElement(I);
730 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
733 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
736 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
737 EVT PtrVT = InitPtr.getValueType();
739 unsigned NumElements;
740 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
741 NumElements = AT->getNumElements();
742 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
743 NumElements = VT->getNumElements();
745 llvm_unreachable("Unexpected type");
747 unsigned EltSize = TD.getTypeAllocSize(SeqTy->getElementType());
748 SmallVector<SDValue, 8> Chains;
749 for (unsigned i = 0; i < NumElements; ++i) {
750 SDValue Offset = DAG.getConstant(i * EltSize, DL, PtrVT);
751 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
753 Constant *Elt = Init->getAggregateElement(i);
754 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
757 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
760 if (isa<UndefValue>(Init)) {
761 EVT VT = EVT::getEVT(InitTy);
762 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
763 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
764 MachinePointerInfo(UndefValue::get(PtrTy)), false,
765 false, TD.getPrefTypeAlignment(InitTy));
769 llvm_unreachable("Unhandled constant initializer");
772 static bool hasDefinedInitializer(const GlobalValue *GV) {
773 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
774 if (!GVar || !GVar->hasInitializer())
777 if (isa<UndefValue>(GVar->getInitializer()))
783 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
785 SelectionDAG &DAG) const {
787 const DataLayout &DL = DAG.getDataLayout();
788 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
789 const GlobalValue *GV = G->getGlobal();
791 switch (G->getAddressSpace()) {
792 case AMDGPUAS::LOCAL_ADDRESS: {
793 // XXX: What does the value of G->getOffset() mean?
794 assert(G->getOffset() == 0 &&
795 "Do not know what to do with an non-zero offset");
797 // TODO: We could emit code to handle the initialization somewhere.
798 if (hasDefinedInitializer(GV))
802 if (MFI->LocalMemoryObjects.count(GV) == 0) {
803 uint64_t Size = DL.getTypeAllocSize(GV->getType()->getElementType());
804 Offset = MFI->LDSSize;
805 MFI->LocalMemoryObjects[GV] = Offset;
806 // XXX: Account for alignment?
807 MFI->LDSSize += Size;
809 Offset = MFI->LocalMemoryObjects[GV];
812 return DAG.getConstant(Offset, SDLoc(Op),
813 getPointerTy(DL, AMDGPUAS::LOCAL_ADDRESS));
815 case AMDGPUAS::CONSTANT_ADDRESS: {
816 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
817 Type *EltType = GV->getType()->getElementType();
818 unsigned Size = DL.getTypeAllocSize(EltType);
819 unsigned Alignment = DL.getPrefTypeAlignment(EltType);
821 MVT PrivPtrVT = getPointerTy(DL, AMDGPUAS::PRIVATE_ADDRESS);
822 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
824 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
825 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
827 const GlobalVariable *Var = cast<GlobalVariable>(GV);
828 if (!Var->hasInitializer()) {
829 // This has no use, but bugpoint will hit it.
830 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
833 const Constant *Init = Var->getInitializer();
834 SmallVector<SDNode*, 8> WorkList;
836 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
837 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
838 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
840 WorkList.push_back(*I);
842 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
843 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
844 E = WorkList.end(); I != E; ++I) {
845 SmallVector<SDValue, 8> Ops;
846 Ops.push_back(Chain);
847 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
848 Ops.push_back((*I)->getOperand(i));
850 DAG.UpdateNodeOperands(*I, Ops);
852 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
856 const Function &Fn = *DAG.getMachineFunction().getFunction();
857 DiagnosticInfoUnsupported BadInit(Fn,
858 "initializer for address space");
859 DAG.getContext()->diagnose(BadInit);
863 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
864 SelectionDAG &DAG) const {
865 SmallVector<SDValue, 8> Args;
867 for (const SDUse &U : Op->ops())
868 DAG.ExtractVectorElements(U.get(), Args);
870 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
873 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
874 SelectionDAG &DAG) const {
876 SmallVector<SDValue, 8> Args;
877 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
878 EVT VT = Op.getValueType();
879 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
880 VT.getVectorNumElements());
882 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
885 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
886 SelectionDAG &DAG) const {
888 MachineFunction &MF = DAG.getMachineFunction();
889 const AMDGPUFrameLowering *TFL = Subtarget->getFrameLowering();
891 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
893 unsigned FrameIndex = FIN->getIndex();
894 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
895 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), SDLoc(Op),
899 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
900 SelectionDAG &DAG) const {
901 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
903 EVT VT = Op.getValueType();
905 switch (IntrinsicID) {
907 case AMDGPUIntrinsic::AMDGPU_abs:
908 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
909 return LowerIntrinsicIABS(Op, DAG);
910 case AMDGPUIntrinsic::AMDGPU_lrp:
911 return LowerIntrinsicLRP(Op, DAG);
913 case AMDGPUIntrinsic::AMDGPU_clamp:
914 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
915 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
916 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
918 case Intrinsic::AMDGPU_div_scale: {
919 // 3rd parameter required to be a constant.
920 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
922 return DAG.getUNDEF(VT);
924 // Translate to the operands expected by the machine instruction. The
925 // first parameter must be the same as the first instruction.
926 SDValue Numerator = Op.getOperand(1);
927 SDValue Denominator = Op.getOperand(2);
929 // Note this order is opposite of the machine instruction's operations,
930 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
931 // intrinsic has the numerator as the first operand to match a normal
932 // division operation.
934 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
936 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
937 Denominator, Numerator);
940 case Intrinsic::AMDGPU_div_fmas:
941 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
942 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
945 case Intrinsic::AMDGPU_div_fixup:
946 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
947 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
949 case Intrinsic::AMDGPU_trig_preop:
950 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
951 Op.getOperand(1), Op.getOperand(2));
953 case Intrinsic::AMDGPU_rcp:
954 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
956 case Intrinsic::AMDGPU_rsq:
957 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
959 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
960 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
962 case Intrinsic::AMDGPU_rsq_clamped:
963 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
964 Type *Type = VT.getTypeForEVT(*DAG.getContext());
965 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
966 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
968 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
969 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
970 DAG.getConstantFP(Max, DL, VT));
971 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
972 DAG.getConstantFP(Min, DL, VT));
974 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
977 case Intrinsic::AMDGPU_ldexp:
978 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
981 case AMDGPUIntrinsic::AMDGPU_imax:
982 return DAG.getNode(ISD::SMAX, DL, VT, Op.getOperand(1),
984 case AMDGPUIntrinsic::AMDGPU_umax:
985 return DAG.getNode(ISD::UMAX, DL, VT, Op.getOperand(1),
987 case AMDGPUIntrinsic::AMDGPU_imin:
988 return DAG.getNode(ISD::SMIN, DL, VT, Op.getOperand(1),
990 case AMDGPUIntrinsic::AMDGPU_umin:
991 return DAG.getNode(ISD::UMIN, DL, VT, Op.getOperand(1),
994 case AMDGPUIntrinsic::AMDGPU_umul24:
995 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
996 Op.getOperand(1), Op.getOperand(2));
998 case AMDGPUIntrinsic::AMDGPU_imul24:
999 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
1000 Op.getOperand(1), Op.getOperand(2));
1002 case AMDGPUIntrinsic::AMDGPU_umad24:
1003 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
1004 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
1006 case AMDGPUIntrinsic::AMDGPU_imad24:
1007 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
1008 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
1010 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
1011 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
1013 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
1014 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
1016 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
1017 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
1019 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
1020 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
1022 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
1023 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
1028 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
1029 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
1034 case AMDGPUIntrinsic::AMDGPU_bfi:
1035 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
1040 case AMDGPUIntrinsic::AMDGPU_bfm:
1041 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
1045 case AMDGPUIntrinsic::AMDGPU_brev:
1046 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
1048 case Intrinsic::AMDGPU_class:
1049 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
1050 Op.getOperand(1), Op.getOperand(2));
1052 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
1053 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
1055 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
1056 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
1057 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
1058 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
1062 ///IABS(a) = SMAX(sub(0, a), a)
1063 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
1064 SelectionDAG &DAG) const {
1066 EVT VT = Op.getValueType();
1067 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1070 return DAG.getNode(ISD::SMAX, DL, VT, Neg, Op.getOperand(1));
1073 /// Linear Interpolation
1074 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
1075 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
1076 SelectionDAG &DAG) const {
1078 EVT VT = Op.getValueType();
1079 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
1080 DAG.getConstantFP(1.0f, DL, MVT::f32),
1082 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
1084 return DAG.getNode(ISD::FADD, DL, VT,
1085 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
1089 /// \brief Generate Min/Max node
1090 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,
1097 DAGCombinerInfo &DCI) const {
1098 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1101 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1104 SelectionDAG &DAG = DCI.DAG;
1105 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1114 case ISD::SETFALSE2:
1123 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1124 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1130 // Ordered. Assume ordered for undefined.
1132 // Only do this after legalization to avoid interfering with other combines
1133 // which might occur.
1134 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1135 !DCI.isCalledByLegalizer())
1138 // We need to permute the operands to get the correct NaN behavior. The
1139 // selected operand is the second one based on the failing compare with NaN,
1140 // so permute it based on the compare type the hardware uses.
1142 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1143 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1148 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1149 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1155 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1156 !DCI.isCalledByLegalizer())
1160 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1161 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1163 case ISD::SETCC_INVALID:
1164 llvm_unreachable("Invalid setcc condcode!");
1169 // FIXME: Remove this when combines added to DAGCombiner.
1170 SDValue AMDGPUTargetLowering::CombineIMinMax(SDLoc DL,
1177 SelectionDAG &DAG) const {
1178 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1181 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1185 unsigned Opc = (LHS == True) ? ISD::UMIN : ISD::UMAX;
1186 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1190 unsigned Opc = (LHS == True) ? ISD::SMIN : ISD::SMAX;
1191 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1195 unsigned Opc = (LHS == True) ? ISD::SMAX : ISD::SMIN;
1196 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1200 unsigned Opc = (LHS == True) ? ISD::UMAX : ISD::UMIN;
1201 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1208 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1209 SelectionDAG &DAG) const {
1210 LoadSDNode *Load = cast<LoadSDNode>(Op);
1211 EVT MemVT = Load->getMemoryVT();
1212 EVT MemEltVT = MemVT.getVectorElementType();
1214 EVT LoadVT = Op.getValueType();
1215 EVT EltVT = LoadVT.getVectorElementType();
1216 EVT PtrVT = Load->getBasePtr().getValueType();
1218 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1219 SmallVector<SDValue, 8> Loads;
1220 SmallVector<SDValue, 8> Chains;
1223 unsigned MemEltSize = MemEltVT.getStoreSize();
1224 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1226 for (unsigned i = 0; i < NumElts; ++i) {
1227 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1228 DAG.getConstant(i * MemEltSize, SL, PtrVT));
1231 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1232 Load->getChain(), Ptr,
1233 SrcValue.getWithOffset(i * MemEltSize),
1234 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1235 Load->isInvariant(), Load->getAlignment());
1236 Loads.push_back(NewLoad.getValue(0));
1237 Chains.push_back(NewLoad.getValue(1));
1241 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1242 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1245 return DAG.getMergeValues(Ops, SL);
1248 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1249 SelectionDAG &DAG) const {
1250 EVT VT = Op.getValueType();
1252 // If this is a 2 element vector, we really want to scalarize and not create
1253 // weird 1 element vectors.
1254 if (VT.getVectorNumElements() == 2)
1255 return ScalarizeVectorLoad(Op, DAG);
1257 LoadSDNode *Load = cast<LoadSDNode>(Op);
1258 SDValue BasePtr = Load->getBasePtr();
1259 EVT PtrVT = BasePtr.getValueType();
1260 EVT MemVT = Load->getMemoryVT();
1262 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1265 EVT LoMemVT, HiMemVT;
1268 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1269 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1270 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1272 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1273 Load->getChain(), BasePtr,
1275 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1276 Load->isInvariant(), Load->getAlignment());
1278 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1279 DAG.getConstant(LoMemVT.getStoreSize(), SL,
1283 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1284 Load->getChain(), HiPtr,
1285 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1286 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1287 Load->isInvariant(), Load->getAlignment());
1290 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1291 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1292 LoLoad.getValue(1), HiLoad.getValue(1))
1295 return DAG.getMergeValues(Ops, SL);
1298 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1299 SelectionDAG &DAG) const {
1300 StoreSDNode *Store = cast<StoreSDNode>(Op);
1301 EVT MemVT = Store->getMemoryVT();
1302 unsigned MemBits = MemVT.getSizeInBits();
1304 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1305 // truncating store into an i32 store.
1306 // XXX: We could also handle optimize other vector bitwidths.
1307 if (!MemVT.isVector() || MemBits > 32) {
1312 SDValue Value = Store->getValue();
1313 EVT VT = Value.getValueType();
1314 EVT ElemVT = VT.getVectorElementType();
1315 SDValue Ptr = Store->getBasePtr();
1316 EVT MemEltVT = MemVT.getVectorElementType();
1317 unsigned MemEltBits = MemEltVT.getSizeInBits();
1318 unsigned MemNumElements = MemVT.getVectorNumElements();
1319 unsigned PackedSize = MemVT.getStoreSizeInBits();
1320 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, DL, MVT::i32);
1322 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1324 SDValue PackedValue;
1325 for (unsigned i = 0; i < MemNumElements; ++i) {
1326 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1327 DAG.getConstant(i, DL, MVT::i32));
1328 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1329 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1331 SDValue Shift = DAG.getConstant(MemEltBits * i, DL, MVT::i32);
1332 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1337 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1341 if (PackedSize < 32) {
1342 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1343 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1344 Store->getMemOperand()->getPointerInfo(),
1346 Store->isNonTemporal(), Store->isVolatile(),
1347 Store->getAlignment());
1350 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1351 Store->getMemOperand()->getPointerInfo(),
1352 Store->isVolatile(), Store->isNonTemporal(),
1353 Store->getAlignment());
1356 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1357 SelectionDAG &DAG) const {
1358 StoreSDNode *Store = cast<StoreSDNode>(Op);
1359 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1360 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1361 EVT PtrVT = Store->getBasePtr().getValueType();
1362 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1365 SmallVector<SDValue, 8> Chains;
1367 unsigned EltSize = MemEltVT.getStoreSize();
1368 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1370 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1371 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1373 DAG.getConstant(i, SL, MVT::i32));
1375 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), SL, PtrVT);
1376 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1378 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1379 SrcValue.getWithOffset(i * EltSize),
1380 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1381 Store->getAlignment());
1382 Chains.push_back(NewStore);
1385 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1388 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1389 SelectionDAG &DAG) const {
1390 StoreSDNode *Store = cast<StoreSDNode>(Op);
1391 SDValue Val = Store->getValue();
1392 EVT VT = Val.getValueType();
1394 // If this is a 2 element vector, we really want to scalarize and not create
1395 // weird 1 element vectors.
1396 if (VT.getVectorNumElements() == 2)
1397 return ScalarizeVectorStore(Op, DAG);
1399 EVT MemVT = Store->getMemoryVT();
1400 SDValue Chain = Store->getChain();
1401 SDValue BasePtr = Store->getBasePtr();
1405 EVT LoMemVT, HiMemVT;
1408 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1409 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1410 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1412 EVT PtrVT = BasePtr.getValueType();
1413 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1414 DAG.getConstant(LoMemVT.getStoreSize(), SL,
1417 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1419 = DAG.getTruncStore(Chain, SL, Lo,
1423 Store->isNonTemporal(),
1424 Store->isVolatile(),
1425 Store->getAlignment());
1427 = DAG.getTruncStore(Chain, SL, Hi,
1429 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1431 Store->isNonTemporal(),
1432 Store->isVolatile(),
1433 Store->getAlignment());
1435 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1439 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1441 LoadSDNode *Load = cast<LoadSDNode>(Op);
1442 ISD::LoadExtType ExtType = Load->getExtensionType();
1443 EVT VT = Op.getValueType();
1444 EVT MemVT = Load->getMemoryVT();
1446 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1447 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1448 // FIXME: Copied from PPC
1449 // First, load into 32 bits, then truncate to 1 bit.
1451 SDValue Chain = Load->getChain();
1452 SDValue BasePtr = Load->getBasePtr();
1453 MachineMemOperand *MMO = Load->getMemOperand();
1455 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1456 BasePtr, MVT::i8, MMO);
1459 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1463 return DAG.getMergeValues(Ops, DL);
1466 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1467 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1468 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1471 // <SI && AS=PRIVATE && EXTLOAD && size < 32bit,
1472 // register (2-)byte extract.
1474 // Get Register holding the target.
1475 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1476 DAG.getConstant(2, DL, MVT::i32));
1477 // Load the Register.
1478 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1479 Load->getChain(), Ptr,
1480 DAG.getTargetConstant(0, DL, MVT::i32),
1483 // Get offset within the register.
1484 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1486 DAG.getConstant(0x3, DL, MVT::i32));
1488 // Bit offset of target byte (byteIdx * 8).
1489 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1490 DAG.getConstant(3, DL, MVT::i32));
1492 // Shift to the right.
1493 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1495 // Eliminate the upper bits by setting them to ...
1496 EVT MemEltVT = MemVT.getScalarType();
1499 if (ExtType == ISD::SEXTLOAD) {
1500 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1503 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1507 return DAG.getMergeValues(Ops, DL);
1512 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1516 return DAG.getMergeValues(Ops, DL);
1519 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1521 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1522 if (Result.getNode()) {
1526 StoreSDNode *Store = cast<StoreSDNode>(Op);
1527 SDValue Chain = Store->getChain();
1528 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1529 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1530 Store->getValue().getValueType().isVector()) {
1531 return ScalarizeVectorStore(Op, DAG);
1534 EVT MemVT = Store->getMemoryVT();
1535 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1536 MemVT.bitsLT(MVT::i32)) {
1538 if (Store->getMemoryVT() == MVT::i8) {
1540 } else if (Store->getMemoryVT() == MVT::i16) {
1543 SDValue BasePtr = Store->getBasePtr();
1544 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1545 DAG.getConstant(2, DL, MVT::i32));
1546 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1548 DAG.getTargetConstant(0, DL, MVT::i32));
1550 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1551 DAG.getConstant(0x3, DL, MVT::i32));
1553 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1554 DAG.getConstant(3, DL, MVT::i32));
1556 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1559 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1561 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1562 MaskedValue, ShiftAmt);
1564 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32,
1565 DAG.getConstant(Mask, DL, MVT::i32),
1567 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1568 DAG.getConstant(0xffffffff, DL, MVT::i32));
1569 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1571 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1572 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1574 DAG.getTargetConstant(0, DL, MVT::i32));
1579 // This is a shortcut for integer division because we have fast i32<->f32
1580 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1581 // float is enough to accurately represent up to a 24-bit integer.
1582 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1584 EVT VT = Op.getValueType();
1585 SDValue LHS = Op.getOperand(0);
1586 SDValue RHS = Op.getOperand(1);
1587 MVT IntVT = MVT::i32;
1588 MVT FltVT = MVT::f32;
1590 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1591 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1593 if (VT.isVector()) {
1594 unsigned NElts = VT.getVectorNumElements();
1595 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1596 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1599 unsigned BitSize = VT.getScalarType().getSizeInBits();
1601 SDValue jq = DAG.getConstant(1, DL, IntVT);
1604 // char|short jq = ia ^ ib;
1605 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1607 // jq = jq >> (bitsize - 2)
1608 jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1609 DAG.getConstant(BitSize - 2, DL, VT));
1612 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1615 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1618 // int ia = (int)LHS;
1620 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1622 // int ib, (int)RHS;
1624 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1626 // float fa = (float)ia;
1627 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1629 // float fb = (float)ib;
1630 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1632 // float fq = native_divide(fa, fb);
1633 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1634 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1637 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1639 // float fqneg = -fq;
1640 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1642 // float fr = mad(fqneg, fb, fa);
1643 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1644 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1646 // int iq = (int)fq;
1647 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1650 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1653 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1655 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1657 // int cv = fr >= fb;
1658 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1660 // jq = (cv ? jq : 0);
1661 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1663 // dst = trunc/extend to legal type
1664 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1667 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1669 // Rem needs compensation, it's easier to recompute it
1670 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1671 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1677 return DAG.getMergeValues(Res, DL);
1680 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1682 SmallVectorImpl<SDValue> &Results) const {
1683 assert(Op.getValueType() == MVT::i64);
1686 EVT VT = Op.getValueType();
1687 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1689 SDValue one = DAG.getConstant(1, DL, HalfVT);
1690 SDValue zero = DAG.getConstant(0, DL, HalfVT);
1693 SDValue LHS = Op.getOperand(0);
1694 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
1695 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
1697 SDValue RHS = Op.getOperand(1);
1698 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
1699 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
1701 if (VT == MVT::i64 &&
1702 DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1703 DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1705 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1708 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(0), zero);
1709 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(1), zero);
1710 Results.push_back(DIV);
1711 Results.push_back(REM);
1715 // Get Speculative values
1716 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1717 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1719 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
1720 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, zero);
1722 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
1723 SDValue DIV_Lo = zero;
1725 const unsigned halfBitWidth = HalfVT.getSizeInBits();
1727 for (unsigned i = 0; i < halfBitWidth; ++i) {
1728 const unsigned bitPos = halfBitWidth - i - 1;
1729 SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
1730 // Get value of high bit
1731 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1732 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
1733 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1736 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
1738 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1740 SDValue BIT = DAG.getConstant(1 << bitPos, DL, HalfVT);
1741 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
1743 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1746 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1747 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1750 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
1751 Results.push_back(DIV);
1752 Results.push_back(REM);
1755 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1756 SelectionDAG &DAG) const {
1758 EVT VT = Op.getValueType();
1760 if (VT == MVT::i64) {
1761 SmallVector<SDValue, 2> Results;
1762 LowerUDIVREM64(Op, DAG, Results);
1763 return DAG.getMergeValues(Results, DL);
1766 SDValue Num = Op.getOperand(0);
1767 SDValue Den = Op.getOperand(1);
1769 if (VT == MVT::i32) {
1770 if (DAG.MaskedValueIsZero(Num, APInt::getHighBitsSet(32, 8)) &&
1771 DAG.MaskedValueIsZero(Den, APInt::getHighBitsSet(32, 8))) {
1772 // TODO: We technically could do this for i64, but shouldn't that just be
1773 // handled by something generally reducing 64-bit division on 32-bit
1774 // values to 32-bit?
1775 return LowerDIVREM24(Op, DAG, false);
1779 // RCP = URECIP(Den) = 2^32 / Den + e
1780 // e is rounding error.
1781 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1783 // RCP_LO = mul(RCP, Den) */
1784 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1786 // RCP_HI = mulhu (RCP, Den) */
1787 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1789 // NEG_RCP_LO = -RCP_LO
1790 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1793 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1794 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1797 // Calculate the rounding error from the URECIP instruction
1798 // E = mulhu(ABS_RCP_LO, RCP)
1799 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1801 // RCP_A_E = RCP + E
1802 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1804 // RCP_S_E = RCP - E
1805 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1807 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1808 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1811 // Quotient = mulhu(Tmp0, Num)
1812 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1814 // Num_S_Remainder = Quotient * Den
1815 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1817 // Remainder = Num - Num_S_Remainder
1818 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1820 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1821 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1822 DAG.getConstant(-1, DL, VT),
1823 DAG.getConstant(0, DL, VT),
1825 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1826 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1828 DAG.getConstant(-1, DL, VT),
1829 DAG.getConstant(0, DL, VT),
1831 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1832 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1835 // Calculate Division result:
1837 // Quotient_A_One = Quotient + 1
1838 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1839 DAG.getConstant(1, DL, VT));
1841 // Quotient_S_One = Quotient - 1
1842 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1843 DAG.getConstant(1, DL, VT));
1845 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1846 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1847 Quotient, Quotient_A_One, ISD::SETEQ);
1849 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1850 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1851 Quotient_S_One, Div, ISD::SETEQ);
1853 // Calculate Rem result:
1855 // Remainder_S_Den = Remainder - Den
1856 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1858 // Remainder_A_Den = Remainder + Den
1859 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1861 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1862 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1863 Remainder, Remainder_S_Den, ISD::SETEQ);
1865 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1866 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1867 Remainder_A_Den, Rem, ISD::SETEQ);
1872 return DAG.getMergeValues(Ops, DL);
1875 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1876 SelectionDAG &DAG) const {
1878 EVT VT = Op.getValueType();
1880 SDValue LHS = Op.getOperand(0);
1881 SDValue RHS = Op.getOperand(1);
1883 SDValue Zero = DAG.getConstant(0, DL, VT);
1884 SDValue NegOne = DAG.getConstant(-1, DL, VT);
1886 if (VT == MVT::i32 &&
1887 DAG.ComputeNumSignBits(LHS) > 8 &&
1888 DAG.ComputeNumSignBits(RHS) > 8) {
1889 return LowerDIVREM24(Op, DAG, true);
1891 if (VT == MVT::i64 &&
1892 DAG.ComputeNumSignBits(LHS) > 32 &&
1893 DAG.ComputeNumSignBits(RHS) > 32) {
1894 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1897 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1898 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1899 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1902 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1903 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1905 return DAG.getMergeValues(Res, DL);
1908 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1909 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1910 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1911 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1913 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1914 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1916 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1917 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1919 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1920 SDValue Rem = Div.getValue(1);
1922 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1923 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1925 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1926 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1932 return DAG.getMergeValues(Res, DL);
1935 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1936 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1938 EVT VT = Op.getValueType();
1939 SDValue X = Op.getOperand(0);
1940 SDValue Y = Op.getOperand(1);
1942 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1943 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1944 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1946 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1949 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1951 SDValue Src = Op.getOperand(0);
1953 // result = trunc(src)
1954 // if (src > 0.0 && src != result)
1957 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1959 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
1960 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1963 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
1965 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1966 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1967 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1969 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1970 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1973 static SDValue extractF64Exponent(SDValue Hi, SDLoc SL, SelectionDAG &DAG) {
1974 const unsigned FractBits = 52;
1975 const unsigned ExpBits = 11;
1977 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1979 DAG.getConstant(FractBits - 32, SL, MVT::i32),
1980 DAG.getConstant(ExpBits, SL, MVT::i32));
1981 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1982 DAG.getConstant(1023, SL, MVT::i32));
1987 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1989 SDValue Src = Op.getOperand(0);
1991 assert(Op.getValueType() == MVT::f64);
1993 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1994 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1996 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1998 // Extract the upper half, since this is where we will find the sign and
2000 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
2002 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2004 const unsigned FractBits = 52;
2006 // Extract the sign bit.
2007 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32);
2008 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
2010 // Extend back to to 64-bits.
2011 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
2013 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
2015 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
2016 const SDValue FractMask
2017 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64);
2019 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
2020 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
2021 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
2024 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2026 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
2028 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2029 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2031 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
2032 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
2034 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
2037 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
2039 SDValue Src = Op.getOperand(0);
2041 assert(Op.getValueType() == MVT::f64);
2043 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
2044 SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
2045 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2047 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2048 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2050 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2052 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
2053 SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
2056 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2057 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2059 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2062 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2063 // FNEARBYINT and FRINT are the same, except in their handling of FP
2064 // exceptions. Those aren't really meaningful for us, and OpenCL only has
2065 // rint, so just treat them as equivalent.
2066 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2069 // XXX - May require not supporting f32 denormals?
2070 SDValue AMDGPUTargetLowering::LowerFROUND32(SDValue Op, SelectionDAG &DAG) const {
2072 SDValue X = Op.getOperand(0);
2074 SDValue T = DAG.getNode(ISD::FTRUNC, SL, MVT::f32, X);
2076 SDValue Diff = DAG.getNode(ISD::FSUB, SL, MVT::f32, X, T);
2078 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff);
2080 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f32);
2081 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
2082 const SDValue Half = DAG.getConstantFP(0.5, SL, MVT::f32);
2084 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f32, One, X);
2087 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
2089 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2091 SDValue Sel = DAG.getNode(ISD::SELECT, SL, MVT::f32, Cmp, SignOne, Zero);
2093 return DAG.getNode(ISD::FADD, SL, MVT::f32, T, Sel);
2096 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
2098 SDValue X = Op.getOperand(0);
2100 SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
2102 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2103 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2104 const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
2105 const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
2107 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2109 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2111 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
2113 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2115 const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL,
2118 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2119 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2120 DAG.getConstant(INT64_C(0x0008000000000000), SL,
2124 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2125 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
2126 DAG.getConstant(0, SL, MVT::i64), Tmp0,
2129 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2130 D, DAG.getConstant(0, SL, MVT::i64));
2131 SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
2133 K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2134 K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
2136 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2137 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2138 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
2140 SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
2142 DAG.getConstantFP(1.0, SL, MVT::f64),
2143 DAG.getConstantFP(0.0, SL, MVT::f64));
2145 SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
2147 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
2148 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
2153 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2154 EVT VT = Op.getValueType();
2157 return LowerFROUND32(Op, DAG);
2160 return LowerFROUND64(Op, DAG);
2162 llvm_unreachable("unhandled type");
2165 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2167 SDValue Src = Op.getOperand(0);
2169 // result = trunc(src);
2170 // if (src < 0.0 && src != result)
2173 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2175 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2176 const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
2179 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2181 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2182 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2183 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2185 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2186 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2189 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2190 bool Signed) const {
2192 SDValue Src = Op.getOperand(0);
2194 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2196 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2197 DAG.getConstant(0, SL, MVT::i32));
2198 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2199 DAG.getConstant(1, SL, MVT::i32));
2201 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2204 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2206 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2207 DAG.getConstant(32, SL, MVT::i32));
2209 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2212 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2213 SelectionDAG &DAG) const {
2214 SDValue S0 = Op.getOperand(0);
2215 if (S0.getValueType() != MVT::i64)
2218 EVT DestVT = Op.getValueType();
2219 if (DestVT == MVT::f64)
2220 return LowerINT_TO_FP64(Op, DAG, false);
2222 assert(DestVT == MVT::f32);
2226 // f32 uint_to_fp i64
2227 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2228 DAG.getConstant(0, DL, MVT::i32));
2229 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
2230 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2231 DAG.getConstant(1, DL, MVT::i32));
2232 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
2233 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
2234 DAG.getConstantFP(4294967296.0f, DL, MVT::f32)); // 2^32
2235 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
2238 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2239 SelectionDAG &DAG) const {
2240 SDValue Src = Op.getOperand(0);
2241 if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64)
2242 return LowerINT_TO_FP64(Op, DAG, true);
2247 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2248 bool Signed) const {
2251 SDValue Src = Op.getOperand(0);
2253 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2255 SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL,
2257 SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL,
2260 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2262 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2265 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2267 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2268 MVT::i32, FloorMul);
2269 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2271 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
2273 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2276 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2277 SelectionDAG &DAG) const {
2278 SDValue Src = Op.getOperand(0);
2280 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2281 return LowerFP64_TO_INT(Op, DAG, true);
2286 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2287 SelectionDAG &DAG) const {
2288 SDValue Src = Op.getOperand(0);
2290 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2291 return LowerFP64_TO_INT(Op, DAG, false);
2296 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2297 SelectionDAG &DAG) const {
2298 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2299 MVT VT = Op.getSimpleValueType();
2300 MVT ScalarVT = VT.getScalarType();
2305 SDValue Src = Op.getOperand(0);
2308 // TODO: Don't scalarize on Evergreen?
2309 unsigned NElts = VT.getVectorNumElements();
2310 SmallVector<SDValue, 8> Args;
2311 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2313 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2314 for (unsigned I = 0; I < NElts; ++I)
2315 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2317 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
2320 //===----------------------------------------------------------------------===//
2321 // Custom DAG optimizations
2322 //===----------------------------------------------------------------------===//
2324 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2325 APInt KnownZero, KnownOne;
2326 EVT VT = Op.getValueType();
2327 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2329 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2332 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2333 EVT VT = Op.getValueType();
2335 // In order for this to be a signed 24-bit value, bit 23, must
2337 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2338 // as unsigned 24-bit values.
2339 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2342 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2344 SelectionDAG &DAG = DCI.DAG;
2345 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2346 EVT VT = Op.getValueType();
2348 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2349 APInt KnownZero, KnownOne;
2350 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2351 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2352 DCI.CommitTargetLoweringOpt(TLO);
2355 template <typename IntTy>
2356 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
2357 uint32_t Offset, uint32_t Width, SDLoc DL) {
2358 if (Width + Offset < 32) {
2359 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2360 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2361 return DAG.getConstant(Result, DL, MVT::i32);
2364 return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2367 static bool usesAllNormalStores(SDNode *LoadVal) {
2368 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2369 if (!ISD::isNormalStore(*I))
2376 // If we have a copy of an illegal type, replace it with a load / store of an
2377 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2378 // instructions emitted when handling extloads and truncstores. Ideally we could
2379 // recognize the pack / unpack pattern to eliminate it.
2380 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2381 DAGCombinerInfo &DCI) const {
2382 if (!DCI.isBeforeLegalize())
2385 StoreSDNode *SN = cast<StoreSDNode>(N);
2386 SDValue Value = SN->getValue();
2387 EVT VT = Value.getValueType();
2389 if (isTypeLegal(VT) || SN->isVolatile() ||
2390 !ISD::isNormalLoad(Value.getNode()) || VT.getSizeInBits() < 8)
2393 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2394 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2397 EVT MemVT = LoadVal->getMemoryVT();
2400 SelectionDAG &DAG = DCI.DAG;
2401 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2403 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2405 LoadVal->getChain(),
2406 LoadVal->getBasePtr(),
2407 LoadVal->getOffset(),
2409 LoadVal->getMemOperand());
2411 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2412 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2414 return DAG.getStore(SN->getChain(), SL, NewLoad,
2415 SN->getBasePtr(), SN->getMemOperand());
2418 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2419 DAGCombinerInfo &DCI) const {
2420 EVT VT = N->getValueType(0);
2422 if (VT.isVector() || VT.getSizeInBits() > 32)
2425 SelectionDAG &DAG = DCI.DAG;
2428 SDValue N0 = N->getOperand(0);
2429 SDValue N1 = N->getOperand(1);
2432 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2433 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2434 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2435 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2436 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2437 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2438 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2439 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2444 // We need to use sext even for MUL_U24, because MUL_U24 is used
2445 // for signed multiply of 8 and 16-bit types.
2446 return DAG.getSExtOrTrunc(Mul, DL, VT);
2449 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2450 DAGCombinerInfo &DCI) const {
2451 SelectionDAG &DAG = DCI.DAG;
2454 switch(N->getOpcode()) {
2458 return performMulCombine(N, DCI);
2459 case AMDGPUISD::MUL_I24:
2460 case AMDGPUISD::MUL_U24: {
2461 SDValue N0 = N->getOperand(0);
2462 SDValue N1 = N->getOperand(1);
2463 simplifyI24(N0, DCI);
2464 simplifyI24(N1, DCI);
2468 SDValue Cond = N->getOperand(0);
2469 if (Cond.getOpcode() == ISD::SETCC && Cond.hasOneUse()) {
2470 EVT VT = N->getValueType(0);
2471 SDValue LHS = Cond.getOperand(0);
2472 SDValue RHS = Cond.getOperand(1);
2473 SDValue CC = Cond.getOperand(2);
2475 SDValue True = N->getOperand(1);
2476 SDValue False = N->getOperand(2);
2479 return CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
2481 // TODO: Implement min / max Evergreen instructions.
2482 if (VT == MVT::i32 &&
2483 Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
2484 return CombineIMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
2490 case AMDGPUISD::BFE_I32:
2491 case AMDGPUISD::BFE_U32: {
2492 assert(!N->getValueType(0).isVector() &&
2493 "Vector handling of BFE not implemented");
2494 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2498 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2500 return DAG.getConstant(0, DL, MVT::i32);
2502 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2506 SDValue BitsFrom = N->getOperand(0);
2507 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2509 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2511 if (OffsetVal == 0) {
2512 // This is already sign / zero extended, so try to fold away extra BFEs.
2513 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2515 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2516 if (OpSignBits >= SignBits)
2519 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2521 // This is a sign_extend_inreg. Replace it to take advantage of existing
2522 // DAG Combines. If not eliminated, we will match back to BFE during
2525 // TODO: The sext_inreg of extended types ends, although we can could
2526 // handle them in a single BFE.
2527 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2528 DAG.getValueType(SmallVT));
2531 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2534 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2536 return constantFoldBFE<int32_t>(DAG,
2537 CVal->getSExtValue(),
2543 return constantFoldBFE<uint32_t>(DAG,
2544 CVal->getZExtValue(),
2550 if ((OffsetVal + WidthVal) >= 32) {
2551 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
2552 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2553 BitsFrom, ShiftVal);
2556 if (BitsFrom.hasOneUse()) {
2557 APInt Demanded = APInt::getBitsSet(32,
2559 OffsetVal + WidthVal);
2561 APInt KnownZero, KnownOne;
2562 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2563 !DCI.isBeforeLegalizeOps());
2564 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2565 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2566 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2567 KnownZero, KnownOne, TLO)) {
2568 DCI.CommitTargetLoweringOpt(TLO);
2576 return performStoreCombine(N, DCI);
2581 //===----------------------------------------------------------------------===//
2583 //===----------------------------------------------------------------------===//
2585 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2588 const SmallVectorImpl<ISD::InputArg> &Ins,
2589 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2591 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2592 if (Ins[i].ArgVT == Ins[i].VT) {
2593 OrigIns.push_back(Ins[i]);
2598 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2599 // Vector has been split into scalars.
2600 VT = Ins[i].ArgVT.getVectorElementType();
2601 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2602 Ins[i].ArgVT.getVectorElementType() !=
2603 Ins[i].VT.getVectorElementType()) {
2604 // Vector elements have been promoted
2607 // Vector has been spilt into smaller vectors.
2611 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2612 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2613 OrigIns.push_back(Arg);
2617 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2618 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2619 return CFP->isExactlyValue(1.0);
2621 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2622 return C->isAllOnesValue();
2627 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2628 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2629 return CFP->getValueAPF().isZero();
2631 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2632 return C->isNullValue();
2637 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2638 const TargetRegisterClass *RC,
2639 unsigned Reg, EVT VT) const {
2640 MachineFunction &MF = DAG.getMachineFunction();
2641 MachineRegisterInfo &MRI = MF.getRegInfo();
2642 unsigned VirtualRegister;
2643 if (!MRI.isLiveIn(Reg)) {
2644 VirtualRegister = MRI.createVirtualRegister(RC);
2645 MRI.addLiveIn(Reg, VirtualRegister);
2647 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2649 return DAG.getRegister(VirtualRegister, VT);
2652 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2654 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2655 switch ((AMDGPUISD::NodeType)Opcode) {
2656 case AMDGPUISD::FIRST_NUMBER: break;
2658 NODE_NAME_CASE(CALL);
2659 NODE_NAME_CASE(UMUL);
2660 NODE_NAME_CASE(RET_FLAG);
2661 NODE_NAME_CASE(BRANCH_COND);
2664 NODE_NAME_CASE(DWORDADDR)
2665 NODE_NAME_CASE(FRACT)
2666 NODE_NAME_CASE(CLAMP)
2667 NODE_NAME_CASE(COS_HW)
2668 NODE_NAME_CASE(SIN_HW)
2669 NODE_NAME_CASE(FMAX_LEGACY)
2670 NODE_NAME_CASE(FMIN_LEGACY)
2671 NODE_NAME_CASE(FMAX3)
2672 NODE_NAME_CASE(SMAX3)
2673 NODE_NAME_CASE(UMAX3)
2674 NODE_NAME_CASE(FMIN3)
2675 NODE_NAME_CASE(SMIN3)
2676 NODE_NAME_CASE(UMIN3)
2677 NODE_NAME_CASE(URECIP)
2678 NODE_NAME_CASE(DIV_SCALE)
2679 NODE_NAME_CASE(DIV_FMAS)
2680 NODE_NAME_CASE(DIV_FIXUP)
2681 NODE_NAME_CASE(TRIG_PREOP)
2684 NODE_NAME_CASE(RSQ_LEGACY)
2685 NODE_NAME_CASE(RSQ_CLAMPED)
2686 NODE_NAME_CASE(LDEXP)
2687 NODE_NAME_CASE(FP_CLASS)
2688 NODE_NAME_CASE(DOT4)
2689 NODE_NAME_CASE(CARRY)
2690 NODE_NAME_CASE(BORROW)
2691 NODE_NAME_CASE(BFE_U32)
2692 NODE_NAME_CASE(BFE_I32)
2695 NODE_NAME_CASE(BREV)
2696 NODE_NAME_CASE(MUL_U24)
2697 NODE_NAME_CASE(MUL_I24)
2698 NODE_NAME_CASE(MAD_U24)
2699 NODE_NAME_CASE(MAD_I24)
2700 NODE_NAME_CASE(TEXTURE_FETCH)
2701 NODE_NAME_CASE(EXPORT)
2702 NODE_NAME_CASE(CONST_ADDRESS)
2703 NODE_NAME_CASE(REGISTER_LOAD)
2704 NODE_NAME_CASE(REGISTER_STORE)
2705 NODE_NAME_CASE(LOAD_CONSTANT)
2706 NODE_NAME_CASE(LOAD_INPUT)
2707 NODE_NAME_CASE(SAMPLE)
2708 NODE_NAME_CASE(SAMPLEB)
2709 NODE_NAME_CASE(SAMPLED)
2710 NODE_NAME_CASE(SAMPLEL)
2711 NODE_NAME_CASE(CVT_F32_UBYTE0)
2712 NODE_NAME_CASE(CVT_F32_UBYTE1)
2713 NODE_NAME_CASE(CVT_F32_UBYTE2)
2714 NODE_NAME_CASE(CVT_F32_UBYTE3)
2715 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2716 NODE_NAME_CASE(CONST_DATA_PTR)
2717 case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
2718 NODE_NAME_CASE(SENDMSG)
2719 NODE_NAME_CASE(INTERP_MOV)
2720 NODE_NAME_CASE(INTERP_P1)
2721 NODE_NAME_CASE(INTERP_P2)
2722 NODE_NAME_CASE(STORE_MSKOR)
2723 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2724 case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break;
2729 SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
2730 DAGCombinerInfo &DCI,
2731 unsigned &RefinementSteps,
2732 bool &UseOneConstNR) const {
2733 SelectionDAG &DAG = DCI.DAG;
2734 EVT VT = Operand.getValueType();
2736 if (VT == MVT::f32) {
2737 RefinementSteps = 0;
2738 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
2741 // TODO: There is also f64 rsq instruction, but the documentation is less
2742 // clear on its precision.
2747 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
2748 DAGCombinerInfo &DCI,
2749 unsigned &RefinementSteps) const {
2750 SelectionDAG &DAG = DCI.DAG;
2751 EVT VT = Operand.getValueType();
2753 if (VT == MVT::f32) {
2754 // Reciprocal, < 1 ulp error.
2756 // This reciprocal approximation converges to < 0.5 ulp error with one
2757 // newton rhapson performed with two fused multiple adds (FMAs).
2759 RefinementSteps = 0;
2760 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
2763 // TODO: There is also f64 rcp instruction, but the documentation is less
2764 // clear on its precision.
2769 static void computeKnownBitsForMinMax(const SDValue Op0,
2773 const SelectionDAG &DAG,
2775 APInt Op0Zero, Op0One;
2776 APInt Op1Zero, Op1One;
2777 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2778 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2780 KnownZero = Op0Zero & Op1Zero;
2781 KnownOne = Op0One & Op1One;
2784 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2788 const SelectionDAG &DAG,
2789 unsigned Depth) const {
2791 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2795 unsigned Opc = Op.getOpcode();
2800 case ISD::INTRINSIC_WO_CHAIN: {
2801 // FIXME: The intrinsic should just use the node.
2802 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2803 case AMDGPUIntrinsic::AMDGPU_imax:
2804 case AMDGPUIntrinsic::AMDGPU_umax:
2805 case AMDGPUIntrinsic::AMDGPU_imin:
2806 case AMDGPUIntrinsic::AMDGPU_umin:
2807 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2808 KnownZero, KnownOne, DAG, Depth);
2816 case AMDGPUISD::CARRY:
2817 case AMDGPUISD::BORROW: {
2818 KnownZero = APInt::getHighBitsSet(32, 31);
2822 case AMDGPUISD::BFE_I32:
2823 case AMDGPUISD::BFE_U32: {
2824 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2828 unsigned BitWidth = 32;
2829 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2831 if (Opc == AMDGPUISD::BFE_U32)
2832 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2839 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2841 const SelectionDAG &DAG,
2842 unsigned Depth) const {
2843 switch (Op.getOpcode()) {
2844 case AMDGPUISD::BFE_I32: {
2845 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2849 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2850 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2851 if (!Offset || !Offset->isNullValue())
2854 // TODO: Could probably figure something out with non-0 offsets.
2855 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2856 return std::max(SignBits, Op0SignBits);
2859 case AMDGPUISD::BFE_U32: {
2860 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2861 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
2864 case AMDGPUISD::CARRY:
2865 case AMDGPUISD::BORROW: