1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
40 const Twine &Description;
45 static int getKindID() {
47 KindID = llvm::getNextAvailablePluginDiagnosticKind();
52 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53 DiagnosticSeverity Severity = DS_Error)
54 : DiagnosticInfo(getKindID(), Severity),
58 const Function &getFunction() const { return Fn; }
59 const Twine &getDescription() const { return Description; }
61 void print(DiagnosticPrinter &DP) const override {
62 DP << "unsupported " << getDescription() << " in " << Fn.getName();
65 static bool classof(const DiagnosticInfo *DI) {
66 return DI->getKind() == getKindID();
70 int DiagnosticInfoUnsupported::KindID = 0;
74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75 CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State) {
77 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78 ArgFlags.getOrigAlign());
79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
84 #include "AMDGPUGenCallingConv.inc"
86 // Find a larger type to do a load / store of a vector with.
87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88 unsigned StoreSize = VT.getStoreSizeInBits();
90 return EVT::getIntegerVT(Ctx, StoreSize);
92 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
96 // Type for a vector that will be loaded to.
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98 unsigned StoreSize = VT.getStoreSizeInBits();
100 return EVT::getIntegerVT(Ctx, 32);
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
106 const AMDGPUSubtarget &STI)
107 : TargetLowering(TM), Subtarget(&STI) {
108 setOperationAction(ISD::Constant, MVT::i32, Legal);
109 setOperationAction(ISD::Constant, MVT::i64, Legal);
110 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
111 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
113 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
114 setOperationAction(ISD::BRIND, MVT::Other, Expand);
116 // We need to custom lower some of the intrinsics
117 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
119 // Library functions. These default to Expand, but we have instructions
121 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
122 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
123 setOperationAction(ISD::FPOW, MVT::f32, Legal);
124 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
125 setOperationAction(ISD::FABS, MVT::f32, Legal);
126 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
127 setOperationAction(ISD::FRINT, MVT::f32, Legal);
128 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
129 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
130 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
132 setOperationAction(ISD::FROUND, MVT::f32, Custom);
133 setOperationAction(ISD::FROUND, MVT::f64, Custom);
135 setOperationAction(ISD::FREM, MVT::f32, Custom);
136 setOperationAction(ISD::FREM, MVT::f64, Custom);
138 // v_mad_f32 does not support denormals according to some sources.
139 if (!Subtarget->hasFP32Denormals())
140 setOperationAction(ISD::FMAD, MVT::f32, Legal);
142 // Expand to fneg + fadd.
143 setOperationAction(ISD::FSUB, MVT::f64, Expand);
145 // Lower floating point store/load to integer store/load to reduce the number
146 // of patterns in tablegen.
147 setOperationAction(ISD::STORE, MVT::f32, Promote);
148 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
150 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
151 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
153 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
154 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
156 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
157 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
159 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
160 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
162 setOperationAction(ISD::STORE, MVT::f64, Promote);
163 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
165 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
166 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
168 // Custom lowering of vector stores is required for local address space
170 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
172 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
173 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
174 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
176 // XXX: This can be change to Custom, once ExpandVectorStores can
177 // handle 64-bit stores.
178 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
180 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
181 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
182 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
183 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
184 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
187 setOperationAction(ISD::LOAD, MVT::f32, Promote);
188 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
190 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
193 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
196 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
197 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
199 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
200 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
202 setOperationAction(ISD::LOAD, MVT::f64, Promote);
203 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
205 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
206 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
209 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
210 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
211 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
213 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
216 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
217 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
219 // There are no 64-bit extloads. These should be done as a 32-bit extload and
220 // an extension to 64-bit.
221 for (MVT VT : MVT::integer_valuetypes()) {
222 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
223 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
224 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
227 for (MVT VT : MVT::integer_vector_valuetypes()) {
228 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
229 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
230 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
231 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
232 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
233 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
234 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
235 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
236 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
237 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
238 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
239 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
242 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
244 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
245 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
246 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
247 setOperationAction(ISD::FRINT, MVT::f64, Custom);
248 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
251 if (!Subtarget->hasBFI()) {
252 // fcopysign can be done in a single instruction with BFI.
253 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
254 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
257 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
259 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
260 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
261 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
262 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand);
264 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
265 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
266 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
267 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand);
269 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
270 setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand);
271 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
272 setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand);
274 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
275 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
277 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
278 for (MVT VT : ScalarIntVTs) {
279 setOperationAction(ISD::SREM, VT, Expand);
280 setOperationAction(ISD::SDIV, VT, Expand);
282 // GPU does not have divrem function for signed or unsigned.
283 setOperationAction(ISD::SDIVREM, VT, Custom);
284 setOperationAction(ISD::UDIVREM, VT, Custom);
286 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
287 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
288 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
290 setOperationAction(ISD::BSWAP, VT, Expand);
291 setOperationAction(ISD::CTTZ, VT, Expand);
292 setOperationAction(ISD::CTLZ, VT, Expand);
295 if (!Subtarget->hasBCNT(32))
296 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
298 if (!Subtarget->hasBCNT(64))
299 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
301 // The hardware supports 32-bit ROTR, but not ROTL.
302 setOperationAction(ISD::ROTL, MVT::i32, Expand);
303 setOperationAction(ISD::ROTL, MVT::i64, Expand);
304 setOperationAction(ISD::ROTR, MVT::i64, Expand);
306 setOperationAction(ISD::MUL, MVT::i64, Expand);
307 setOperationAction(ISD::MULHU, MVT::i64, Expand);
308 setOperationAction(ISD::MULHS, MVT::i64, Expand);
309 setOperationAction(ISD::UDIV, MVT::i32, Expand);
310 setOperationAction(ISD::UREM, MVT::i32, Expand);
311 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
312 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
313 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
314 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
315 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
317 setOperationAction(ISD::SMIN, MVT::i32, Legal);
318 setOperationAction(ISD::UMIN, MVT::i32, Legal);
319 setOperationAction(ISD::SMAX, MVT::i32, Legal);
320 setOperationAction(ISD::UMAX, MVT::i32, Legal);
322 if (!Subtarget->hasFFBH())
323 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
325 if (!Subtarget->hasFFBL())
326 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
328 static const MVT::SimpleValueType VectorIntTypes[] = {
329 MVT::v2i32, MVT::v4i32
332 for (MVT VT : VectorIntTypes) {
333 // Expand the following operations for the current type by default.
334 setOperationAction(ISD::ADD, VT, Expand);
335 setOperationAction(ISD::AND, VT, Expand);
336 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
337 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
338 setOperationAction(ISD::MUL, VT, Expand);
339 setOperationAction(ISD::OR, VT, Expand);
340 setOperationAction(ISD::SHL, VT, Expand);
341 setOperationAction(ISD::SRA, VT, Expand);
342 setOperationAction(ISD::SRL, VT, Expand);
343 setOperationAction(ISD::ROTL, VT, Expand);
344 setOperationAction(ISD::ROTR, VT, Expand);
345 setOperationAction(ISD::SUB, VT, Expand);
346 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
347 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
348 setOperationAction(ISD::SDIV, VT, Expand);
349 setOperationAction(ISD::UDIV, VT, Expand);
350 setOperationAction(ISD::SREM, VT, Expand);
351 setOperationAction(ISD::UREM, VT, Expand);
352 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
353 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
354 setOperationAction(ISD::SDIVREM, VT, Custom);
355 setOperationAction(ISD::UDIVREM, VT, Custom);
356 setOperationAction(ISD::ADDC, VT, Expand);
357 setOperationAction(ISD::SUBC, VT, Expand);
358 setOperationAction(ISD::ADDE, VT, Expand);
359 setOperationAction(ISD::SUBE, VT, Expand);
360 setOperationAction(ISD::SELECT, VT, Expand);
361 setOperationAction(ISD::VSELECT, VT, Expand);
362 setOperationAction(ISD::SELECT_CC, VT, Expand);
363 setOperationAction(ISD::XOR, VT, Expand);
364 setOperationAction(ISD::BSWAP, VT, Expand);
365 setOperationAction(ISD::CTPOP, VT, Expand);
366 setOperationAction(ISD::CTTZ, VT, Expand);
367 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
368 setOperationAction(ISD::CTLZ, VT, Expand);
369 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
370 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
373 static const MVT::SimpleValueType FloatVectorTypes[] = {
374 MVT::v2f32, MVT::v4f32
377 for (MVT VT : FloatVectorTypes) {
378 setOperationAction(ISD::FABS, VT, Expand);
379 setOperationAction(ISD::FMINNUM, VT, Expand);
380 setOperationAction(ISD::FMAXNUM, VT, Expand);
381 setOperationAction(ISD::FADD, VT, Expand);
382 setOperationAction(ISD::FCEIL, VT, Expand);
383 setOperationAction(ISD::FCOS, VT, Expand);
384 setOperationAction(ISD::FDIV, VT, Expand);
385 setOperationAction(ISD::FEXP2, VT, Expand);
386 setOperationAction(ISD::FLOG2, VT, Expand);
387 setOperationAction(ISD::FREM, VT, Expand);
388 setOperationAction(ISD::FPOW, VT, Expand);
389 setOperationAction(ISD::FFLOOR, VT, Expand);
390 setOperationAction(ISD::FTRUNC, VT, Expand);
391 setOperationAction(ISD::FMUL, VT, Expand);
392 setOperationAction(ISD::FMA, VT, Expand);
393 setOperationAction(ISD::FRINT, VT, Expand);
394 setOperationAction(ISD::FNEARBYINT, VT, Expand);
395 setOperationAction(ISD::FSQRT, VT, Expand);
396 setOperationAction(ISD::FSIN, VT, Expand);
397 setOperationAction(ISD::FSUB, VT, Expand);
398 setOperationAction(ISD::FNEG, VT, Expand);
399 setOperationAction(ISD::SELECT, VT, Expand);
400 setOperationAction(ISD::VSELECT, VT, Expand);
401 setOperationAction(ISD::SELECT_CC, VT, Expand);
402 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
403 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
406 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
407 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
409 setTargetDAGCombine(ISD::SHL);
410 setTargetDAGCombine(ISD::MUL);
411 setTargetDAGCombine(ISD::SELECT);
412 setTargetDAGCombine(ISD::SELECT_CC);
413 setTargetDAGCombine(ISD::STORE);
415 setTargetDAGCombine(ISD::FADD);
416 setTargetDAGCombine(ISD::FSUB);
418 setBooleanContents(ZeroOrNegativeOneBooleanContent);
419 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
421 setSchedulingPreference(Sched::RegPressure);
422 setJumpIsExpensive(true);
424 // SI at least has hardware support for floating point exceptions, but no way
425 // of using or handling them is implemented. They are also optional in OpenCL
427 setHasFloatingPointExceptions(false);
429 setSelectIsExpensive(false);
430 PredictableSelectIsExpensive = false;
432 // There are no integer divide instructions, and these expand to a pretty
433 // large sequence of instructions.
434 setIntDivIsCheap(false);
435 setPow2SDivIsCheap(false);
436 setFsqrtIsCheap(true);
438 // FIXME: Need to really handle these.
439 MaxStoresPerMemcpy = 4096;
440 MaxStoresPerMemmove = 4096;
441 MaxStoresPerMemset = 4096;
444 //===----------------------------------------------------------------------===//
445 // Target Information
446 //===----------------------------------------------------------------------===//
448 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
452 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
456 // The backend supports 32 and 64 bit floating point immediates.
457 // FIXME: Why are we reporting vectors of FP immediates as legal?
458 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
459 EVT ScalarVT = VT.getScalarType();
460 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
463 // We don't want to shrink f64 / f32 constants.
464 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
465 EVT ScalarVT = VT.getScalarType();
466 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
469 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
473 unsigned NewSize = NewVT.getStoreSizeInBits();
475 // If we are reducing to a 32-bit load, this is always better.
479 EVT OldVT = N->getValueType(0);
480 unsigned OldSize = OldVT.getStoreSizeInBits();
482 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
483 // extloads, so doing one requires using a buffer_load. In cases where we
484 // still couldn't use a scalar load, using the wider load shouldn't really
487 // If the old size already had to be an extload, there's no harm in continuing
488 // to reduce the width.
489 return (OldSize < 32);
492 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
494 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
497 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
498 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
500 return ((LScalarSize <= CastScalarSize) ||
501 (CastScalarSize >= 32) ||
505 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
506 // profitable with the expansion for 64-bit since it's generally good to
508 // FIXME: These should really have the size as a parameter.
509 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
513 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
517 //===---------------------------------------------------------------------===//
519 //===---------------------------------------------------------------------===//
521 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
522 assert(VT.isFloatingPoint());
523 return VT == MVT::f32 || VT == MVT::f64;
526 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
527 assert(VT.isFloatingPoint());
528 return VT == MVT::f32 || VT == MVT::f64;
531 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
537 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
538 // Truncate is just accessing a subregister.
539 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
542 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
543 // Truncate is just accessing a subregister.
544 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
545 (Dest->getPrimitiveSizeInBits() % 32 == 0);
548 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
549 unsigned SrcSize = Src->getScalarSizeInBits();
550 unsigned DestSize = Dest->getScalarSizeInBits();
552 return SrcSize == 32 && DestSize == 64;
555 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
556 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
557 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
558 // this will enable reducing 64-bit operations the 32-bit, which is always
560 return Src == MVT::i32 && Dest == MVT::i64;
563 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
564 return isZExtFree(Val.getValueType(), VT2);
567 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
568 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
569 // limited number of native 64-bit operations. Shrinking an operation to fit
570 // in a single 32-bit register should always be helpful. As currently used,
571 // this is much less general than the name suggests, and is only used in
572 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
573 // not profitable, and may actually be harmful.
574 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
577 //===---------------------------------------------------------------------===//
578 // TargetLowering Callbacks
579 //===---------------------------------------------------------------------===//
581 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
582 const SmallVectorImpl<ISD::InputArg> &Ins) const {
584 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
587 SDValue AMDGPUTargetLowering::LowerReturn(
589 CallingConv::ID CallConv,
591 const SmallVectorImpl<ISD::OutputArg> &Outs,
592 const SmallVectorImpl<SDValue> &OutVals,
593 SDLoc DL, SelectionDAG &DAG) const {
594 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
597 //===---------------------------------------------------------------------===//
598 // Target specific lowering
599 //===---------------------------------------------------------------------===//
601 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
602 SmallVectorImpl<SDValue> &InVals) const {
603 SDValue Callee = CLI.Callee;
604 SelectionDAG &DAG = CLI.DAG;
606 const Function &Fn = *DAG.getMachineFunction().getFunction();
608 StringRef FuncName("<unknown>");
610 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
611 FuncName = G->getSymbol();
612 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
613 FuncName = G->getGlobal()->getName();
615 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
616 DAG.getContext()->diagnose(NoCalls);
620 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
621 SelectionDAG &DAG) const {
622 switch (Op.getOpcode()) {
624 Op.getNode()->dump();
625 llvm_unreachable("Custom lowering code for this"
626 "instruction is not implemented yet!");
628 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
629 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
630 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
631 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
632 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
633 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
634 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
635 case ISD::FREM: return LowerFREM(Op, DAG);
636 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
637 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
638 case ISD::FRINT: return LowerFRINT(Op, DAG);
639 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
640 case ISD::FROUND: return LowerFROUND(Op, DAG);
641 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
642 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
643 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
644 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
645 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
650 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
651 SmallVectorImpl<SDValue> &Results,
652 SelectionDAG &DAG) const {
653 switch (N->getOpcode()) {
654 case ISD::SIGN_EXTEND_INREG:
655 // Different parts of legalization seem to interpret which type of
656 // sign_extend_inreg is the one to check for custom lowering. The extended
657 // from type is what really matters, but some places check for custom
658 // lowering of the result type. This results in trying to use
659 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
660 // nothing here and let the illegal result integer be handled normally.
663 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
667 Results.push_back(SDValue(Node, 0));
668 Results.push_back(SDValue(Node, 1));
669 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
671 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
675 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
676 if (Lowered.getNode())
677 Results.push_back(Lowered);
685 // FIXME: This implements accesses to initialized globals in the constant
686 // address space by copying them to private and accessing that. It does not
687 // properly handle illegal types or vectors. The private vector loads are not
688 // scalarized, and the illegal scalars hit an assertion. This technique will not
689 // work well with large initializers, and this should eventually be
690 // removed. Initialized globals should be placed into a data section that the
691 // runtime will load into a buffer before the kernel is executed. Uses of the
692 // global need to be replaced with a pointer loaded from an implicit kernel
693 // argument into this buffer holding the copy of the data, which will remove the
694 // need for any of this.
695 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
696 const GlobalValue *GV,
697 const SDValue &InitPtr,
699 SelectionDAG &DAG) const {
700 const DataLayout &TD = DAG.getDataLayout();
702 Type *InitTy = Init->getType();
704 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
705 EVT VT = EVT::getEVT(InitTy);
706 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
707 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, DL, VT), InitPtr,
708 MachinePointerInfo(UndefValue::get(PtrTy)), false,
709 false, TD.getPrefTypeAlignment(InitTy));
712 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
713 EVT VT = EVT::getEVT(CFP->getType());
714 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
715 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, DL, VT), InitPtr,
716 MachinePointerInfo(UndefValue::get(PtrTy)), false,
717 false, TD.getPrefTypeAlignment(CFP->getType()));
720 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
721 const StructLayout *SL = TD.getStructLayout(ST);
723 EVT PtrVT = InitPtr.getValueType();
724 SmallVector<SDValue, 8> Chains;
726 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
727 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), DL, PtrVT);
728 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
730 Constant *Elt = Init->getAggregateElement(I);
731 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
734 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
737 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
738 EVT PtrVT = InitPtr.getValueType();
740 unsigned NumElements;
741 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
742 NumElements = AT->getNumElements();
743 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
744 NumElements = VT->getNumElements();
746 llvm_unreachable("Unexpected type");
748 unsigned EltSize = TD.getTypeAllocSize(SeqTy->getElementType());
749 SmallVector<SDValue, 8> Chains;
750 for (unsigned i = 0; i < NumElements; ++i) {
751 SDValue Offset = DAG.getConstant(i * EltSize, DL, PtrVT);
752 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
754 Constant *Elt = Init->getAggregateElement(i);
755 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
758 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
761 if (isa<UndefValue>(Init)) {
762 EVT VT = EVT::getEVT(InitTy);
763 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
764 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
765 MachinePointerInfo(UndefValue::get(PtrTy)), false,
766 false, TD.getPrefTypeAlignment(InitTy));
770 llvm_unreachable("Unhandled constant initializer");
773 static bool hasDefinedInitializer(const GlobalValue *GV) {
774 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
775 if (!GVar || !GVar->hasInitializer())
778 if (isa<UndefValue>(GVar->getInitializer()))
784 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
786 SelectionDAG &DAG) const {
788 const DataLayout &DL = DAG.getDataLayout();
789 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
790 const GlobalValue *GV = G->getGlobal();
792 switch (G->getAddressSpace()) {
793 case AMDGPUAS::LOCAL_ADDRESS: {
794 // XXX: What does the value of G->getOffset() mean?
795 assert(G->getOffset() == 0 &&
796 "Do not know what to do with an non-zero offset");
798 // TODO: We could emit code to handle the initialization somewhere.
799 if (hasDefinedInitializer(GV))
803 if (MFI->LocalMemoryObjects.count(GV) == 0) {
804 uint64_t Size = DL.getTypeAllocSize(GV->getType()->getElementType());
805 Offset = MFI->LDSSize;
806 MFI->LocalMemoryObjects[GV] = Offset;
807 // XXX: Account for alignment?
808 MFI->LDSSize += Size;
810 Offset = MFI->LocalMemoryObjects[GV];
813 return DAG.getConstant(Offset, SDLoc(Op),
814 getPointerTy(DL, AMDGPUAS::LOCAL_ADDRESS));
816 case AMDGPUAS::CONSTANT_ADDRESS: {
817 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
818 Type *EltType = GV->getType()->getElementType();
819 unsigned Size = DL.getTypeAllocSize(EltType);
820 unsigned Alignment = DL.getPrefTypeAlignment(EltType);
822 MVT PrivPtrVT = getPointerTy(DL, AMDGPUAS::PRIVATE_ADDRESS);
823 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
825 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
826 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
828 const GlobalVariable *Var = cast<GlobalVariable>(GV);
829 if (!Var->hasInitializer()) {
830 // This has no use, but bugpoint will hit it.
831 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
834 const Constant *Init = Var->getInitializer();
835 SmallVector<SDNode*, 8> WorkList;
837 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
838 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
839 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
841 WorkList.push_back(*I);
843 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
844 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
845 E = WorkList.end(); I != E; ++I) {
846 SmallVector<SDValue, 8> Ops;
847 Ops.push_back(Chain);
848 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
849 Ops.push_back((*I)->getOperand(i));
851 DAG.UpdateNodeOperands(*I, Ops);
853 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
857 const Function &Fn = *DAG.getMachineFunction().getFunction();
858 DiagnosticInfoUnsupported BadInit(Fn,
859 "initializer for address space");
860 DAG.getContext()->diagnose(BadInit);
864 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
865 SelectionDAG &DAG) const {
866 SmallVector<SDValue, 8> Args;
868 for (const SDUse &U : Op->ops())
869 DAG.ExtractVectorElements(U.get(), Args);
871 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
874 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
875 SelectionDAG &DAG) const {
877 SmallVector<SDValue, 8> Args;
878 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
879 EVT VT = Op.getValueType();
880 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
881 VT.getVectorNumElements());
883 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
886 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
887 SelectionDAG &DAG) const {
889 MachineFunction &MF = DAG.getMachineFunction();
890 const AMDGPUFrameLowering *TFL = Subtarget->getFrameLowering();
892 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
894 unsigned FrameIndex = FIN->getIndex();
895 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
896 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), SDLoc(Op),
900 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
901 SelectionDAG &DAG) const {
902 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
904 EVT VT = Op.getValueType();
906 switch (IntrinsicID) {
908 case AMDGPUIntrinsic::AMDGPU_abs:
909 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
910 return LowerIntrinsicIABS(Op, DAG);
911 case AMDGPUIntrinsic::AMDGPU_lrp:
912 return LowerIntrinsicLRP(Op, DAG);
914 case AMDGPUIntrinsic::AMDGPU_clamp:
915 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
916 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
917 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
919 case Intrinsic::AMDGPU_div_scale: {
920 // 3rd parameter required to be a constant.
921 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
923 return DAG.getUNDEF(VT);
925 // Translate to the operands expected by the machine instruction. The
926 // first parameter must be the same as the first instruction.
927 SDValue Numerator = Op.getOperand(1);
928 SDValue Denominator = Op.getOperand(2);
930 // Note this order is opposite of the machine instruction's operations,
931 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
932 // intrinsic has the numerator as the first operand to match a normal
933 // division operation.
935 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
937 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
938 Denominator, Numerator);
941 case Intrinsic::AMDGPU_div_fmas:
942 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
943 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
946 case Intrinsic::AMDGPU_div_fixup:
947 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
948 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
950 case Intrinsic::AMDGPU_trig_preop:
951 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
952 Op.getOperand(1), Op.getOperand(2));
954 case Intrinsic::AMDGPU_rcp:
955 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
957 case Intrinsic::AMDGPU_rsq:
958 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
960 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
961 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
963 case Intrinsic::AMDGPU_rsq_clamped:
964 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
965 Type *Type = VT.getTypeForEVT(*DAG.getContext());
966 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
967 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
969 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
970 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
971 DAG.getConstantFP(Max, DL, VT));
972 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
973 DAG.getConstantFP(Min, DL, VT));
975 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
978 case Intrinsic::AMDGPU_ldexp:
979 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
982 case AMDGPUIntrinsic::AMDGPU_imax:
983 return DAG.getNode(ISD::SMAX, DL, VT, Op.getOperand(1),
985 case AMDGPUIntrinsic::AMDGPU_umax:
986 return DAG.getNode(ISD::UMAX, DL, VT, Op.getOperand(1),
988 case AMDGPUIntrinsic::AMDGPU_imin:
989 return DAG.getNode(ISD::SMIN, DL, VT, Op.getOperand(1),
991 case AMDGPUIntrinsic::AMDGPU_umin:
992 return DAG.getNode(ISD::UMIN, DL, VT, Op.getOperand(1),
995 case AMDGPUIntrinsic::AMDGPU_umul24:
996 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
997 Op.getOperand(1), Op.getOperand(2));
999 case AMDGPUIntrinsic::AMDGPU_imul24:
1000 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
1001 Op.getOperand(1), Op.getOperand(2));
1003 case AMDGPUIntrinsic::AMDGPU_umad24:
1004 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
1005 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
1007 case AMDGPUIntrinsic::AMDGPU_imad24:
1008 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
1009 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
1011 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
1012 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
1014 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
1015 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
1017 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
1018 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
1020 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
1021 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
1023 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
1024 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
1029 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
1030 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
1035 case AMDGPUIntrinsic::AMDGPU_bfi:
1036 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
1041 case AMDGPUIntrinsic::AMDGPU_bfm:
1042 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
1046 case AMDGPUIntrinsic::AMDGPU_brev:
1047 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
1049 case Intrinsic::AMDGPU_class:
1050 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
1051 Op.getOperand(1), Op.getOperand(2));
1053 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
1054 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
1056 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
1057 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
1058 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
1059 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
1063 ///IABS(a) = SMAX(sub(0, a), a)
1064 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
1065 SelectionDAG &DAG) const {
1067 EVT VT = Op.getValueType();
1068 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1071 return DAG.getNode(ISD::SMAX, DL, VT, Neg, Op.getOperand(1));
1074 /// Linear Interpolation
1075 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
1076 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
1077 SelectionDAG &DAG) const {
1079 EVT VT = Op.getValueType();
1080 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
1081 DAG.getConstantFP(1.0f, DL, MVT::f32),
1083 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
1085 return DAG.getNode(ISD::FADD, DL, VT,
1086 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
1090 /// \brief Generate Min/Max node
1091 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,
1098 DAGCombinerInfo &DCI) const {
1099 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1102 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1105 SelectionDAG &DAG = DCI.DAG;
1106 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1115 case ISD::SETFALSE2:
1124 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1125 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1131 // Ordered. Assume ordered for undefined.
1133 // Only do this after legalization to avoid interfering with other combines
1134 // which might occur.
1135 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1136 !DCI.isCalledByLegalizer())
1139 // We need to permute the operands to get the correct NaN behavior. The
1140 // selected operand is the second one based on the failing compare with NaN,
1141 // so permute it based on the compare type the hardware uses.
1143 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1144 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1149 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1150 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1156 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1157 !DCI.isCalledByLegalizer())
1161 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1162 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1164 case ISD::SETCC_INVALID:
1165 llvm_unreachable("Invalid setcc condcode!");
1170 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1171 SelectionDAG &DAG) const {
1172 LoadSDNode *Load = cast<LoadSDNode>(Op);
1173 EVT MemVT = Load->getMemoryVT();
1174 EVT MemEltVT = MemVT.getVectorElementType();
1176 EVT LoadVT = Op.getValueType();
1177 EVT EltVT = LoadVT.getVectorElementType();
1178 EVT PtrVT = Load->getBasePtr().getValueType();
1180 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1181 SmallVector<SDValue, 8> Loads;
1182 SmallVector<SDValue, 8> Chains;
1185 unsigned MemEltSize = MemEltVT.getStoreSize();
1186 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1188 for (unsigned i = 0; i < NumElts; ++i) {
1189 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1190 DAG.getConstant(i * MemEltSize, SL, PtrVT));
1193 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1194 Load->getChain(), Ptr,
1195 SrcValue.getWithOffset(i * MemEltSize),
1196 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1197 Load->isInvariant(), Load->getAlignment());
1198 Loads.push_back(NewLoad.getValue(0));
1199 Chains.push_back(NewLoad.getValue(1));
1203 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1204 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1207 return DAG.getMergeValues(Ops, SL);
1210 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1211 SelectionDAG &DAG) const {
1212 EVT VT = Op.getValueType();
1214 // If this is a 2 element vector, we really want to scalarize and not create
1215 // weird 1 element vectors.
1216 if (VT.getVectorNumElements() == 2)
1217 return ScalarizeVectorLoad(Op, DAG);
1219 LoadSDNode *Load = cast<LoadSDNode>(Op);
1220 SDValue BasePtr = Load->getBasePtr();
1221 EVT PtrVT = BasePtr.getValueType();
1222 EVT MemVT = Load->getMemoryVT();
1224 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1227 EVT LoMemVT, HiMemVT;
1230 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1231 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1232 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1234 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1235 Load->getChain(), BasePtr,
1237 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1238 Load->isInvariant(), Load->getAlignment());
1240 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1241 DAG.getConstant(LoMemVT.getStoreSize(), SL,
1245 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1246 Load->getChain(), HiPtr,
1247 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1248 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1249 Load->isInvariant(), Load->getAlignment());
1252 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1253 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1254 LoLoad.getValue(1), HiLoad.getValue(1))
1257 return DAG.getMergeValues(Ops, SL);
1260 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1261 SelectionDAG &DAG) const {
1262 StoreSDNode *Store = cast<StoreSDNode>(Op);
1263 EVT MemVT = Store->getMemoryVT();
1264 unsigned MemBits = MemVT.getSizeInBits();
1266 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1267 // truncating store into an i32 store.
1268 // XXX: We could also handle optimize other vector bitwidths.
1269 if (!MemVT.isVector() || MemBits > 32) {
1274 SDValue Value = Store->getValue();
1275 EVT VT = Value.getValueType();
1276 EVT ElemVT = VT.getVectorElementType();
1277 SDValue Ptr = Store->getBasePtr();
1278 EVT MemEltVT = MemVT.getVectorElementType();
1279 unsigned MemEltBits = MemEltVT.getSizeInBits();
1280 unsigned MemNumElements = MemVT.getVectorNumElements();
1281 unsigned PackedSize = MemVT.getStoreSizeInBits();
1282 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, DL, MVT::i32);
1284 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1286 SDValue PackedValue;
1287 for (unsigned i = 0; i < MemNumElements; ++i) {
1288 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1289 DAG.getConstant(i, DL, MVT::i32));
1290 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1291 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1293 SDValue Shift = DAG.getConstant(MemEltBits * i, DL, MVT::i32);
1294 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1299 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1303 if (PackedSize < 32) {
1304 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1305 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1306 Store->getMemOperand()->getPointerInfo(),
1308 Store->isNonTemporal(), Store->isVolatile(),
1309 Store->getAlignment());
1312 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1313 Store->getMemOperand()->getPointerInfo(),
1314 Store->isVolatile(), Store->isNonTemporal(),
1315 Store->getAlignment());
1318 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1319 SelectionDAG &DAG) const {
1320 StoreSDNode *Store = cast<StoreSDNode>(Op);
1321 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1322 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1323 EVT PtrVT = Store->getBasePtr().getValueType();
1324 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1327 SmallVector<SDValue, 8> Chains;
1329 unsigned EltSize = MemEltVT.getStoreSize();
1330 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1332 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1333 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1335 DAG.getConstant(i, SL, MVT::i32));
1337 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), SL, PtrVT);
1338 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1340 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1341 SrcValue.getWithOffset(i * EltSize),
1342 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1343 Store->getAlignment());
1344 Chains.push_back(NewStore);
1347 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1350 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1351 SelectionDAG &DAG) const {
1352 StoreSDNode *Store = cast<StoreSDNode>(Op);
1353 SDValue Val = Store->getValue();
1354 EVT VT = Val.getValueType();
1356 // If this is a 2 element vector, we really want to scalarize and not create
1357 // weird 1 element vectors.
1358 if (VT.getVectorNumElements() == 2)
1359 return ScalarizeVectorStore(Op, DAG);
1361 EVT MemVT = Store->getMemoryVT();
1362 SDValue Chain = Store->getChain();
1363 SDValue BasePtr = Store->getBasePtr();
1367 EVT LoMemVT, HiMemVT;
1370 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1371 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1372 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1374 EVT PtrVT = BasePtr.getValueType();
1375 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1376 DAG.getConstant(LoMemVT.getStoreSize(), SL,
1379 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1381 = DAG.getTruncStore(Chain, SL, Lo,
1385 Store->isNonTemporal(),
1386 Store->isVolatile(),
1387 Store->getAlignment());
1389 = DAG.getTruncStore(Chain, SL, Hi,
1391 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1393 Store->isNonTemporal(),
1394 Store->isVolatile(),
1395 Store->getAlignment());
1397 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1401 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1403 LoadSDNode *Load = cast<LoadSDNode>(Op);
1404 ISD::LoadExtType ExtType = Load->getExtensionType();
1405 EVT VT = Op.getValueType();
1406 EVT MemVT = Load->getMemoryVT();
1408 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1409 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1410 // FIXME: Copied from PPC
1411 // First, load into 32 bits, then truncate to 1 bit.
1413 SDValue Chain = Load->getChain();
1414 SDValue BasePtr = Load->getBasePtr();
1415 MachineMemOperand *MMO = Load->getMemOperand();
1417 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1418 BasePtr, MVT::i8, MMO);
1421 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1425 return DAG.getMergeValues(Ops, DL);
1428 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1429 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1430 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1433 // <SI && AS=PRIVATE && EXTLOAD && size < 32bit,
1434 // register (2-)byte extract.
1436 // Get Register holding the target.
1437 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1438 DAG.getConstant(2, DL, MVT::i32));
1439 // Load the Register.
1440 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1441 Load->getChain(), Ptr,
1442 DAG.getTargetConstant(0, DL, MVT::i32),
1445 // Get offset within the register.
1446 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1448 DAG.getConstant(0x3, DL, MVT::i32));
1450 // Bit offset of target byte (byteIdx * 8).
1451 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1452 DAG.getConstant(3, DL, MVT::i32));
1454 // Shift to the right.
1455 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1457 // Eliminate the upper bits by setting them to ...
1458 EVT MemEltVT = MemVT.getScalarType();
1461 if (ExtType == ISD::SEXTLOAD) {
1462 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1465 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1469 return DAG.getMergeValues(Ops, DL);
1474 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1478 return DAG.getMergeValues(Ops, DL);
1481 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1483 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1484 if (Result.getNode()) {
1488 StoreSDNode *Store = cast<StoreSDNode>(Op);
1489 SDValue Chain = Store->getChain();
1490 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1491 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1492 Store->getValue().getValueType().isVector()) {
1493 return ScalarizeVectorStore(Op, DAG);
1496 EVT MemVT = Store->getMemoryVT();
1497 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1498 MemVT.bitsLT(MVT::i32)) {
1500 if (Store->getMemoryVT() == MVT::i8) {
1502 } else if (Store->getMemoryVT() == MVT::i16) {
1505 SDValue BasePtr = Store->getBasePtr();
1506 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1507 DAG.getConstant(2, DL, MVT::i32));
1508 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1510 DAG.getTargetConstant(0, DL, MVT::i32));
1512 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1513 DAG.getConstant(0x3, DL, MVT::i32));
1515 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1516 DAG.getConstant(3, DL, MVT::i32));
1518 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1521 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1523 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1524 MaskedValue, ShiftAmt);
1526 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32,
1527 DAG.getConstant(Mask, DL, MVT::i32),
1529 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1530 DAG.getConstant(0xffffffff, DL, MVT::i32));
1531 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1533 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1534 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1536 DAG.getTargetConstant(0, DL, MVT::i32));
1541 // This is a shortcut for integer division because we have fast i32<->f32
1542 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1543 // float is enough to accurately represent up to a 24-bit integer.
1544 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1546 EVT VT = Op.getValueType();
1547 SDValue LHS = Op.getOperand(0);
1548 SDValue RHS = Op.getOperand(1);
1549 MVT IntVT = MVT::i32;
1550 MVT FltVT = MVT::f32;
1552 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1553 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1555 if (VT.isVector()) {
1556 unsigned NElts = VT.getVectorNumElements();
1557 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1558 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1561 unsigned BitSize = VT.getScalarType().getSizeInBits();
1563 SDValue jq = DAG.getConstant(1, DL, IntVT);
1566 // char|short jq = ia ^ ib;
1567 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1569 // jq = jq >> (bitsize - 2)
1570 jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1571 DAG.getConstant(BitSize - 2, DL, VT));
1574 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1577 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1580 // int ia = (int)LHS;
1582 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1584 // int ib, (int)RHS;
1586 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1588 // float fa = (float)ia;
1589 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1591 // float fb = (float)ib;
1592 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1594 // float fq = native_divide(fa, fb);
1595 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1596 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1599 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1601 // float fqneg = -fq;
1602 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1604 // float fr = mad(fqneg, fb, fa);
1605 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1606 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1608 // int iq = (int)fq;
1609 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1612 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1615 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1617 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1619 // int cv = fr >= fb;
1620 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1622 // jq = (cv ? jq : 0);
1623 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1625 // dst = trunc/extend to legal type
1626 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1629 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1631 // Rem needs compensation, it's easier to recompute it
1632 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1633 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1639 return DAG.getMergeValues(Res, DL);
1642 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1644 SmallVectorImpl<SDValue> &Results) const {
1645 assert(Op.getValueType() == MVT::i64);
1648 EVT VT = Op.getValueType();
1649 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1651 SDValue one = DAG.getConstant(1, DL, HalfVT);
1652 SDValue zero = DAG.getConstant(0, DL, HalfVT);
1655 SDValue LHS = Op.getOperand(0);
1656 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
1657 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
1659 SDValue RHS = Op.getOperand(1);
1660 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
1661 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
1663 if (VT == MVT::i64 &&
1664 DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1665 DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1667 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1670 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(0), zero);
1671 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(1), zero);
1672 Results.push_back(DIV);
1673 Results.push_back(REM);
1677 // Get Speculative values
1678 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1679 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1681 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
1682 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, zero);
1684 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
1685 SDValue DIV_Lo = zero;
1687 const unsigned halfBitWidth = HalfVT.getSizeInBits();
1689 for (unsigned i = 0; i < halfBitWidth; ++i) {
1690 const unsigned bitPos = halfBitWidth - i - 1;
1691 SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
1692 // Get value of high bit
1693 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1694 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
1695 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1698 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
1700 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1702 SDValue BIT = DAG.getConstant(1 << bitPos, DL, HalfVT);
1703 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
1705 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1708 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1709 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1712 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
1713 Results.push_back(DIV);
1714 Results.push_back(REM);
1717 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1718 SelectionDAG &DAG) const {
1720 EVT VT = Op.getValueType();
1722 if (VT == MVT::i64) {
1723 SmallVector<SDValue, 2> Results;
1724 LowerUDIVREM64(Op, DAG, Results);
1725 return DAG.getMergeValues(Results, DL);
1728 SDValue Num = Op.getOperand(0);
1729 SDValue Den = Op.getOperand(1);
1731 if (VT == MVT::i32) {
1732 if (DAG.MaskedValueIsZero(Num, APInt::getHighBitsSet(32, 8)) &&
1733 DAG.MaskedValueIsZero(Den, APInt::getHighBitsSet(32, 8))) {
1734 // TODO: We technically could do this for i64, but shouldn't that just be
1735 // handled by something generally reducing 64-bit division on 32-bit
1736 // values to 32-bit?
1737 return LowerDIVREM24(Op, DAG, false);
1741 // RCP = URECIP(Den) = 2^32 / Den + e
1742 // e is rounding error.
1743 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1745 // RCP_LO = mul(RCP, Den) */
1746 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1748 // RCP_HI = mulhu (RCP, Den) */
1749 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1751 // NEG_RCP_LO = -RCP_LO
1752 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1755 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1756 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1759 // Calculate the rounding error from the URECIP instruction
1760 // E = mulhu(ABS_RCP_LO, RCP)
1761 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1763 // RCP_A_E = RCP + E
1764 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1766 // RCP_S_E = RCP - E
1767 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1769 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1770 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1773 // Quotient = mulhu(Tmp0, Num)
1774 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1776 // Num_S_Remainder = Quotient * Den
1777 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1779 // Remainder = Num - Num_S_Remainder
1780 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1782 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1783 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1784 DAG.getConstant(-1, DL, VT),
1785 DAG.getConstant(0, DL, VT),
1787 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1788 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1790 DAG.getConstant(-1, DL, VT),
1791 DAG.getConstant(0, DL, VT),
1793 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1794 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1797 // Calculate Division result:
1799 // Quotient_A_One = Quotient + 1
1800 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1801 DAG.getConstant(1, DL, VT));
1803 // Quotient_S_One = Quotient - 1
1804 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1805 DAG.getConstant(1, DL, VT));
1807 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1808 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1809 Quotient, Quotient_A_One, ISD::SETEQ);
1811 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1812 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1813 Quotient_S_One, Div, ISD::SETEQ);
1815 // Calculate Rem result:
1817 // Remainder_S_Den = Remainder - Den
1818 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1820 // Remainder_A_Den = Remainder + Den
1821 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1823 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1824 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1825 Remainder, Remainder_S_Den, ISD::SETEQ);
1827 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1828 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1829 Remainder_A_Den, Rem, ISD::SETEQ);
1834 return DAG.getMergeValues(Ops, DL);
1837 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1838 SelectionDAG &DAG) const {
1840 EVT VT = Op.getValueType();
1842 SDValue LHS = Op.getOperand(0);
1843 SDValue RHS = Op.getOperand(1);
1845 SDValue Zero = DAG.getConstant(0, DL, VT);
1846 SDValue NegOne = DAG.getConstant(-1, DL, VT);
1848 if (VT == MVT::i32 &&
1849 DAG.ComputeNumSignBits(LHS) > 8 &&
1850 DAG.ComputeNumSignBits(RHS) > 8) {
1851 return LowerDIVREM24(Op, DAG, true);
1853 if (VT == MVT::i64 &&
1854 DAG.ComputeNumSignBits(LHS) > 32 &&
1855 DAG.ComputeNumSignBits(RHS) > 32) {
1856 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1859 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1860 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1861 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1864 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1865 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1867 return DAG.getMergeValues(Res, DL);
1870 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1871 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1872 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1873 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1875 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1876 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1878 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1879 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1881 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1882 SDValue Rem = Div.getValue(1);
1884 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1885 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1887 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1888 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1894 return DAG.getMergeValues(Res, DL);
1897 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1898 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1900 EVT VT = Op.getValueType();
1901 SDValue X = Op.getOperand(0);
1902 SDValue Y = Op.getOperand(1);
1904 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1905 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1906 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1908 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1911 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1913 SDValue Src = Op.getOperand(0);
1915 // result = trunc(src)
1916 // if (src > 0.0 && src != result)
1919 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1921 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
1922 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1925 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
1927 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1928 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1929 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1931 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1932 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1935 static SDValue extractF64Exponent(SDValue Hi, SDLoc SL, SelectionDAG &DAG) {
1936 const unsigned FractBits = 52;
1937 const unsigned ExpBits = 11;
1939 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1941 DAG.getConstant(FractBits - 32, SL, MVT::i32),
1942 DAG.getConstant(ExpBits, SL, MVT::i32));
1943 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1944 DAG.getConstant(1023, SL, MVT::i32));
1949 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1951 SDValue Src = Op.getOperand(0);
1953 assert(Op.getValueType() == MVT::f64);
1955 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1956 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1958 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1960 // Extract the upper half, since this is where we will find the sign and
1962 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1964 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
1966 const unsigned FractBits = 52;
1968 // Extract the sign bit.
1969 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32);
1970 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1972 // Extend back to to 64-bits.
1973 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1975 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1977 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1978 const SDValue FractMask
1979 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64);
1981 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1982 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1983 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1986 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
1988 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
1990 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1991 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1993 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1994 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1996 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1999 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
2001 SDValue Src = Op.getOperand(0);
2003 assert(Op.getValueType() == MVT::f64);
2005 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
2006 SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
2007 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2009 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2010 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2012 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2014 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
2015 SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
2018 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2019 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2021 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2024 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2025 // FNEARBYINT and FRINT are the same, except in their handling of FP
2026 // exceptions. Those aren't really meaningful for us, and OpenCL only has
2027 // rint, so just treat them as equivalent.
2028 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2031 // XXX - May require not supporting f32 denormals?
2032 SDValue AMDGPUTargetLowering::LowerFROUND32(SDValue Op, SelectionDAG &DAG) const {
2034 SDValue X = Op.getOperand(0);
2036 SDValue T = DAG.getNode(ISD::FTRUNC, SL, MVT::f32, X);
2038 SDValue Diff = DAG.getNode(ISD::FSUB, SL, MVT::f32, X, T);
2040 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff);
2042 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f32);
2043 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
2044 const SDValue Half = DAG.getConstantFP(0.5, SL, MVT::f32);
2046 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f32, One, X);
2049 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
2051 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2053 SDValue Sel = DAG.getNode(ISD::SELECT, SL, MVT::f32, Cmp, SignOne, Zero);
2055 return DAG.getNode(ISD::FADD, SL, MVT::f32, T, Sel);
2058 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
2060 SDValue X = Op.getOperand(0);
2062 SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
2064 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2065 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2066 const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
2067 const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
2069 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2071 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2073 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
2075 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2077 const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL,
2080 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2081 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2082 DAG.getConstant(INT64_C(0x0008000000000000), SL,
2086 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2087 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
2088 DAG.getConstant(0, SL, MVT::i64), Tmp0,
2091 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2092 D, DAG.getConstant(0, SL, MVT::i64));
2093 SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
2095 K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2096 K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
2098 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2099 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2100 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
2102 SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
2104 DAG.getConstantFP(1.0, SL, MVT::f64),
2105 DAG.getConstantFP(0.0, SL, MVT::f64));
2107 SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
2109 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
2110 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
2115 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2116 EVT VT = Op.getValueType();
2119 return LowerFROUND32(Op, DAG);
2122 return LowerFROUND64(Op, DAG);
2124 llvm_unreachable("unhandled type");
2127 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2129 SDValue Src = Op.getOperand(0);
2131 // result = trunc(src);
2132 // if (src < 0.0 && src != result)
2135 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2137 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2138 const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
2141 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2143 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2144 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2145 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2147 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2148 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2151 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2152 bool Signed) const {
2154 SDValue Src = Op.getOperand(0);
2156 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2158 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2159 DAG.getConstant(0, SL, MVT::i32));
2160 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2161 DAG.getConstant(1, SL, MVT::i32));
2163 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2166 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2168 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2169 DAG.getConstant(32, SL, MVT::i32));
2171 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2174 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2175 SelectionDAG &DAG) const {
2176 SDValue S0 = Op.getOperand(0);
2177 if (S0.getValueType() != MVT::i64)
2180 EVT DestVT = Op.getValueType();
2181 if (DestVT == MVT::f64)
2182 return LowerINT_TO_FP64(Op, DAG, false);
2184 assert(DestVT == MVT::f32);
2188 // f32 uint_to_fp i64
2189 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2190 DAG.getConstant(0, DL, MVT::i32));
2191 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
2192 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2193 DAG.getConstant(1, DL, MVT::i32));
2194 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
2195 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
2196 DAG.getConstantFP(4294967296.0f, DL, MVT::f32)); // 2^32
2197 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
2200 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2201 SelectionDAG &DAG) const {
2202 SDValue Src = Op.getOperand(0);
2203 if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64)
2204 return LowerINT_TO_FP64(Op, DAG, true);
2209 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2210 bool Signed) const {
2213 SDValue Src = Op.getOperand(0);
2215 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2217 SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL,
2219 SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL,
2222 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2224 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2227 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2229 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2230 MVT::i32, FloorMul);
2231 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2233 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
2235 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2238 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2239 SelectionDAG &DAG) const {
2240 SDValue Src = Op.getOperand(0);
2242 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2243 return LowerFP64_TO_INT(Op, DAG, true);
2248 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2249 SelectionDAG &DAG) const {
2250 SDValue Src = Op.getOperand(0);
2252 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2253 return LowerFP64_TO_INT(Op, DAG, false);
2258 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2259 SelectionDAG &DAG) const {
2260 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2261 MVT VT = Op.getSimpleValueType();
2262 MVT ScalarVT = VT.getScalarType();
2267 SDValue Src = Op.getOperand(0);
2270 // TODO: Don't scalarize on Evergreen?
2271 unsigned NElts = VT.getVectorNumElements();
2272 SmallVector<SDValue, 8> Args;
2273 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2275 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2276 for (unsigned I = 0; I < NElts; ++I)
2277 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2279 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
2282 //===----------------------------------------------------------------------===//
2283 // Custom DAG optimizations
2284 //===----------------------------------------------------------------------===//
2286 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2287 APInt KnownZero, KnownOne;
2288 EVT VT = Op.getValueType();
2289 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2291 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2294 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2295 EVT VT = Op.getValueType();
2297 // In order for this to be a signed 24-bit value, bit 23, must
2299 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2300 // as unsigned 24-bit values.
2301 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2304 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2306 SelectionDAG &DAG = DCI.DAG;
2307 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2308 EVT VT = Op.getValueType();
2310 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2311 APInt KnownZero, KnownOne;
2312 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2313 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2314 DCI.CommitTargetLoweringOpt(TLO);
2317 template <typename IntTy>
2318 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
2319 uint32_t Offset, uint32_t Width, SDLoc DL) {
2320 if (Width + Offset < 32) {
2321 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2322 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2323 return DAG.getConstant(Result, DL, MVT::i32);
2326 return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2329 static bool usesAllNormalStores(SDNode *LoadVal) {
2330 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2331 if (!ISD::isNormalStore(*I))
2338 // If we have a copy of an illegal type, replace it with a load / store of an
2339 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2340 // instructions emitted when handling extloads and truncstores. Ideally we could
2341 // recognize the pack / unpack pattern to eliminate it.
2342 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2343 DAGCombinerInfo &DCI) const {
2344 if (!DCI.isBeforeLegalize())
2347 StoreSDNode *SN = cast<StoreSDNode>(N);
2348 SDValue Value = SN->getValue();
2349 EVT VT = Value.getValueType();
2351 if (isTypeLegal(VT) || SN->isVolatile() ||
2352 !ISD::isNormalLoad(Value.getNode()) || VT.getSizeInBits() < 8)
2355 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2356 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2359 EVT MemVT = LoadVal->getMemoryVT();
2362 SelectionDAG &DAG = DCI.DAG;
2363 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2365 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2367 LoadVal->getChain(),
2368 LoadVal->getBasePtr(),
2369 LoadVal->getOffset(),
2371 LoadVal->getMemOperand());
2373 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2374 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2376 return DAG.getStore(SN->getChain(), SL, NewLoad,
2377 SN->getBasePtr(), SN->getMemOperand());
2380 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
2381 DAGCombinerInfo &DCI) const {
2382 if (N->getValueType(0) != MVT::i64)
2385 // i64 (shl x, 32) -> (build_pair 0, x)
2387 // Doing this with moves theoretically helps MI optimizations that understand
2388 // copies. 2 v_mov_b32_e32 will have the same code size / cycle count as
2389 // v_lshl_b64. In the SALU case, I think this is slightly worse since it
2390 // doubles the code size and I'm unsure about cycle count.
2391 const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2392 if (!RHS || RHS->getZExtValue() != 32)
2395 SDValue LHS = N->getOperand(0);
2398 SelectionDAG &DAG = DCI.DAG;
2400 // Extract low 32-bits.
2401 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
2403 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2404 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, Zero, Lo);
2407 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2408 DAGCombinerInfo &DCI) const {
2409 EVT VT = N->getValueType(0);
2411 if (VT.isVector() || VT.getSizeInBits() > 32)
2414 SelectionDAG &DAG = DCI.DAG;
2417 SDValue N0 = N->getOperand(0);
2418 SDValue N1 = N->getOperand(1);
2421 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2422 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2423 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2424 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2425 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2426 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2427 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2428 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2433 // We need to use sext even for MUL_U24, because MUL_U24 is used
2434 // for signed multiply of 8 and 16-bit types.
2435 return DAG.getSExtOrTrunc(Mul, DL, VT);
2438 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2439 DAGCombinerInfo &DCI) const {
2440 SelectionDAG &DAG = DCI.DAG;
2443 switch(N->getOpcode()) {
2447 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2450 return performShlCombine(N, DCI);
2453 return performMulCombine(N, DCI);
2454 case AMDGPUISD::MUL_I24:
2455 case AMDGPUISD::MUL_U24: {
2456 SDValue N0 = N->getOperand(0);
2457 SDValue N1 = N->getOperand(1);
2458 simplifyI24(N0, DCI);
2459 simplifyI24(N1, DCI);
2463 SDValue Cond = N->getOperand(0);
2464 if (Cond.getOpcode() == ISD::SETCC && Cond.hasOneUse()) {
2465 EVT VT = N->getValueType(0);
2466 SDValue LHS = Cond.getOperand(0);
2467 SDValue RHS = Cond.getOperand(1);
2468 SDValue CC = Cond.getOperand(2);
2470 SDValue True = N->getOperand(1);
2471 SDValue False = N->getOperand(2);
2474 return CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
2479 case AMDGPUISD::BFE_I32:
2480 case AMDGPUISD::BFE_U32: {
2481 assert(!N->getValueType(0).isVector() &&
2482 "Vector handling of BFE not implemented");
2483 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2487 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2489 return DAG.getConstant(0, DL, MVT::i32);
2491 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2495 SDValue BitsFrom = N->getOperand(0);
2496 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2498 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2500 if (OffsetVal == 0) {
2501 // This is already sign / zero extended, so try to fold away extra BFEs.
2502 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2504 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2505 if (OpSignBits >= SignBits)
2508 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2510 // This is a sign_extend_inreg. Replace it to take advantage of existing
2511 // DAG Combines. If not eliminated, we will match back to BFE during
2514 // TODO: The sext_inreg of extended types ends, although we can could
2515 // handle them in a single BFE.
2516 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2517 DAG.getValueType(SmallVT));
2520 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2523 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2525 return constantFoldBFE<int32_t>(DAG,
2526 CVal->getSExtValue(),
2532 return constantFoldBFE<uint32_t>(DAG,
2533 CVal->getZExtValue(),
2539 if ((OffsetVal + WidthVal) >= 32) {
2540 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
2541 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2542 BitsFrom, ShiftVal);
2545 if (BitsFrom.hasOneUse()) {
2546 APInt Demanded = APInt::getBitsSet(32,
2548 OffsetVal + WidthVal);
2550 APInt KnownZero, KnownOne;
2551 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2552 !DCI.isBeforeLegalizeOps());
2553 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2554 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2555 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2556 KnownZero, KnownOne, TLO)) {
2557 DCI.CommitTargetLoweringOpt(TLO);
2565 return performStoreCombine(N, DCI);
2570 //===----------------------------------------------------------------------===//
2572 //===----------------------------------------------------------------------===//
2574 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2577 const SmallVectorImpl<ISD::InputArg> &Ins,
2578 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2580 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2581 if (Ins[i].ArgVT == Ins[i].VT) {
2582 OrigIns.push_back(Ins[i]);
2587 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2588 // Vector has been split into scalars.
2589 VT = Ins[i].ArgVT.getVectorElementType();
2590 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2591 Ins[i].ArgVT.getVectorElementType() !=
2592 Ins[i].VT.getVectorElementType()) {
2593 // Vector elements have been promoted
2596 // Vector has been spilt into smaller vectors.
2600 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2601 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2602 OrigIns.push_back(Arg);
2606 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2607 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2608 return CFP->isExactlyValue(1.0);
2610 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2611 return C->isAllOnesValue();
2616 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2617 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2618 return CFP->getValueAPF().isZero();
2620 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2621 return C->isNullValue();
2626 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2627 const TargetRegisterClass *RC,
2628 unsigned Reg, EVT VT) const {
2629 MachineFunction &MF = DAG.getMachineFunction();
2630 MachineRegisterInfo &MRI = MF.getRegInfo();
2631 unsigned VirtualRegister;
2632 if (!MRI.isLiveIn(Reg)) {
2633 VirtualRegister = MRI.createVirtualRegister(RC);
2634 MRI.addLiveIn(Reg, VirtualRegister);
2636 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2638 return DAG.getRegister(VirtualRegister, VT);
2641 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
2642 const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const {
2643 uint64_t ArgOffset = MFI->ABIArgOffset;
2648 return ArgOffset + 4;
2650 llvm_unreachable("unexpected implicit parameter type");
2653 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2655 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2656 switch ((AMDGPUISD::NodeType)Opcode) {
2657 case AMDGPUISD::FIRST_NUMBER: break;
2659 NODE_NAME_CASE(CALL);
2660 NODE_NAME_CASE(UMUL);
2661 NODE_NAME_CASE(RET_FLAG);
2662 NODE_NAME_CASE(BRANCH_COND);
2665 NODE_NAME_CASE(DWORDADDR)
2666 NODE_NAME_CASE(FRACT)
2667 NODE_NAME_CASE(CLAMP)
2668 NODE_NAME_CASE(COS_HW)
2669 NODE_NAME_CASE(SIN_HW)
2670 NODE_NAME_CASE(FMAX_LEGACY)
2671 NODE_NAME_CASE(FMIN_LEGACY)
2672 NODE_NAME_CASE(FMAX3)
2673 NODE_NAME_CASE(SMAX3)
2674 NODE_NAME_CASE(UMAX3)
2675 NODE_NAME_CASE(FMIN3)
2676 NODE_NAME_CASE(SMIN3)
2677 NODE_NAME_CASE(UMIN3)
2678 NODE_NAME_CASE(URECIP)
2679 NODE_NAME_CASE(DIV_SCALE)
2680 NODE_NAME_CASE(DIV_FMAS)
2681 NODE_NAME_CASE(DIV_FIXUP)
2682 NODE_NAME_CASE(TRIG_PREOP)
2685 NODE_NAME_CASE(RSQ_LEGACY)
2686 NODE_NAME_CASE(RSQ_CLAMPED)
2687 NODE_NAME_CASE(LDEXP)
2688 NODE_NAME_CASE(FP_CLASS)
2689 NODE_NAME_CASE(DOT4)
2690 NODE_NAME_CASE(CARRY)
2691 NODE_NAME_CASE(BORROW)
2692 NODE_NAME_CASE(BFE_U32)
2693 NODE_NAME_CASE(BFE_I32)
2696 NODE_NAME_CASE(BREV)
2697 NODE_NAME_CASE(MUL_U24)
2698 NODE_NAME_CASE(MUL_I24)
2699 NODE_NAME_CASE(MAD_U24)
2700 NODE_NAME_CASE(MAD_I24)
2701 NODE_NAME_CASE(TEXTURE_FETCH)
2702 NODE_NAME_CASE(EXPORT)
2703 NODE_NAME_CASE(CONST_ADDRESS)
2704 NODE_NAME_CASE(REGISTER_LOAD)
2705 NODE_NAME_CASE(REGISTER_STORE)
2706 NODE_NAME_CASE(LOAD_CONSTANT)
2707 NODE_NAME_CASE(LOAD_INPUT)
2708 NODE_NAME_CASE(SAMPLE)
2709 NODE_NAME_CASE(SAMPLEB)
2710 NODE_NAME_CASE(SAMPLED)
2711 NODE_NAME_CASE(SAMPLEL)
2712 NODE_NAME_CASE(CVT_F32_UBYTE0)
2713 NODE_NAME_CASE(CVT_F32_UBYTE1)
2714 NODE_NAME_CASE(CVT_F32_UBYTE2)
2715 NODE_NAME_CASE(CVT_F32_UBYTE3)
2716 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2717 NODE_NAME_CASE(CONST_DATA_PTR)
2718 case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
2719 NODE_NAME_CASE(SENDMSG)
2720 NODE_NAME_CASE(INTERP_MOV)
2721 NODE_NAME_CASE(INTERP_P1)
2722 NODE_NAME_CASE(INTERP_P2)
2723 NODE_NAME_CASE(STORE_MSKOR)
2724 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2725 case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break;
2730 SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
2731 DAGCombinerInfo &DCI,
2732 unsigned &RefinementSteps,
2733 bool &UseOneConstNR) const {
2734 SelectionDAG &DAG = DCI.DAG;
2735 EVT VT = Operand.getValueType();
2737 if (VT == MVT::f32) {
2738 RefinementSteps = 0;
2739 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
2742 // TODO: There is also f64 rsq instruction, but the documentation is less
2743 // clear on its precision.
2748 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
2749 DAGCombinerInfo &DCI,
2750 unsigned &RefinementSteps) const {
2751 SelectionDAG &DAG = DCI.DAG;
2752 EVT VT = Operand.getValueType();
2754 if (VT == MVT::f32) {
2755 // Reciprocal, < 1 ulp error.
2757 // This reciprocal approximation converges to < 0.5 ulp error with one
2758 // newton rhapson performed with two fused multiple adds (FMAs).
2760 RefinementSteps = 0;
2761 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
2764 // TODO: There is also f64 rcp instruction, but the documentation is less
2765 // clear on its precision.
2770 static void computeKnownBitsForMinMax(const SDValue Op0,
2774 const SelectionDAG &DAG,
2776 APInt Op0Zero, Op0One;
2777 APInt Op1Zero, Op1One;
2778 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2779 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2781 KnownZero = Op0Zero & Op1Zero;
2782 KnownOne = Op0One & Op1One;
2785 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2789 const SelectionDAG &DAG,
2790 unsigned Depth) const {
2792 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2796 unsigned Opc = Op.getOpcode();
2801 case ISD::INTRINSIC_WO_CHAIN: {
2802 // FIXME: The intrinsic should just use the node.
2803 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2804 case AMDGPUIntrinsic::AMDGPU_imax:
2805 case AMDGPUIntrinsic::AMDGPU_umax:
2806 case AMDGPUIntrinsic::AMDGPU_imin:
2807 case AMDGPUIntrinsic::AMDGPU_umin:
2808 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2809 KnownZero, KnownOne, DAG, Depth);
2817 case AMDGPUISD::CARRY:
2818 case AMDGPUISD::BORROW: {
2819 KnownZero = APInt::getHighBitsSet(32, 31);
2823 case AMDGPUISD::BFE_I32:
2824 case AMDGPUISD::BFE_U32: {
2825 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2829 unsigned BitWidth = 32;
2830 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2832 if (Opc == AMDGPUISD::BFE_U32)
2833 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2840 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2842 const SelectionDAG &DAG,
2843 unsigned Depth) const {
2844 switch (Op.getOpcode()) {
2845 case AMDGPUISD::BFE_I32: {
2846 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2850 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2851 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2852 if (!Offset || !Offset->isNullValue())
2855 // TODO: Could probably figure something out with non-0 offsets.
2856 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2857 return std::max(SignBits, Op0SignBits);
2860 case AMDGPUISD::BFE_U32: {
2861 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2862 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
2865 case AMDGPUISD::CARRY:
2866 case AMDGPUISD::BORROW: