1 //===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction defs that are common to all hw codegen
13 //===----------------------------------------------------------------------===//
15 class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
16 field bit isRegisterLoad = 0;
17 field bit isRegisterStore = 0;
19 let Namespace = "AMDGPU";
20 let OutOperandList = outs;
21 let InOperandList = ins;
23 let Pattern = pattern;
24 let Itinerary = NullALU;
26 let TSFlags{63} = isRegisterLoad;
27 let TSFlags{62} = isRegisterStore;
30 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
31 : AMDGPUInst<outs, ins, asm, pattern> {
33 field bits<32> Inst = 0xffffffff;
37 def FP32Denormals : Predicate<"Subtarget.hasFP32Denormals()">;
38 def FP64Denormals : Predicate<"Subtarget.hasFP64Denormals()">;
39 def UnsafeFPMath : Predicate<"TM.Options.UnsafeFPMath">;
41 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
42 def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
44 let OperandType = "OPERAND_IMMEDIATE" in {
46 def u32imm : Operand<i32> {
47 let PrintMethod = "printU32ImmOperand";
50 def u16imm : Operand<i16> {
51 let PrintMethod = "printU16ImmOperand";
54 def u8imm : Operand<i8> {
55 let PrintMethod = "printU8ImmOperand";
58 } // End OperandType = "OPERAND_IMMEDIATE"
60 //===--------------------------------------------------------------------===//
62 //===--------------------------------------------------------------------===//
63 def brtarget : Operand<OtherVT>;
65 //===----------------------------------------------------------------------===//
66 // PatLeafs for floating-point comparisons
67 //===----------------------------------------------------------------------===//
69 def COND_OEQ : PatLeaf <
71 [{return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;}]
74 def COND_ONE : PatLeaf <
76 [{return N->get() == ISD::SETONE || N->get() == ISD::SETNE;}]
79 def COND_OGT : PatLeaf <
81 [{return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;}]
84 def COND_OGE : PatLeaf <
86 [{return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;}]
89 def COND_OLT : PatLeaf <
91 [{return N->get() == ISD::SETOLT || N->get() == ISD::SETLT;}]
94 def COND_OLE : PatLeaf <
96 [{return N->get() == ISD::SETOLE || N->get() == ISD::SETLE;}]
100 def COND_O : PatLeaf <(cond), [{return N->get() == ISD::SETO;}]>;
101 def COND_UO : PatLeaf <(cond), [{return N->get() == ISD::SETUO;}]>;
103 //===----------------------------------------------------------------------===//
104 // PatLeafs for unsigned / unordered comparisons
105 //===----------------------------------------------------------------------===//
107 def COND_UEQ : PatLeaf <(cond), [{return N->get() == ISD::SETUEQ;}]>;
108 def COND_UNE : PatLeaf <(cond), [{return N->get() == ISD::SETUNE;}]>;
109 def COND_UGT : PatLeaf <(cond), [{return N->get() == ISD::SETUGT;}]>;
110 def COND_UGE : PatLeaf <(cond), [{return N->get() == ISD::SETUGE;}]>;
111 def COND_ULT : PatLeaf <(cond), [{return N->get() == ISD::SETULT;}]>;
112 def COND_ULE : PatLeaf <(cond), [{return N->get() == ISD::SETULE;}]>;
114 // XXX - For some reason R600 version is preferring to use unordered
116 def COND_UNE_NE : PatLeaf <
118 [{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
121 //===----------------------------------------------------------------------===//
122 // PatLeafs for signed comparisons
123 //===----------------------------------------------------------------------===//
125 def COND_SGT : PatLeaf <(cond), [{return N->get() == ISD::SETGT;}]>;
126 def COND_SGE : PatLeaf <(cond), [{return N->get() == ISD::SETGE;}]>;
127 def COND_SLT : PatLeaf <(cond), [{return N->get() == ISD::SETLT;}]>;
128 def COND_SLE : PatLeaf <(cond), [{return N->get() == ISD::SETLE;}]>;
130 //===----------------------------------------------------------------------===//
131 // PatLeafs for integer equality
132 //===----------------------------------------------------------------------===//
134 def COND_EQ : PatLeaf <
136 [{return N->get() == ISD::SETEQ || N->get() == ISD::SETUEQ;}]
139 def COND_NE : PatLeaf <
141 [{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}]
144 def COND_NULL : PatLeaf <
146 [{(void)N; return false;}]
149 //===----------------------------------------------------------------------===//
150 // Load/Store Pattern Fragments
151 //===----------------------------------------------------------------------===//
153 class PrivateMemOp <dag ops, dag frag> : PatFrag <ops, frag, [{
154 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
157 class PrivateLoad <SDPatternOperator op> : PrivateMemOp <
158 (ops node:$ptr), (op node:$ptr)
161 class PrivateStore <SDPatternOperator op> : PrivateMemOp <
162 (ops node:$value, node:$ptr), (op node:$value, node:$ptr)
165 def load_private : PrivateLoad <load>;
167 def truncstorei8_private : PrivateStore <truncstorei8>;
168 def truncstorei16_private : PrivateStore <truncstorei16>;
169 def store_private : PrivateStore <store>;
171 def global_store : PatFrag<(ops node:$val, node:$ptr),
172 (store node:$val, node:$ptr), [{
173 return isGlobalStore(dyn_cast<StoreSDNode>(N));
176 // Global address space loads
177 def global_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
178 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
181 // Constant address space loads
182 def constant_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
183 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
186 class AZExtLoadBase <SDPatternOperator ld_node>: PatFrag<(ops node:$ptr),
187 (ld_node node:$ptr), [{
188 LoadSDNode *L = cast<LoadSDNode>(N);
189 return L->getExtensionType() == ISD::ZEXTLOAD ||
190 L->getExtensionType() == ISD::EXTLOAD;
193 def az_extload : AZExtLoadBase <unindexedload>;
195 def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
196 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
199 def az_extloadi8_global : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
200 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
203 def sextloadi8_global : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
204 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
207 def az_extloadi8_constant : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
208 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
211 def sextloadi8_constant : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
212 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
215 def az_extloadi8_local : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
216 return isLocalLoad(dyn_cast<LoadSDNode>(N));
219 def sextloadi8_local : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
220 return isLocalLoad(dyn_cast<LoadSDNode>(N));
223 def extloadi8_private : PrivateLoad <az_extloadi8>;
224 def sextloadi8_private : PrivateLoad <sextloadi8>;
226 def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
227 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
230 def az_extloadi16_global : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
231 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
234 def sextloadi16_global : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
235 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
238 def az_extloadi16_constant : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
239 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
242 def sextloadi16_constant : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
243 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
246 def az_extloadi16_local : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
247 return isLocalLoad(dyn_cast<LoadSDNode>(N));
250 def sextloadi16_local : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
251 return isLocalLoad(dyn_cast<LoadSDNode>(N));
254 def extloadi16_private : PrivateLoad <az_extloadi16>;
255 def sextloadi16_private : PrivateLoad <sextloadi16>;
257 def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
258 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
261 def az_extloadi32_global : PatFrag<(ops node:$ptr),
262 (az_extloadi32 node:$ptr), [{
263 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
266 def az_extloadi32_flat : PatFrag<(ops node:$ptr),
267 (az_extloadi32 node:$ptr), [{
268 return isFlatLoad(dyn_cast<LoadSDNode>(N));
271 def az_extloadi32_constant : PatFrag<(ops node:$ptr),
272 (az_extloadi32 node:$ptr), [{
273 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
276 def truncstorei8_global : PatFrag<(ops node:$val, node:$ptr),
277 (truncstorei8 node:$val, node:$ptr), [{
278 return isGlobalStore(dyn_cast<StoreSDNode>(N));
281 def truncstorei16_global : PatFrag<(ops node:$val, node:$ptr),
282 (truncstorei16 node:$val, node:$ptr), [{
283 return isGlobalStore(dyn_cast<StoreSDNode>(N));
286 def local_store : PatFrag<(ops node:$val, node:$ptr),
287 (store node:$val, node:$ptr), [{
288 return isLocalStore(dyn_cast<StoreSDNode>(N));
291 def truncstorei8_local : PatFrag<(ops node:$val, node:$ptr),
292 (truncstorei8 node:$val, node:$ptr), [{
293 return isLocalStore(dyn_cast<StoreSDNode>(N));
296 def truncstorei16_local : PatFrag<(ops node:$val, node:$ptr),
297 (truncstorei16 node:$val, node:$ptr), [{
298 return isLocalStore(dyn_cast<StoreSDNode>(N));
301 def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
302 return isLocalLoad(dyn_cast<LoadSDNode>(N));
305 class Aligned8Bytes <dag ops, dag frag> : PatFrag <ops, frag, [{
306 return cast<MemSDNode>(N)->getAlignment() % 8 == 0;
309 def local_load_aligned8bytes : Aligned8Bytes <
310 (ops node:$ptr), (local_load node:$ptr)
313 def local_store_aligned8bytes : Aligned8Bytes <
314 (ops node:$val, node:$ptr), (local_store node:$val, node:$ptr)
317 class local_binary_atomic_op<SDNode atomic_op> :
318 PatFrag<(ops node:$ptr, node:$value),
319 (atomic_op node:$ptr, node:$value), [{
320 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
324 def atomic_swap_local : local_binary_atomic_op<atomic_swap>;
325 def atomic_load_add_local : local_binary_atomic_op<atomic_load_add>;
326 def atomic_load_sub_local : local_binary_atomic_op<atomic_load_sub>;
327 def atomic_load_and_local : local_binary_atomic_op<atomic_load_and>;
328 def atomic_load_or_local : local_binary_atomic_op<atomic_load_or>;
329 def atomic_load_xor_local : local_binary_atomic_op<atomic_load_xor>;
330 def atomic_load_nand_local : local_binary_atomic_op<atomic_load_nand>;
331 def atomic_load_min_local : local_binary_atomic_op<atomic_load_min>;
332 def atomic_load_max_local : local_binary_atomic_op<atomic_load_max>;
333 def atomic_load_umin_local : local_binary_atomic_op<atomic_load_umin>;
334 def atomic_load_umax_local : local_binary_atomic_op<atomic_load_umax>;
336 def mskor_global : PatFrag<(ops node:$val, node:$ptr),
337 (AMDGPUstore_mskor node:$val, node:$ptr), [{
338 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
341 multiclass AtomicCmpSwapLocal <SDNode cmp_swap_node> {
343 def _32_local : PatFrag <
344 (ops node:$ptr, node:$cmp, node:$swap),
345 (cmp_swap_node node:$ptr, node:$cmp, node:$swap), [{
346 AtomicSDNode *AN = cast<AtomicSDNode>(N);
347 return AN->getMemoryVT() == MVT::i32 &&
348 AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
351 def _64_local : PatFrag<
352 (ops node:$ptr, node:$cmp, node:$swap),
353 (cmp_swap_node node:$ptr, node:$cmp, node:$swap), [{
354 AtomicSDNode *AN = cast<AtomicSDNode>(N);
355 return AN->getMemoryVT() == MVT::i64 &&
356 AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
360 defm atomic_cmp_swap : AtomicCmpSwapLocal <atomic_cmp_swap>;
362 def mskor_flat : PatFrag<(ops node:$val, node:$ptr),
363 (AMDGPUstore_mskor node:$val, node:$ptr), [{
364 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::FLAT_ADDRESS;
367 class global_binary_atomic_op<SDNode atomic_op> : PatFrag<
368 (ops node:$ptr, node:$value),
369 (atomic_op node:$ptr, node:$value),
370 [{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;}]
373 def atomic_swap_global : global_binary_atomic_op<atomic_swap>;
374 def atomic_add_global : global_binary_atomic_op<atomic_load_add>;
375 def atomic_and_global : global_binary_atomic_op<atomic_load_and>;
376 def atomic_max_global : global_binary_atomic_op<atomic_load_max>;
377 def atomic_min_global : global_binary_atomic_op<atomic_load_min>;
378 def atomic_or_global : global_binary_atomic_op<atomic_load_or>;
379 def atomic_sub_global : global_binary_atomic_op<atomic_load_sub>;
380 def atomic_umax_global : global_binary_atomic_op<atomic_load_umax>;
381 def atomic_umin_global : global_binary_atomic_op<atomic_load_umin>;
382 def atomic_xor_global : global_binary_atomic_op<atomic_load_xor>;
384 //===----------------------------------------------------------------------===//
385 // Misc Pattern Fragments
386 //===----------------------------------------------------------------------===//
389 int TWO_PI = 0x40c90fdb;
391 int TWO_PI_INV = 0x3e22f983;
392 int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
393 int FP32_NEG_ONE = 0xbf800000;
394 int FP32_ONE = 0x3f800000;
396 def CONST : Constants;
398 def FP_ZERO : PatLeaf <
400 [{return N->getValueAPF().isZero();}]
403 def FP_ONE : PatLeaf <
405 [{return N->isExactlyValue(1.0);}]
408 def FP_HALF : PatLeaf <
410 [{return N->isExactlyValue(0.5);}]
413 let isCodeGenOnly = 1, isPseudo = 1 in {
415 let usesCustomInserter = 1 in {
417 class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
421 [(set f32:$dst, (AMDGPUclamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
424 class FABS <RegisterClass rc> : AMDGPUShaderInst <
428 [(set f32:$dst, (fabs f32:$src0))]
431 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
435 [(set f32:$dst, (fneg f32:$src0))]
438 } // usesCustomInserter = 1
440 multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
441 ComplexPattern addrPat> {
442 let UseNamedOperandTable = 1 in {
444 def RegisterLoad : AMDGPUShaderInst <
445 (outs dstClass:$dst),
446 (ins addrClass:$addr, i32imm:$chan),
447 "RegisterLoad $dst, $addr",
448 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
450 let isRegisterLoad = 1;
453 def RegisterStore : AMDGPUShaderInst <
455 (ins dstClass:$val, addrClass:$addr, i32imm:$chan),
456 "RegisterStore $val, $addr",
457 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
459 let isRegisterStore = 1;
464 } // End isCodeGenOnly = 1, isPseudo = 1
466 /* Generic helper patterns for intrinsics */
467 /* -------------------------------------- */
469 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
471 (fpow f32:$src0, f32:$src1),
472 (exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
475 /* Other helper patterns */
476 /* --------------------- */
478 /* Extract element pattern */
479 class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
482 (sub_type (extractelt vec_type:$src, sub_idx)),
483 (EXTRACT_SUBREG $src, sub_reg)
486 /* Insert element pattern */
487 class Insert_Element <ValueType elem_type, ValueType vec_type,
488 int sub_idx, SubRegIndex sub_reg>
490 (insertelt vec_type:$vec, elem_type:$elem, sub_idx),
491 (INSERT_SUBREG $vec, $elem, sub_reg)
494 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
495 // can handle COPY instructions.
496 // bitconvert pattern
497 class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
498 (dt (bitconvert (st rc:$src0))),
502 // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
503 // can handle COPY instructions.
504 class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
505 (vt (AMDGPUdwordaddr (vt rc:$addr))),
511 multiclass BFIPatterns <Instruction BFI_INT,
512 Instruction LoadImm32,
513 RegisterClass RC64> {
514 // Definition from ISA doc:
515 // (y & x) | (z & ~x)
517 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
521 // SHA-256 Ch function
524 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
529 (fcopysign f32:$src0, f32:$src1),
530 (BFI_INT (LoadImm32 0x7fffffff), $src0, $src1)
534 (f64 (fcopysign f64:$src0, f64:$src1)),
536 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
537 (BFI_INT (LoadImm32 0x7fffffff),
538 (i32 (EXTRACT_SUBREG $src0, sub1)),
539 (i32 (EXTRACT_SUBREG $src1, sub1))), sub1)
543 // SHA-256 Ma patterns
545 // ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
546 class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
547 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
548 (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
551 // Bitfield extract patterns
553 def IMMZeroBasedBitfieldMask : PatLeaf <(imm), [{
554 return isMask_32(N->getZExtValue());
557 def IMMPopCount : SDNodeXForm<imm, [{
558 return CurDAG->getTargetConstant(countPopulation(N->getZExtValue()), SDLoc(N),
562 class BFEPattern <Instruction BFE, Instruction MOV> : Pat <
563 (i32 (and (i32 (srl i32:$src, i32:$rshift)), IMMZeroBasedBitfieldMask:$mask)),
564 (BFE $src, $rshift, (MOV (i32 (IMMPopCount $mask))))
568 class ROTRPattern <Instruction BIT_ALIGN> : Pat <
569 (rotr i32:$src0, i32:$src1),
570 (BIT_ALIGN $src0, $src0, $src1)
573 // 24-bit arithmetic patterns
574 def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
576 // Special conversion patterns
578 def cvt_rpi_i32_f32 : PatFrag <
580 (fp_to_sint (ffloor (fadd $src, FP_HALF))),
581 [{ (void) N; return TM.Options.NoNaNsFPMath; }]
584 def cvt_flr_i32_f32 : PatFrag <
586 (fp_to_sint (ffloor $src)),
587 [{ (void)N; return TM.Options.NoNaNsFPMath; }]
591 class UMUL24Pattern <Instruction UMUL24> : Pat <
592 (mul U24:$x, U24:$y),
597 class IMad24Pat<Instruction Inst> : Pat <
598 (add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2),
599 (Inst $src0, $src1, $src2)
602 class UMad24Pat<Instruction Inst> : Pat <
603 (add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2),
604 (Inst $src0, $src1, $src2)
607 multiclass Expand24IBitOps<Instruction MulInst, Instruction AddInst> {
608 def _expand_imad24 : Pat <
609 (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2),
610 (AddInst (MulInst $src0, $src1), $src2)
613 def _expand_imul24 : Pat <
614 (AMDGPUmul_i24 i32:$src0, i32:$src1),
615 (MulInst $src0, $src1)
619 multiclass Expand24UBitOps<Instruction MulInst, Instruction AddInst> {
620 def _expand_umad24 : Pat <
621 (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2),
622 (AddInst (MulInst $src0, $src1), $src2)
625 def _expand_umul24 : Pat <
626 (AMDGPUmul_u24 i32:$src0, i32:$src1),
627 (MulInst $src0, $src1)
631 class RcpPat<Instruction RcpInst, ValueType vt> : Pat <
632 (fdiv FP_ONE, vt:$src),
636 class RsqPat<Instruction RsqInst, ValueType vt> : Pat <
637 (AMDGPUrcp (fsqrt vt:$src)),
641 include "R600Instructions.td"
642 include "R700Instructions.td"
643 include "EvergreenInstructions.td"
644 include "CaymanInstructions.td"
646 include "SIInstrInfo.td"