1 //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Parent TargetRegisterInfo class common to all hw codegen targets.
13 //===----------------------------------------------------------------------===//
15 #include "AMDGPURegisterInfo.h"
16 #include "AMDGPUTargetMachine.h"
20 AMDGPURegisterInfo::AMDGPURegisterInfo() : AMDGPUGenRegisterInfo(0) {}
22 //===----------------------------------------------------------------------===//
23 // Function handling callbacks - Functions are a seldom used feature of GPUS, so
24 // they are not supported at this time.
25 //===----------------------------------------------------------------------===//
27 const MCPhysReg AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
30 AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
31 return &CalleeSavedReg;
34 void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
36 unsigned FIOperandNum,
37 RegScavenger *RS) const {
38 llvm_unreachable("Subroutines not supported yet");
41 unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {
42 return AMDGPU::NoRegister;
45 unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const {
46 static const unsigned SubRegs[] = {
47 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
48 AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
49 AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
53 assert(Channel < array_lengthof(SubRegs));
54 return SubRegs[Channel];
57 unsigned AMDGPURegisterInfo::getIndirectSubReg(unsigned IndirectIndex) const {
59 return getSubRegFromChannel(IndirectIndex);
62 #define GET_REGINFO_TARGET_DESC
63 #include "AMDGPUGenRegisterInfo.inc"