1 //===-- AMDGPUSubtarget.cpp - AMDGPU Subtarget Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Implements the AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #include "AMDGPUSubtarget.h"
16 #include "R600ISelLowering.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineScheduler.h"
19 #include "SIFrameLowering.h"
20 #include "SIISelLowering.h"
21 #include "SIInstrInfo.h"
22 #include "SIMachineFunctionInfo.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/CodeGen/MachineScheduler.h"
28 #define DEBUG_TYPE "amdgpu-subtarget"
30 #define GET_SUBTARGETINFO_ENUM
31 #define GET_SUBTARGETINFO_TARGET_DESC
32 #define GET_SUBTARGETINFO_CTOR
33 #include "AMDGPUGenSubtargetInfo.inc"
36 AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT,
37 StringRef GPU, StringRef FS) {
38 // Determine default and user-specified characteristics
39 // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
40 // enabled, but some instructions do not respect them and they run at the
41 // double precision rate, so don't enable by default.
43 // We want to be able to turn these off, but making this a subtarget feature
44 // for SI has the unhelpful behavior that it unsets everything else if you
47 SmallString<256> FullFS("+promote-alloca,+fp64-denormals,");
48 if (isAmdHsaOS()) // Turn on FlatForGlobal for HSA.
49 FullFS += "+flat-for-global,";
52 if (GPU == "" && TT.getArch() == Triple::amdgcn)
55 ParseSubtargetFeatures(GPU, FullFS);
57 // FIXME: I don't think think Evergreen has any useful support for
58 // denormals, but should be checked. Should we issue a warning somewhere
59 // if someone tries to enable these?
60 if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
61 FP32Denormals = false;
62 FP64Denormals = false;
67 AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
69 : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false),
70 DumpCode(false), R600ALUInst(false), HasVertexCache(false),
71 TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
72 FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
73 CaymanISA(false), FlatAddressSpace(false), FlatForGlobal(false),
74 EnableIRStructurizer(true), EnablePromoteAlloca(false), EnableIfCvt(true),
75 EnableLoadStoreOpt(false), EnableUnsafeDSOffsetFolding(false),
76 WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
77 EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false),
78 GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), LDSBankCount(0),
79 IsaVersion(ISAVersion0_0_0), EnableHugeScratchBuffer(false),
80 FrameLowering(nullptr),
81 InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) {
83 initializeSubtargetDependencies(TT, GPU, FS);
85 const unsigned MaxStackAlign = 64 * 16; // Maximum stack alignment (long16)
87 if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
88 InstrInfo.reset(new R600InstrInfo(*this));
89 TLInfo.reset(new R600TargetLowering(TM, *this));
91 // FIXME: Should have R600 specific FrameLowering
92 FrameLowering.reset(new AMDGPUFrameLowering(
93 TargetFrameLowering::StackGrowsUp,
97 InstrInfo.reset(new SIInstrInfo(*this));
98 TLInfo.reset(new SITargetLowering(TM, *this));
99 FrameLowering.reset(new SIFrameLowering(
100 TargetFrameLowering::StackGrowsUp,
106 unsigned AMDGPUSubtarget::getStackEntrySize() const {
107 assert(getGeneration() <= NORTHERN_ISLANDS);
108 switch(getWavefrontSize()) {
112 return hasCaymanISA() ? 4 : 8;
116 llvm_unreachable("Illegal wavefront size.");
120 unsigned AMDGPUSubtarget::getAmdKernelCodeChipID() const {
121 switch(getGeneration()) {
122 default: llvm_unreachable("ChipID unknown");
123 case SEA_ISLANDS: return 12;
127 AMDGPU::IsaVersion AMDGPUSubtarget::getIsaVersion() const {
128 return AMDGPU::getIsaVersion(getFeatureBits());
131 bool AMDGPUSubtarget::isVGPRSpillingEnabled(
132 const SIMachineFunctionInfo *MFI) const {
133 return MFI->getShaderType() == ShaderType::COMPUTE || EnableVGPRSpilling;
136 void AMDGPUSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
139 unsigned NumRegionInstrs) const {
140 if (getGeneration() >= SOUTHERN_ISLANDS) {
142 // Track register pressure so the scheduler can try to decrease
143 // pressure once register usage is above the threshold defined by
144 // SIRegisterInfo::getRegPressureSetLimit()
145 Policy.ShouldTrackPressure = true;
147 // Enabling both top down and bottom up scheduling seems to give us less
148 // register spills than just using one of these approaches on its own.
149 Policy.OnlyTopDown = false;
150 Policy.OnlyBottomUp = false;