1 //=====-- AMDGPUSubtarget.h - Define Subtarget for AMDGPU ------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
19 #include "AMDGPUFrameLowering.h"
20 #include "AMDGPUInstrInfo.h"
21 #include "AMDGPUISelLowering.h"
22 #include "AMDGPUSubtarget.h"
23 #include "Utils/AMDGPUBaseInfo.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "AMDGPUGenSubtargetInfo.inc"
32 class SIMachineFunctionInfo;
34 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
48 FIXED_SGPR_COUNT_FOR_INIT_BUG = 80
65 short TexVTXClauseSize;
72 bool FlatAddressSpace;
74 bool EnableIRStructurizer;
75 bool EnablePromoteAlloca;
77 bool EnableLoadStoreOpt;
78 bool EnableUnsafeDSOffsetFolding;
80 unsigned WavefrontSize;
83 bool EnableVGPRSpilling;
92 bool EnableHugeScratchBuffer;
93 bool EnableSIScheduler;
95 std::unique_ptr<AMDGPUFrameLowering> FrameLowering;
96 std::unique_ptr<AMDGPUTargetLowering> TLInfo;
97 std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
98 InstrItineraryData InstrItins;
102 AMDGPUSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
104 AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
105 StringRef GPU, StringRef FS);
107 const AMDGPUFrameLowering *getFrameLowering() const override {
108 return FrameLowering.get();
110 const AMDGPUInstrInfo *getInstrInfo() const override {
111 return InstrInfo.get();
113 const AMDGPURegisterInfo *getRegisterInfo() const override {
114 return &InstrInfo->getRegisterInfo();
116 AMDGPUTargetLowering *getTargetLowering() const override {
119 const InstrItineraryData *getInstrItineraryData() const override {
123 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
125 bool is64bit() const {
129 bool hasVertexCache() const {
130 return HasVertexCache;
133 short getTexVTXClauseSize() const {
134 return TexVTXClauseSize;
137 Generation getGeneration() const {
141 bool hasHWFP64() const {
145 bool hasCaymanISA() const {
149 bool hasFP32Denormals() const {
150 return FP32Denormals;
153 bool hasFP64Denormals() const {
154 return FP64Denormals;
157 bool hasFastFMAF32() const {
161 bool hasFlatAddressSpace() const {
162 return FlatAddressSpace;
165 bool useFlatForGlobal() const {
166 return FlatForGlobal;
169 bool hasBFE() const {
170 return (getGeneration() >= EVERGREEN);
173 bool hasBFI() const {
174 return (getGeneration() >= EVERGREEN);
177 bool hasBFM() const {
181 bool hasBCNT(unsigned Size) const {
183 return (getGeneration() >= EVERGREEN);
186 return (getGeneration() >= SOUTHERN_ISLANDS);
191 bool hasMulU24() const {
192 return (getGeneration() >= EVERGREEN);
195 bool hasMulI24() const {
196 return (getGeneration() >= SOUTHERN_ISLANDS ||
200 bool hasFFBL() const {
201 return (getGeneration() >= EVERGREEN);
204 bool hasFFBH() const {
205 return (getGeneration() >= EVERGREEN);
208 bool hasCARRY() const {
209 return (getGeneration() >= EVERGREEN);
212 bool hasBORROW() const {
213 return (getGeneration() >= EVERGREEN);
216 bool IsIRStructurizerEnabled() const {
217 return EnableIRStructurizer;
220 bool isPromoteAllocaEnabled() const {
221 return EnablePromoteAlloca;
224 bool isIfCvtEnabled() const {
228 bool loadStoreOptEnabled() const {
229 return EnableLoadStoreOpt;
232 bool unsafeDSOffsetFoldingEnabled() const {
233 return EnableUnsafeDSOffsetFolding;
236 unsigned getWavefrontSize() const {
237 return WavefrontSize;
240 unsigned getStackEntrySize() const;
242 bool hasCFAluBug() const {
243 assert(getGeneration() <= NORTHERN_ISLANDS);
247 int getLocalMemorySize() const {
248 return LocalMemorySize;
251 bool hasSGPRInitBug() const {
255 int getLDSBankCount() const {
259 unsigned getAmdKernelCodeChipID() const;
261 AMDGPU::IsaVersion getIsaVersion() const;
263 bool enableMachineScheduler() const override {
267 void overrideSchedPolicy(MachineSchedPolicy &Policy,
268 MachineInstr *begin, MachineInstr *end,
269 unsigned NumRegionInstrs) const override;
271 // Helper functions to simplify if statements
272 bool isTargetELF() const {
276 StringRef getDeviceName() const {
280 bool enableHugeScratchBuffer() const {
281 return EnableHugeScratchBuffer;
284 bool enableSIScheduler() const {
285 return EnableSIScheduler;
288 bool dumpCode() const {
291 bool r600ALUEncoding() const {
294 bool isAmdHsaOS() const {
295 return TargetTriple.getOS() == Triple::AMDHSA;
297 bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
299 bool isXNACKEnabled() const {
303 unsigned getMaxWavesPerCU() const {
304 if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
307 // FIXME: Not sure what this is for other subtagets.
308 llvm_unreachable("do not know max waves per CU for this subtarget.");
311 bool enableSubRegLiveness() const override {
315 /// \brief Returns the offset in bytes from the start of the input buffer
316 /// of the first explicit kernel argument.
317 unsigned getExplicitKernelArgOffset() const {
318 return isAmdHsaOS() ? 0 : 36;
321 unsigned getMaxNumUserSGPRs() const {
326 } // End namespace llvm