1 //=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUInstrInfo.h"
20 #include "AMDGPUIntrinsicInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600ISelLowering.h"
23 #include "AMDKernelCodeT.h"
24 #include "Utils/AMDGPUBaseInfo.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/Target/TargetSubtargetInfo.h"
29 #define GET_SUBTARGETINFO_HEADER
30 #include "AMDGPUGenSubtargetInfo.inc"
34 class SIMachineFunctionInfo;
36 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
50 FIXED_SGPR_COUNT_FOR_INIT_BUG = 80
67 short TexVTXClauseSize;
74 bool FlatAddressSpace;
75 bool EnableIRStructurizer;
76 bool EnablePromoteAlloca;
78 bool EnableLoadStoreOpt;
79 bool EnableUnsafeDSOffsetFolding;
80 unsigned WavefrontSize;
83 bool EnableVGPRSpilling;
92 bool EnableHugeScratchBuffer;
94 AMDGPUFrameLowering FrameLowering;
95 std::unique_ptr<AMDGPUTargetLowering> TLInfo;
96 std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
97 InstrItineraryData InstrItins;
101 AMDGPUSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
103 AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
104 StringRef GPU, StringRef FS);
106 const AMDGPUFrameLowering *getFrameLowering() const override {
107 return &FrameLowering;
109 const AMDGPUInstrInfo *getInstrInfo() const override {
110 return InstrInfo.get();
112 const AMDGPURegisterInfo *getRegisterInfo() const override {
113 return &InstrInfo->getRegisterInfo();
115 AMDGPUTargetLowering *getTargetLowering() const override {
118 const InstrItineraryData *getInstrItineraryData() const override {
122 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
124 bool is64bit() const {
128 bool hasVertexCache() const {
129 return HasVertexCache;
132 short getTexVTXClauseSize() const {
133 return TexVTXClauseSize;
136 Generation getGeneration() const {
140 bool hasHWFP64() const {
144 bool hasCaymanISA() const {
148 bool hasFP32Denormals() const {
149 return FP32Denormals;
152 bool hasFP64Denormals() const {
153 return FP64Denormals;
156 bool hasFastFMAF32() const {
160 bool hasFlatAddressSpace() const {
161 return FlatAddressSpace;
164 bool hasBFE() const {
165 return (getGeneration() >= EVERGREEN);
168 bool hasBFI() const {
169 return (getGeneration() >= EVERGREEN);
172 bool hasBFM() const {
176 bool hasBCNT(unsigned Size) const {
178 return (getGeneration() >= EVERGREEN);
181 return (getGeneration() >= SOUTHERN_ISLANDS);
186 bool hasMulU24() const {
187 return (getGeneration() >= EVERGREEN);
190 bool hasMulI24() const {
191 return (getGeneration() >= SOUTHERN_ISLANDS ||
195 bool hasFFBL() const {
196 return (getGeneration() >= EVERGREEN);
199 bool hasFFBH() const {
200 return (getGeneration() >= EVERGREEN);
203 bool hasCARRY() const {
204 return (getGeneration() >= EVERGREEN);
207 bool hasBORROW() const {
208 return (getGeneration() >= EVERGREEN);
211 bool IsIRStructurizerEnabled() const {
212 return EnableIRStructurizer;
215 bool isPromoteAllocaEnabled() const {
216 return EnablePromoteAlloca;
219 bool isIfCvtEnabled() const {
223 bool loadStoreOptEnabled() const {
224 return EnableLoadStoreOpt;
227 bool unsafeDSOffsetFoldingEnabled() const {
228 return EnableUnsafeDSOffsetFolding;
231 unsigned getWavefrontSize() const {
232 return WavefrontSize;
235 unsigned getStackEntrySize() const;
237 bool hasCFAluBug() const {
238 assert(getGeneration() <= NORTHERN_ISLANDS);
242 int getLocalMemorySize() const {
243 return LocalMemorySize;
246 bool hasSGPRInitBug() const {
250 int getLDSBankCount() const {
254 unsigned getAmdKernelCodeChipID() const;
256 AMDGPU::IsaVersion getIsaVersion() const;
258 bool enableMachineScheduler() const override {
262 void overrideSchedPolicy(MachineSchedPolicy &Policy,
263 MachineInstr *begin, MachineInstr *end,
264 unsigned NumRegionInstrs) const override;
266 // Helper functions to simplify if statements
267 bool isTargetELF() const {
271 StringRef getDeviceName() const {
275 bool enableHugeScratchBuffer() const {
276 return EnableHugeScratchBuffer;
279 bool dumpCode() const {
282 bool r600ALUEncoding() const {
285 bool isAmdHsaOS() const {
286 return TargetTriple.getOS() == Triple::AMDHSA;
288 bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
290 unsigned getMaxWavesPerCU() const {
291 if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
294 // FIXME: Not sure what this is for other subtagets.
295 llvm_unreachable("do not know max waves per CU for this subtarget.");
298 bool enableSubRegLiveness() const override {
302 /// \brief Returns the offset in bytes from the start of the input buffer
303 /// of the first explicit kernel argument.
304 unsigned getExplicitKernelArgOffset() const {
305 return isAmdHsaOS() ? 0 : 36;
310 } // End namespace llvm