1 //=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUInstrInfo.h"
20 #include "AMDGPUIntrinsicInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600ISelLowering.h"
23 #include "AMDKernelCodeT.h"
24 #include "Utils/AMDGPUBaseInfo.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/Target/TargetSubtargetInfo.h"
29 #define GET_SUBTARGETINFO_HEADER
30 #include "AMDGPUGenSubtargetInfo.inc"
34 class SIMachineFunctionInfo;
36 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
50 FIXED_SGPR_COUNT_FOR_INIT_BUG = 80
67 short TexVTXClauseSize;
74 bool FlatAddressSpace;
75 bool EnableIRStructurizer;
76 bool EnablePromoteAlloca;
78 bool EnableLoadStoreOpt;
79 bool EnableUnsafeDSOffsetFolding;
80 unsigned WavefrontSize;
83 bool EnableVGPRSpilling;
93 AMDGPUFrameLowering FrameLowering;
94 std::unique_ptr<AMDGPUTargetLowering> TLInfo;
95 std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
96 InstrItineraryData InstrItins;
100 AMDGPUSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
102 AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
103 StringRef GPU, StringRef FS);
105 const AMDGPUFrameLowering *getFrameLowering() const override {
106 return &FrameLowering;
108 const AMDGPUInstrInfo *getInstrInfo() const override {
109 return InstrInfo.get();
111 const AMDGPURegisterInfo *getRegisterInfo() const override {
112 return &InstrInfo->getRegisterInfo();
114 AMDGPUTargetLowering *getTargetLowering() const override {
117 const InstrItineraryData *getInstrItineraryData() const override {
121 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
123 bool is64bit() const {
127 bool hasVertexCache() const {
128 return HasVertexCache;
131 short getTexVTXClauseSize() const {
132 return TexVTXClauseSize;
135 Generation getGeneration() const {
139 bool hasHWFP64() const {
143 bool hasCaymanISA() const {
147 bool hasFP32Denormals() const {
148 return FP32Denormals;
151 bool hasFP64Denormals() const {
152 return FP64Denormals;
155 bool hasFastFMAF32() const {
159 bool hasFlatAddressSpace() const {
160 return FlatAddressSpace;
163 bool hasBFE() const {
164 return (getGeneration() >= EVERGREEN);
167 bool hasBFI() const {
168 return (getGeneration() >= EVERGREEN);
171 bool hasBFM() const {
175 bool hasBCNT(unsigned Size) const {
177 return (getGeneration() >= EVERGREEN);
180 return (getGeneration() >= SOUTHERN_ISLANDS);
185 bool hasMulU24() const {
186 return (getGeneration() >= EVERGREEN);
189 bool hasMulI24() const {
190 return (getGeneration() >= SOUTHERN_ISLANDS ||
194 bool hasFFBL() const {
195 return (getGeneration() >= EVERGREEN);
198 bool hasFFBH() const {
199 return (getGeneration() >= EVERGREEN);
202 bool hasCARRY() const {
203 return (getGeneration() >= EVERGREEN);
206 bool hasBORROW() const {
207 return (getGeneration() >= EVERGREEN);
210 bool IsIRStructurizerEnabled() const {
211 return EnableIRStructurizer;
214 bool isPromoteAllocaEnabled() const {
215 return EnablePromoteAlloca;
218 bool isIfCvtEnabled() const {
222 bool loadStoreOptEnabled() const {
223 return EnableLoadStoreOpt;
226 bool unsafeDSOffsetFoldingEnabled() const {
227 return EnableUnsafeDSOffsetFolding;
230 unsigned getWavefrontSize() const {
231 return WavefrontSize;
234 unsigned getStackEntrySize() const;
236 bool hasCFAluBug() const {
237 assert(getGeneration() <= NORTHERN_ISLANDS);
241 int getLocalMemorySize() const {
242 return LocalMemorySize;
245 bool hasSGPRInitBug() const {
249 int getLDSBankCount() const {
253 unsigned getAmdKernelCodeChipID() const;
255 AMDGPU::IsaVersion getIsaVersion() const;
257 bool enableMachineScheduler() const override {
261 void overrideSchedPolicy(MachineSchedPolicy &Policy,
262 MachineInstr *begin, MachineInstr *end,
263 unsigned NumRegionInstrs) const override;
265 // Helper functions to simplify if statements
266 bool isTargetELF() const {
270 StringRef getDeviceName() const {
274 bool dumpCode() const {
277 bool r600ALUEncoding() const {
280 bool isAmdHsaOS() const {
281 return TargetTriple.getOS() == Triple::AMDHSA;
283 bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
285 unsigned getMaxWavesPerCU() const {
286 if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
289 // FIXME: Not sure what this is for other subtagets.
290 llvm_unreachable("do not know max waves per CU for this subtarget.");
293 bool enableSubRegLiveness() const override {
297 /// \brief Returns the offset in bytes from the start of the input buffer
298 /// of the first explicit kernel argument.
299 unsigned getExplicitKernelArgOffset() const {
300 return isAmdHsaOS() ? 0 : 36;
305 } // End namespace llvm