1 //=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUInstrInfo.h"
20 #include "AMDGPUIntrinsicInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600ISelLowering.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "AMDGPUGenSubtargetInfo.inc"
32 class SIMachineFunctionInfo;
34 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
48 FIXED_SGPR_COUNT_FOR_INIT_BUG = 80
57 short TexVTXClauseSize;
64 bool FlatAddressSpace;
65 bool EnableIRStructurizer;
66 bool EnablePromoteAlloca;
68 bool EnableLoadStoreOpt;
69 unsigned WavefrontSize;
72 bool EnableVGPRSpilling;
81 AMDGPUFrameLowering FrameLowering;
82 std::unique_ptr<AMDGPUTargetLowering> TLInfo;
83 std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
84 InstrItineraryData InstrItins;
88 AMDGPUSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
90 AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
91 StringRef GPU, StringRef FS);
93 const AMDGPUFrameLowering *getFrameLowering() const override {
94 return &FrameLowering;
96 const AMDGPUInstrInfo *getInstrInfo() const override {
97 return InstrInfo.get();
99 const AMDGPURegisterInfo *getRegisterInfo() const override {
100 return &InstrInfo->getRegisterInfo();
102 AMDGPUTargetLowering *getTargetLowering() const override {
105 const InstrItineraryData *getInstrItineraryData() const override {
109 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
111 bool is64bit() const {
115 bool hasVertexCache() const {
116 return HasVertexCache;
119 short getTexVTXClauseSize() const {
120 return TexVTXClauseSize;
123 Generation getGeneration() const {
127 bool hasHWFP64() const {
131 bool hasCaymanISA() const {
135 bool hasFP32Denormals() const {
136 return FP32Denormals;
139 bool hasFP64Denormals() const {
140 return FP64Denormals;
143 bool hasFastFMAF32() const {
147 bool hasFlatAddressSpace() const {
148 return FlatAddressSpace;
151 bool hasBFE() const {
152 return (getGeneration() >= EVERGREEN);
155 bool hasBFI() const {
156 return (getGeneration() >= EVERGREEN);
159 bool hasBFM() const {
163 bool hasBCNT(unsigned Size) const {
165 return (getGeneration() >= EVERGREEN);
168 return (getGeneration() >= SOUTHERN_ISLANDS);
173 bool hasMulU24() const {
174 return (getGeneration() >= EVERGREEN);
177 bool hasMulI24() const {
178 return (getGeneration() >= SOUTHERN_ISLANDS ||
182 bool hasFFBL() const {
183 return (getGeneration() >= EVERGREEN);
186 bool hasFFBH() const {
187 return (getGeneration() >= EVERGREEN);
190 bool hasCARRY() const {
191 return (getGeneration() >= EVERGREEN);
194 bool hasBORROW() const {
195 return (getGeneration() >= EVERGREEN);
198 bool IsIRStructurizerEnabled() const {
199 return EnableIRStructurizer;
202 bool isPromoteAllocaEnabled() const {
203 return EnablePromoteAlloca;
206 bool isIfCvtEnabled() const {
210 bool loadStoreOptEnabled() const {
211 return EnableLoadStoreOpt;
214 unsigned getWavefrontSize() const {
215 return WavefrontSize;
218 unsigned getStackEntrySize() const;
220 bool hasCFAluBug() const {
221 assert(getGeneration() <= NORTHERN_ISLANDS);
225 int getLocalMemorySize() const {
226 return LocalMemorySize;
229 bool hasSGPRInitBug() const {
233 int getLDSBankCount() const {
237 unsigned getAmdKernelCodeChipID() const;
239 bool enableMachineScheduler() const override {
243 void overrideSchedPolicy(MachineSchedPolicy &Policy,
244 MachineInstr *begin, MachineInstr *end,
245 unsigned NumRegionInstrs) const override;
247 // Helper functions to simplify if statements
248 bool isTargetELF() const {
252 StringRef getDeviceName() const {
256 bool dumpCode() const {
259 bool r600ALUEncoding() const {
262 bool isAmdHsaOS() const {
263 return TargetTriple.getOS() == Triple::AMDHSA;
265 bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
267 unsigned getMaxWavesPerCU() const {
268 if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
271 // FIXME: Not sure what this is for other subtagets.
272 llvm_unreachable("do not know max waves per CU for this subtarget.");
275 bool enableSubRegLiveness() const override {
280 } // End namespace llvm