1 //=====-- AMDGPUSubtarget.h - Define Subtarget for AMDGPU ------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief AMDGPU specific subclass of TargetSubtarget.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
19 #include "AMDGPUFrameLowering.h"
20 #include "AMDGPUInstrInfo.h"
21 #include "AMDGPUISelLowering.h"
22 #include "AMDGPUSubtarget.h"
23 #include "Utils/AMDGPUBaseInfo.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "AMDGPUGenSubtargetInfo.inc"
32 class SIMachineFunctionInfo;
34 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
48 FIXED_SGPR_COUNT_FOR_INIT_BUG = 80
65 short TexVTXClauseSize;
72 bool FlatAddressSpace;
73 bool EnableIRStructurizer;
74 bool EnablePromoteAlloca;
76 bool EnableLoadStoreOpt;
77 bool EnableUnsafeDSOffsetFolding;
78 unsigned WavefrontSize;
81 bool EnableVGPRSpilling;
90 bool EnableHugeScratchBuffer;
92 std::unique_ptr<AMDGPUFrameLowering> FrameLowering;
93 std::unique_ptr<AMDGPUTargetLowering> TLInfo;
94 std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
95 InstrItineraryData InstrItins;
99 AMDGPUSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
101 AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
102 StringRef GPU, StringRef FS);
104 const AMDGPUFrameLowering *getFrameLowering() const override {
105 return FrameLowering.get();
107 const AMDGPUInstrInfo *getInstrInfo() const override {
108 return InstrInfo.get();
110 const AMDGPURegisterInfo *getRegisterInfo() const override {
111 return &InstrInfo->getRegisterInfo();
113 AMDGPUTargetLowering *getTargetLowering() const override {
116 const InstrItineraryData *getInstrItineraryData() const override {
120 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
122 bool is64bit() const {
126 bool hasVertexCache() const {
127 return HasVertexCache;
130 short getTexVTXClauseSize() const {
131 return TexVTXClauseSize;
134 Generation getGeneration() const {
138 bool hasHWFP64() const {
142 bool hasCaymanISA() const {
146 bool hasFP32Denormals() const {
147 return FP32Denormals;
150 bool hasFP64Denormals() const {
151 return FP64Denormals;
154 bool hasFastFMAF32() const {
158 bool hasFlatAddressSpace() const {
159 return FlatAddressSpace;
162 bool hasBFE() const {
163 return (getGeneration() >= EVERGREEN);
166 bool hasBFI() const {
167 return (getGeneration() >= EVERGREEN);
170 bool hasBFM() const {
174 bool hasBCNT(unsigned Size) const {
176 return (getGeneration() >= EVERGREEN);
179 return (getGeneration() >= SOUTHERN_ISLANDS);
184 bool hasMulU24() const {
185 return (getGeneration() >= EVERGREEN);
188 bool hasMulI24() const {
189 return (getGeneration() >= SOUTHERN_ISLANDS ||
193 bool hasFFBL() const {
194 return (getGeneration() >= EVERGREEN);
197 bool hasFFBH() const {
198 return (getGeneration() >= EVERGREEN);
201 bool hasCARRY() const {
202 return (getGeneration() >= EVERGREEN);
205 bool hasBORROW() const {
206 return (getGeneration() >= EVERGREEN);
209 bool IsIRStructurizerEnabled() const {
210 return EnableIRStructurizer;
213 bool isPromoteAllocaEnabled() const {
214 return EnablePromoteAlloca;
217 bool isIfCvtEnabled() const {
221 bool loadStoreOptEnabled() const {
222 return EnableLoadStoreOpt;
225 bool unsafeDSOffsetFoldingEnabled() const {
226 return EnableUnsafeDSOffsetFolding;
229 unsigned getWavefrontSize() const {
230 return WavefrontSize;
233 unsigned getStackEntrySize() const;
235 bool hasCFAluBug() const {
236 assert(getGeneration() <= NORTHERN_ISLANDS);
240 int getLocalMemorySize() const {
241 return LocalMemorySize;
244 bool hasSGPRInitBug() const {
248 int getLDSBankCount() const {
252 unsigned getAmdKernelCodeChipID() const;
254 AMDGPU::IsaVersion getIsaVersion() const;
256 bool enableMachineScheduler() const override {
260 void overrideSchedPolicy(MachineSchedPolicy &Policy,
261 MachineInstr *begin, MachineInstr *end,
262 unsigned NumRegionInstrs) const override;
264 // Helper functions to simplify if statements
265 bool isTargetELF() const {
269 StringRef getDeviceName() const {
273 bool enableHugeScratchBuffer() const {
274 return EnableHugeScratchBuffer;
277 bool dumpCode() const {
280 bool r600ALUEncoding() const {
283 bool isAmdHsaOS() const {
284 return TargetTriple.getOS() == Triple::AMDHSA;
286 bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
288 unsigned getMaxWavesPerCU() const {
289 if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
292 // FIXME: Not sure what this is for other subtagets.
293 llvm_unreachable("do not know max waves per CU for this subtarget.");
296 bool enableSubRegLiveness() const override {
300 /// \brief Returns the offset in bytes from the start of the input buffer
301 /// of the first explicit kernel argument.
302 unsigned getExplicitKernelArgOffset() const {
303 return isAmdHsaOS() ? 0 : 36;
308 } // End namespace llvm