1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information needed to emit code for R600 and SI GPUs.
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUTargetMachine.h"
18 #include "AMDGPUTargetTransformInfo.h"
19 #include "R600ISelLowering.h"
20 #include "R600InstrInfo.h"
21 #include "R600MachineScheduler.h"
22 #include "SIISelLowering.h"
23 #include "SIInstrInfo.h"
24 #include "llvm/Analysis/Passes.h"
25 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/IR/Verifier.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/IR/LegacyPassManager.h"
32 #include "llvm/Support/TargetRegistry.h"
33 #include "llvm/Support/raw_os_ostream.h"
34 #include "llvm/Transforms/IPO.h"
35 #include "llvm/Transforms/Scalar.h"
36 #include <llvm/CodeGen/Passes.h>
40 extern "C" void LLVMInitializeAMDGPUTarget() {
41 // Register the target
42 RegisterTargetMachine<R600TargetMachine> X(TheAMDGPUTarget);
43 RegisterTargetMachine<GCNTargetMachine> Y(TheGCNTarget);
46 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
47 return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());
50 static MachineSchedRegistry
51 SchedCustomRegistry("r600", "Run R600's custom scheduler",
52 createR600MachineScheduler);
54 static std::string computeDataLayout(const Triple &TT) {
55 std::string Ret = "e-p:32:32";
57 if (TT.getArch() == Triple::amdgcn) {
58 // 32-bit private, local, and region pointers. 64-bit global and constant.
59 Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64";
62 Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
63 "-v512:512-v1024:1024-v2048:2048-n32:64";
68 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
69 StringRef CPU, StringRef FS,
70 TargetOptions Options, Reloc::Model RM,
72 CodeGenOpt::Level OptLevel)
73 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
75 TLOF(new TargetLoweringObjectFileELF()), Subtarget(TT, CPU, FS, *this),
77 setRequiresStructuredCFG(true);
81 AMDGPUTargetMachine::~AMDGPUTargetMachine() {
85 //===----------------------------------------------------------------------===//
86 // R600 Target Machine (R600 -> Cayman)
87 //===----------------------------------------------------------------------===//
89 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
90 StringRef FS, StringRef CPU,
91 TargetOptions Options, Reloc::Model RM,
92 CodeModel::Model CM, CodeGenOpt::Level OL)
93 : AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {}
95 //===----------------------------------------------------------------------===//
96 // GCN Target Machine (SI+)
97 //===----------------------------------------------------------------------===//
99 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
100 StringRef FS, StringRef CPU,
101 TargetOptions Options, Reloc::Model RM,
102 CodeModel::Model CM, CodeGenOpt::Level OL)
103 : AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {}
105 //===----------------------------------------------------------------------===//
107 //===----------------------------------------------------------------------===//
110 class AMDGPUPassConfig : public TargetPassConfig {
112 AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM)
113 : TargetPassConfig(TM, PM) {}
115 AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
116 return getTM<AMDGPUTargetMachine>();
120 createMachineScheduler(MachineSchedContext *C) const override {
121 const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
122 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
123 return createR600MachineScheduler(C);
127 void addIRPasses() override;
128 void addCodeGenPrepare() override;
129 virtual bool addPreISel() override;
130 virtual bool addInstSelector() override;
133 class R600PassConfig : public AMDGPUPassConfig {
135 R600PassConfig(TargetMachine *TM, PassManagerBase &PM)
136 : AMDGPUPassConfig(TM, PM) { }
138 bool addPreISel() override;
139 void addPreRegAlloc() override;
140 void addPreSched2() override;
141 void addPreEmitPass() override;
144 class GCNPassConfig : public AMDGPUPassConfig {
146 GCNPassConfig(TargetMachine *TM, PassManagerBase &PM)
147 : AMDGPUPassConfig(TM, PM) { }
148 bool addPreISel() override;
149 bool addInstSelector() override;
150 void addPreRegAlloc() override;
151 void addPostRegAlloc() override;
152 void addPreSched2() override;
153 void addPreEmitPass() override;
156 } // End of anonymous namespace
158 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
159 return TargetIRAnalysis([this](Function &F) {
160 return TargetTransformInfo(
161 AMDGPUTTIImpl(this, F.getParent()->getDataLayout()));
165 void AMDGPUPassConfig::addIRPasses() {
166 // Function calls are not supported, so make sure we inline everything.
167 addPass(createAMDGPUAlwaysInlinePass());
168 addPass(createAlwaysInlinerPass());
169 // We need to add the barrier noop pass, otherwise adding the function
170 // inlining pass will cause all of the PassConfigs passes to be run
171 // one function at a time, which means if we have a nodule with two
172 // functions, then we will generate code for the first function
173 // without ever running any passes on the second.
174 addPass(createBarrierNoopPass());
175 // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
176 addPass(createAMDGPUOpenCLImageTypeLoweringPass());
177 TargetPassConfig::addIRPasses();
180 void AMDGPUPassConfig::addCodeGenPrepare() {
181 const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
182 if (ST.isPromoteAllocaEnabled()) {
183 addPass(createAMDGPUPromoteAlloca(ST));
184 addPass(createSROAPass());
186 TargetPassConfig::addCodeGenPrepare();
190 AMDGPUPassConfig::addPreISel() {
191 const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
192 addPass(createFlattenCFGPass());
193 if (ST.IsIRStructurizerEnabled())
194 addPass(createStructurizeCFGPass());
198 bool AMDGPUPassConfig::addInstSelector() {
199 addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
203 //===----------------------------------------------------------------------===//
205 //===----------------------------------------------------------------------===//
207 bool R600PassConfig::addPreISel() {
208 AMDGPUPassConfig::addPreISel();
209 addPass(createR600TextureIntrinsicsReplacer());
213 void R600PassConfig::addPreRegAlloc() {
214 addPass(createR600VectorRegMerger(*TM));
217 void R600PassConfig::addPreSched2() {
218 const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
219 addPass(createR600EmitClauseMarkers(), false);
220 if (ST.isIfCvtEnabled())
221 addPass(&IfConverterID, false);
222 addPass(createR600ClauseMergePass(*TM), false);
225 void R600PassConfig::addPreEmitPass() {
226 addPass(createAMDGPUCFGStructurizerPass(), false);
227 addPass(createR600ExpandSpecialInstrsPass(*TM), false);
228 addPass(&FinalizeMachineBundlesID, false);
229 addPass(createR600Packetizer(*TM), false);
230 addPass(createR600ControlFlowFinalizer(*TM), false);
233 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
234 return new R600PassConfig(this, PM);
237 //===----------------------------------------------------------------------===//
239 //===----------------------------------------------------------------------===//
241 bool GCNPassConfig::addPreISel() {
242 AMDGPUPassConfig::addPreISel();
243 addPass(createSinkingPass());
244 addPass(createSITypeRewriter());
245 addPass(createSIAnnotateControlFlowPass());
249 bool GCNPassConfig::addInstSelector() {
250 AMDGPUPassConfig::addInstSelector();
251 addPass(createSILowerI1CopiesPass());
252 addPass(createSIFixSGPRCopiesPass(*TM));
253 addPass(createSIFoldOperandsPass());
257 void GCNPassConfig::addPreRegAlloc() {
258 const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
260 // This needs to be run directly before register allocation because
261 // earlier passes might recompute live intervals.
262 // TODO: handle CodeGenOpt::None; fast RA ignores spill weights set by the pass
263 if (getOptLevel() > CodeGenOpt::None) {
264 initializeSIFixControlFlowLiveIntervalsPass(*PassRegistry::getPassRegistry());
265 insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);
268 if (getOptLevel() > CodeGenOpt::None && ST.loadStoreOptEnabled()) {
269 // Don't do this with no optimizations since it throws away debug info by
270 // merging nonadjacent loads.
272 // This should be run after scheduling, but before register allocation. It
273 // also need extra copies to the address operand to be eliminated.
274 initializeSILoadStoreOptimizerPass(*PassRegistry::getPassRegistry());
275 insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);
276 insertPass(&MachineSchedulerID, &RegisterCoalescerID);
278 addPass(createSIShrinkInstructionsPass(), false);
279 addPass(createSIFixSGPRLiveRangesPass(), false);
282 void GCNPassConfig::addPostRegAlloc() {
283 addPass(createSIPrepareScratchRegs(), false);
284 addPass(createSIShrinkInstructionsPass(), false);
287 void GCNPassConfig::addPreSched2() {
290 void GCNPassConfig::addPreEmitPass() {
291 addPass(createSIInsertWaits(*TM), false);
292 addPass(createSILowerControlFlowPass(*TM), false);
295 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
296 return new GCNPassConfig(this, PM);