1 //===-- AMDGPUTargetTransformInfo.cpp - AMDGPU specific TTI pass ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 // This file implements a TargetTransformInfo analysis pass specific to the
12 // AMDGPU target machine. It uses the target's detailed information to provide
13 // more precise answers to certain TTI queries, while letting the target
14 // independent and default TTI implementations handle the rest.
16 //===----------------------------------------------------------------------===//
18 #include "AMDGPUTargetTransformInfo.h"
19 #include "llvm/Analysis/LoopInfo.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/Analysis/ValueTracking.h"
22 #include "llvm/CodeGen/BasicTTIImpl.h"
23 #include "llvm/IR/Module.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Target/CostTable.h"
26 #include "llvm/Target/TargetLowering.h"
29 #define DEBUG_TYPE "AMDGPUtti"
31 void AMDGPUTTIImpl::getUnrollingPreferences(Loop *L,
32 TTI::UnrollingPreferences &UP) {
33 UP.Threshold = 300; // Twice the default.
34 UP.MaxCount = UINT_MAX;
37 // TODO: Do we want runtime unrolling?
39 for (const BasicBlock *BB : L->getBlocks()) {
40 const DataLayout &DL = BB->getModule()->getDataLayout();
41 for (const Instruction &I : *BB) {
42 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(&I);
43 if (!GEP || GEP->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS)
46 const Value *Ptr = GEP->getPointerOperand();
47 const AllocaInst *Alloca =
48 dyn_cast<AllocaInst>(GetUnderlyingObject(Ptr, DL));
50 // We want to do whatever we can to limit the number of alloca
51 // instructions that make it through to the code generator. allocas
52 // require us to use indirect addressing, which is slow and prone to
53 // compiler bugs. If this loop does an address calculation on an
54 // alloca ptr, then we want to use a higher than normal loop unroll
55 // threshold. This will give SROA a better chance to eliminate these
58 // Don't use the maximum allowed value here as it will make some
59 // programs way too big.
66 unsigned AMDGPUTTIImpl::getNumberOfRegisters(bool Vec) {
70 // Number of VGPRs on SI.
71 if (ST->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
74 return 4 * 128; // XXX - 4 channels. Should these count as vector instead?
77 unsigned AMDGPUTTIImpl::getRegisterBitWidth(bool) { return 32; }
79 unsigned AMDGPUTTIImpl::getMaxInterleaveFactor(unsigned VF) {
80 // Semi-arbitrary large amount.
84 unsigned AMDGPUTTIImpl::getCFInstrCost(unsigned Opcode) {
85 // XXX - For some reason this isn't called for switch.
88 case Instruction::Ret:
91 return BaseT::getCFInstrCost(Opcode);
95 int AMDGPUTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy,
98 case Instruction::ExtractElement:
99 // Dynamic indexing isn't free and is best avoided.
100 return Index == ~0u ? 2 : 0;
102 return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
106 static bool isIntrinsicSourceOfDivergence(const TargetIntrinsicInfo *TII,
107 const IntrinsicInst *I) {
108 switch (I->getIntrinsicID()) {
111 case Intrinsic::not_intrinsic:
112 // This means we have an intrinsic that isn't defined in
113 // IntrinsicsAMDGPU.td
116 case Intrinsic::amdgcn_interp_p1:
117 case Intrinsic::amdgcn_interp_p2:
118 case Intrinsic::amdgcn_mbcnt_hi:
119 case Intrinsic::amdgcn_mbcnt_lo:
120 case Intrinsic::r600_read_tidig_x:
121 case Intrinsic::r600_read_tidig_y:
122 case Intrinsic::r600_read_tidig_z:
126 StringRef Name = I->getCalledFunction()->getName();
127 switch (TII->lookupName((const char *)Name.bytes_begin(), Name.size())) {
130 case AMDGPUIntrinsic::SI_tid:
131 case AMDGPUIntrinsic::SI_fs_interp:
136 static bool isArgPassedInSGPR(const Argument *A) {
137 const Function *F = A->getParent();
138 unsigned ShaderType = AMDGPU::getShaderType(*F);
140 // Arguments to compute shaders are never a source of divergence.
141 if (ShaderType == ShaderType::COMPUTE)
144 // For non-compute shaders, SGPR inputs are marked with either inreg or byval.
145 if (F->getAttributes().hasAttribute(A->getArgNo() + 1, Attribute::InReg) ||
146 F->getAttributes().hasAttribute(A->getArgNo() + 1, Attribute::ByVal))
149 // Everything else is in VGPRs.
154 /// \returns true if the result of the value could potentially be
155 /// different across workitems in a wavefront.
156 bool AMDGPUTTIImpl::isSourceOfDivergence(const Value *V) const {
158 if (const Argument *A = dyn_cast<Argument>(V))
159 return !isArgPassedInSGPR(A);
161 // Loads from the private address space are divergent, because threads
162 // can execute the load instruction with the same inputs and get different
165 // All other loads are not divergent, because if threads issue loads with the
166 // same arguments, they will always get the same result.
167 if (const LoadInst *Load = dyn_cast<LoadInst>(V))
168 return Load->getPointerAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
170 if (const IntrinsicInst *Intrinsic = dyn_cast<IntrinsicInst>(V)) {
171 const TargetMachine &TM = getTLI()->getTargetMachine();
172 return isIntrinsicSourceOfDivergence(TM.getIntrinsicInfo(), Intrinsic);
175 // Assume all function calls are a source of divergence.
176 if (isa<CallInst>(V) || isa<InvokeInst>(V))