1 //===-- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
11 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
12 #include "Utils/AMDGPUBaseInfo.h"
13 #include "AMDKernelCodeT.h"
14 #include "SIDefines.h"
15 #include "llvm/ADT/APFloat.h"
16 #include "llvm/ADT/SmallString.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCParser/MCAsmLexer.h"
26 #include "llvm/MC/MCParser/MCAsmParser.h"
27 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/MC/MCStreamer.h"
30 #include "llvm/MC/MCSubtargetInfo.h"
31 #include "llvm/MC/MCSymbolELF.h"
32 #include "llvm/MC/MCTargetAsmParser.h"
33 #include "llvm/Support/ELF.h"
34 #include "llvm/Support/SourceMgr.h"
35 #include "llvm/Support/TargetRegistry.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Support/Debug.h"
43 struct OptionalOperand;
45 class AMDGPUOperand : public MCParsedAsmOperand {
53 SMLoc StartLoc, EndLoc;
56 AMDGPUOperand(enum KindTy K) : MCParsedAsmOperand(), Kind(K) {}
87 const MCRegisterInfo *TRI;
98 void addImmOperands(MCInst &Inst, unsigned N) const {
99 Inst.addOperand(MCOperand::createImm(getImm()));
102 StringRef getToken() const {
103 return StringRef(Tok.Data, Tok.Length);
106 void addRegOperands(MCInst &Inst, unsigned N) const {
107 Inst.addOperand(MCOperand::createReg(getReg()));
110 void addRegOrImmOperands(MCInst &Inst, unsigned N) const {
112 addRegOperands(Inst, N);
114 addImmOperands(Inst, N);
117 void addRegWithInputModsOperands(MCInst &Inst, unsigned N) const {
118 Inst.addOperand(MCOperand::createImm(
119 Reg.Modifiers == -1 ? 0 : Reg.Modifiers));
120 addRegOperands(Inst, N);
123 void addSoppBrTargetOperands(MCInst &Inst, unsigned N) const {
125 addImmOperands(Inst, N);
128 Inst.addOperand(MCOperand::createExpr(Expr));
132 bool defaultTokenHasSuffix() const {
133 StringRef Token(Tok.Data, Tok.Length);
135 return Token.endswith("_e32") || Token.endswith("_e64");
138 bool isToken() const override {
139 return Kind == Token;
142 bool isImm() const override {
143 return Kind == Immediate;
146 bool isInlineImm() const {
147 float F = BitsToFloat(Imm.Val);
148 // TODO: Add 0.5pi for VI
149 return isImm() && ((Imm.Val <= 64 && Imm.Val >= -16) ||
150 (F == 0.0 || F == 0.5 || F == -0.5 || F == 1.0 || F == -1.0 ||
151 F == 2.0 || F == -2.0 || F == 4.0 || F == -4.0));
154 bool isDSOffset0() const {
156 return Imm.Type == ImmTyDSOffset0;
159 bool isDSOffset1() const {
161 return Imm.Type == ImmTyDSOffset1;
164 int64_t getImm() const {
168 enum ImmTy getImmTy() const {
173 bool isRegKind() const {
174 return Kind == Register;
177 bool isReg() const override {
178 return Kind == Register && Reg.Modifiers == -1;
181 bool isRegWithInputMods() const {
182 return Kind == Register && (Reg.IsForcedVOP3 || Reg.Modifiers != -1);
185 void setModifiers(unsigned Mods) {
187 Reg.Modifiers = Mods;
190 bool hasModifiers() const {
192 return Reg.Modifiers != -1;
195 unsigned getReg() const override {
199 bool isRegOrImm() const {
200 return isReg() || isImm();
203 bool isRegClass(unsigned RCID) const {
204 return Reg.TRI->getRegClass(RCID).contains(getReg());
207 bool isSCSrc32() const {
208 return isInlineImm() || (isReg() && isRegClass(AMDGPU::SReg_32RegClassID));
211 bool isSSrc32() const {
212 return isImm() || (isReg() && isRegClass(AMDGPU::SReg_32RegClassID));
215 bool isSSrc64() const {
216 return isImm() || isInlineImm() ||
217 (isReg() && isRegClass(AMDGPU::SReg_64RegClassID));
220 bool isSCSrc64() const {
221 return (isReg() && isRegClass(AMDGPU::SReg_64RegClassID)) || isInlineImm();
224 bool isVCSrc32() const {
225 return isInlineImm() || (isReg() && isRegClass(AMDGPU::VS_32RegClassID));
228 bool isVCSrc64() const {
229 return isInlineImm() || (isReg() && isRegClass(AMDGPU::VS_64RegClassID));
232 bool isVSrc32() const {
233 return isImm() || (isReg() && isRegClass(AMDGPU::VS_32RegClassID));
236 bool isVSrc64() const {
237 return isImm() || (isReg() && isRegClass(AMDGPU::VS_64RegClassID));
240 bool isMem() const override {
244 bool isExpr() const {
245 return Kind == Expression;
248 bool isSoppBrTarget() const {
249 return isExpr() || isImm();
252 SMLoc getStartLoc() const override {
256 SMLoc getEndLoc() const override {
260 void print(raw_ostream &OS) const override {
263 OS << "<register " << getReg() << " mods: " << Reg.Modifiers << '>';
269 OS << '\'' << getToken() << '\'';
272 OS << "<expr " << *Expr << '>';
277 static std::unique_ptr<AMDGPUOperand> CreateImm(int64_t Val, SMLoc Loc,
278 enum ImmTy Type = ImmTyNone,
279 bool IsFPImm = false) {
280 auto Op = llvm::make_unique<AMDGPUOperand>(Immediate);
282 Op->Imm.IsFPImm = IsFPImm;
289 static std::unique_ptr<AMDGPUOperand> CreateToken(StringRef Str, SMLoc Loc,
290 bool HasExplicitEncodingSize = true) {
291 auto Res = llvm::make_unique<AMDGPUOperand>(Token);
292 Res->Tok.Data = Str.data();
293 Res->Tok.Length = Str.size();
299 static std::unique_ptr<AMDGPUOperand> CreateReg(unsigned RegNo, SMLoc S,
301 const MCRegisterInfo *TRI,
303 auto Op = llvm::make_unique<AMDGPUOperand>(Register);
304 Op->Reg.RegNo = RegNo;
306 Op->Reg.Modifiers = -1;
307 Op->Reg.IsForcedVOP3 = ForceVOP3;
313 static std::unique_ptr<AMDGPUOperand> CreateExpr(const class MCExpr *Expr, SMLoc S) {
314 auto Op = llvm::make_unique<AMDGPUOperand>(Expression);
321 bool isDSOffset() const;
322 bool isDSOffset01() const;
323 bool isSWaitCnt() const;
324 bool isMubufOffset() const;
325 bool isSMRDOffset() const;
326 bool isSMRDLiteralOffset() const;
329 class AMDGPUAsmParser : public MCTargetAsmParser {
330 const MCInstrInfo &MII;
333 unsigned ForcedEncodingSize;
336 return STI->getFeatureBits()[AMDGPU::FeatureSouthernIslands];
340 return STI->getFeatureBits()[AMDGPU::FeatureSeaIslands];
344 return getSTI().getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
347 bool hasSGPR102_SGPR103() const {
351 /// @name Auto-generated Match Functions
354 #define GET_ASSEMBLER_HEADER
355 #include "AMDGPUGenAsmMatcher.inc"
360 bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor);
361 bool ParseDirectiveHSACodeObjectVersion();
362 bool ParseDirectiveHSACodeObjectISA();
363 bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header);
364 bool ParseDirectiveAMDKernelCodeT();
365 bool ParseSectionDirectiveHSAText();
366 bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo) const;
367 bool ParseDirectiveAMDGPUHsaKernel();
368 bool ParseDirectiveAMDGPUHsaModuleGlobal();
369 bool ParseDirectiveAMDGPUHsaProgramGlobal();
370 bool ParseSectionDirectiveHSADataGlobalAgent();
371 bool ParseSectionDirectiveHSADataGlobalProgram();
375 enum AMDGPUMatchResultTy {
376 Match_PreferE32 = FIRST_TARGET_MATCH_RESULT_TY
379 AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,
380 const MCInstrInfo &MII,
381 const MCTargetOptions &Options)
382 : MCTargetAsmParser(Options, STI), MII(MII), Parser(_Parser),
383 ForcedEncodingSize(0) {
384 MCAsmParserExtension::Initialize(Parser);
386 if (getSTI().getFeatureBits().none()) {
387 // Set default features.
388 copySTI().ToggleFeature("SOUTHERN_ISLANDS");
391 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
394 AMDGPUTargetStreamer &getTargetStreamer() {
395 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
396 return static_cast<AMDGPUTargetStreamer &>(TS);
399 unsigned getForcedEncodingSize() const {
400 return ForcedEncodingSize;
403 void setForcedEncodingSize(unsigned Size) {
404 ForcedEncodingSize = Size;
407 bool isForcedVOP3() const {
408 return ForcedEncodingSize == 64;
411 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
412 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
413 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
414 OperandVector &Operands, MCStreamer &Out,
416 bool MatchingInlineAsm) override;
417 bool ParseDirective(AsmToken DirectiveID) override;
418 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic);
419 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
420 SMLoc NameLoc, OperandVector &Operands) override;
422 OperandMatchResultTy parseIntWithPrefix(const char *Prefix, int64_t &Int,
423 int64_t Default = 0);
424 OperandMatchResultTy parseIntWithPrefix(const char *Prefix,
425 OperandVector &Operands,
426 enum AMDGPUOperand::ImmTy ImmTy =
427 AMDGPUOperand::ImmTyNone);
428 OperandMatchResultTy parseNamedBit(const char *Name, OperandVector &Operands,
429 enum AMDGPUOperand::ImmTy ImmTy =
430 AMDGPUOperand::ImmTyNone);
431 OperandMatchResultTy parseOptionalOps(
432 const ArrayRef<OptionalOperand> &OptionalOps,
433 OperandVector &Operands);
436 void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
437 void cvtDS(MCInst &Inst, const OperandVector &Operands);
438 OperandMatchResultTy parseDSOptionalOps(OperandVector &Operands);
439 OperandMatchResultTy parseDSOff01OptionalOps(OperandVector &Operands);
440 OperandMatchResultTy parseDSOffsetOptional(OperandVector &Operands);
442 bool parseCnt(int64_t &IntVal);
443 OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
444 OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
446 OperandMatchResultTy parseFlatOptionalOps(OperandVector &Operands);
447 OperandMatchResultTy parseFlatAtomicOptionalOps(OperandVector &Operands);
448 void cvtFlat(MCInst &Inst, const OperandVector &Operands);
450 void cvtMubuf(MCInst &Inst, const OperandVector &Operands);
451 OperandMatchResultTy parseOffset(OperandVector &Operands);
452 OperandMatchResultTy parseMubufOptionalOps(OperandVector &Operands);
453 OperandMatchResultTy parseGLC(OperandVector &Operands);
454 OperandMatchResultTy parseSLC(OperandVector &Operands);
455 OperandMatchResultTy parseTFE(OperandVector &Operands);
457 OperandMatchResultTy parseDMask(OperandVector &Operands);
458 OperandMatchResultTy parseUNorm(OperandVector &Operands);
459 OperandMatchResultTy parseR128(OperandVector &Operands);
461 void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
462 OperandMatchResultTy parseVOP3OptionalOps(OperandVector &Operands);
465 struct OptionalOperand {
467 AMDGPUOperand::ImmTy Type;
470 bool (*ConvertResult)(int64_t&);
475 static int getRegClass(bool IsVgpr, unsigned RegWidth) {
479 case 1: return AMDGPU::VGPR_32RegClassID;
480 case 2: return AMDGPU::VReg_64RegClassID;
481 case 3: return AMDGPU::VReg_96RegClassID;
482 case 4: return AMDGPU::VReg_128RegClassID;
483 case 8: return AMDGPU::VReg_256RegClassID;
484 case 16: return AMDGPU::VReg_512RegClassID;
490 case 1: return AMDGPU::SGPR_32RegClassID;
491 case 2: return AMDGPU::SGPR_64RegClassID;
492 case 4: return AMDGPU::SReg_128RegClassID;
493 case 8: return AMDGPU::SReg_256RegClassID;
494 case 16: return AMDGPU::SReg_512RegClassID;
498 static unsigned getRegForName(StringRef RegName) {
500 return StringSwitch<unsigned>(RegName)
501 .Case("exec", AMDGPU::EXEC)
502 .Case("vcc", AMDGPU::VCC)
503 .Case("flat_scratch", AMDGPU::FLAT_SCR)
504 .Case("m0", AMDGPU::M0)
505 .Case("scc", AMDGPU::SCC)
506 .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
507 .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
508 .Case("vcc_lo", AMDGPU::VCC_LO)
509 .Case("vcc_hi", AMDGPU::VCC_HI)
510 .Case("exec_lo", AMDGPU::EXEC_LO)
511 .Case("exec_hi", AMDGPU::EXEC_HI)
515 bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
516 const AsmToken Tok = Parser.getTok();
517 StartLoc = Tok.getLoc();
518 EndLoc = Tok.getEndLoc();
519 const MCRegisterInfo *TRI = getContext().getRegisterInfo();
521 StringRef RegName = Tok.getString();
522 RegNo = getRegForName(RegName);
526 return !subtargetHasRegister(*TRI, RegNo);
529 // Match vgprs and sgprs
530 if (RegName[0] != 's' && RegName[0] != 'v')
533 bool IsVgpr = RegName[0] == 'v';
535 unsigned RegIndexInClass;
536 if (RegName.size() > 1) {
537 // We have a 32-bit register
539 if (RegName.substr(1).getAsInteger(10, RegIndexInClass))
543 // We have a register greater than 32-bits.
545 int64_t RegLo, RegHi;
547 if (getLexer().isNot(AsmToken::LBrac))
551 if (getParser().parseAbsoluteExpression(RegLo))
554 if (getLexer().isNot(AsmToken::Colon))
558 if (getParser().parseAbsoluteExpression(RegHi))
561 if (getLexer().isNot(AsmToken::RBrac))
565 RegWidth = (RegHi - RegLo) + 1;
567 // VGPR registers aren't aligned.
568 RegIndexInClass = RegLo;
570 // SGPR registers are aligned. Max alignment is 4 dwords.
571 unsigned Size = std::min(RegWidth, 4u);
572 if (RegLo % Size != 0)
575 RegIndexInClass = RegLo / Size;
579 int RCID = getRegClass(IsVgpr, RegWidth);
583 const MCRegisterClass RC = TRI->getRegClass(RCID);
584 if (RegIndexInClass >= RC.getNumRegs())
587 RegNo = RC.getRegister(RegIndexInClass);
588 return !subtargetHasRegister(*TRI, RegNo);
591 unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
593 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
595 if ((getForcedEncodingSize() == 32 && (TSFlags & SIInstrFlags::VOP3)) ||
596 (getForcedEncodingSize() == 64 && !(TSFlags & SIInstrFlags::VOP3)))
597 return Match_InvalidOperand;
599 if ((TSFlags & SIInstrFlags::VOP3) &&
600 (TSFlags & SIInstrFlags::VOPAsmPrefer32Bit) &&
601 getForcedEncodingSize() != 64)
602 return Match_PreferE32;
604 return Match_Success;
608 bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
609 OperandVector &Operands,
612 bool MatchingInlineAsm) {
615 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
619 Out.EmitInstruction(Inst, getSTI());
621 case Match_MissingFeature:
622 return Error(IDLoc, "instruction not supported on this GPU");
624 case Match_MnemonicFail:
625 return Error(IDLoc, "unrecognized instruction mnemonic");
627 case Match_InvalidOperand: {
628 SMLoc ErrorLoc = IDLoc;
629 if (ErrorInfo != ~0ULL) {
630 if (ErrorInfo >= Operands.size()) {
631 if (isForcedVOP3()) {
632 // If 64-bit encoding has been forced we can end up with no
633 // clamp or omod operands if none of the registers have modifiers,
634 // so we need to add these to the operand list.
635 AMDGPUOperand &LastOp =
636 ((AMDGPUOperand &)*Operands[Operands.size() - 1]);
637 if (LastOp.isRegKind() ||
639 LastOp.getImmTy() != AMDGPUOperand::ImmTyNone)) {
640 SMLoc S = Parser.getTok().getLoc();
641 Operands.push_back(AMDGPUOperand::CreateImm(0, S,
642 AMDGPUOperand::ImmTyClamp));
643 Operands.push_back(AMDGPUOperand::CreateImm(0, S,
644 AMDGPUOperand::ImmTyOMod));
645 bool Res = MatchAndEmitInstruction(IDLoc, Opcode, Operands,
653 return Error(IDLoc, "too few operands for instruction");
656 ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc();
657 if (ErrorLoc == SMLoc())
660 return Error(ErrorLoc, "invalid operand for instruction");
662 case Match_PreferE32:
663 return Error(IDLoc, "internal error: instruction without _e64 suffix "
664 "should be encoded as e32");
666 llvm_unreachable("Implement any new match types added!");
669 bool AMDGPUAsmParser::ParseDirectiveMajorMinor(uint32_t &Major,
671 if (getLexer().isNot(AsmToken::Integer))
672 return TokError("invalid major version");
674 Major = getLexer().getTok().getIntVal();
677 if (getLexer().isNot(AsmToken::Comma))
678 return TokError("minor version number required, comma expected");
681 if (getLexer().isNot(AsmToken::Integer))
682 return TokError("invalid minor version");
684 Minor = getLexer().getTok().getIntVal();
690 bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectVersion() {
695 if (ParseDirectiveMajorMinor(Major, Minor))
698 getTargetStreamer().EmitDirectiveHSACodeObjectVersion(Major, Minor);
702 bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {
707 StringRef VendorName;
710 // If this directive has no arguments, then use the ISA version for the
712 if (getLexer().is(AsmToken::EndOfStatement)) {
713 AMDGPU::IsaVersion Isa = AMDGPU::getIsaVersion(getSTI().getFeatureBits());
714 getTargetStreamer().EmitDirectiveHSACodeObjectISA(Isa.Major, Isa.Minor,
721 if (ParseDirectiveMajorMinor(Major, Minor))
724 if (getLexer().isNot(AsmToken::Comma))
725 return TokError("stepping version number required, comma expected");
728 if (getLexer().isNot(AsmToken::Integer))
729 return TokError("invalid stepping version");
731 Stepping = getLexer().getTok().getIntVal();
734 if (getLexer().isNot(AsmToken::Comma))
735 return TokError("vendor name required, comma expected");
738 if (getLexer().isNot(AsmToken::String))
739 return TokError("invalid vendor name");
741 VendorName = getLexer().getTok().getStringContents();
744 if (getLexer().isNot(AsmToken::Comma))
745 return TokError("arch name required, comma expected");
748 if (getLexer().isNot(AsmToken::String))
749 return TokError("invalid arch name");
751 ArchName = getLexer().getTok().getStringContents();
754 getTargetStreamer().EmitDirectiveHSACodeObjectISA(Major, Minor, Stepping,
755 VendorName, ArchName);
759 bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,
760 amd_kernel_code_t &Header) {
762 if (getLexer().isNot(AsmToken::Equal))
763 return TokError("expected '='");
766 if (getLexer().isNot(AsmToken::Integer))
767 return TokError("amd_kernel_code_t values must be integers");
769 uint64_t Value = getLexer().getTok().getIntVal();
772 if (ID == "kernel_code_version_major")
773 Header.amd_kernel_code_version_major = Value;
774 else if (ID == "kernel_code_version_minor")
775 Header.amd_kernel_code_version_minor = Value;
776 else if (ID == "machine_kind")
777 Header.amd_machine_kind = Value;
778 else if (ID == "machine_version_major")
779 Header.amd_machine_version_major = Value;
780 else if (ID == "machine_version_minor")
781 Header.amd_machine_version_minor = Value;
782 else if (ID == "machine_version_stepping")
783 Header.amd_machine_version_stepping = Value;
784 else if (ID == "kernel_code_entry_byte_offset")
785 Header.kernel_code_entry_byte_offset = Value;
786 else if (ID == "kernel_code_prefetch_byte_size")
787 Header.kernel_code_prefetch_byte_size = Value;
788 else if (ID == "max_scratch_backing_memory_byte_size")
789 Header.max_scratch_backing_memory_byte_size = Value;
790 else if (ID == "compute_pgm_rsrc1_vgprs")
791 Header.compute_pgm_resource_registers |= S_00B848_VGPRS(Value);
792 else if (ID == "compute_pgm_rsrc1_sgprs")
793 Header.compute_pgm_resource_registers |= S_00B848_SGPRS(Value);
794 else if (ID == "compute_pgm_rsrc1_priority")
795 Header.compute_pgm_resource_registers |= S_00B848_PRIORITY(Value);
796 else if (ID == "compute_pgm_rsrc1_float_mode")
797 Header.compute_pgm_resource_registers |= S_00B848_FLOAT_MODE(Value);
798 else if (ID == "compute_pgm_rsrc1_priv")
799 Header.compute_pgm_resource_registers |= S_00B848_PRIV(Value);
800 else if (ID == "compute_pgm_rsrc1_dx10_clamp")
801 Header.compute_pgm_resource_registers |= S_00B848_DX10_CLAMP(Value);
802 else if (ID == "compute_pgm_rsrc1_debug_mode")
803 Header.compute_pgm_resource_registers |= S_00B848_DEBUG_MODE(Value);
804 else if (ID == "compute_pgm_rsrc1_ieee_mode")
805 Header.compute_pgm_resource_registers |= S_00B848_IEEE_MODE(Value);
806 else if (ID == "compute_pgm_rsrc2_scratch_en")
807 Header.compute_pgm_resource_registers |= (S_00B84C_SCRATCH_EN(Value) << 32);
808 else if (ID == "compute_pgm_rsrc2_user_sgpr")
809 Header.compute_pgm_resource_registers |= (S_00B84C_USER_SGPR(Value) << 32);
810 else if (ID == "compute_pgm_rsrc2_tgid_x_en")
811 Header.compute_pgm_resource_registers |= (S_00B84C_TGID_X_EN(Value) << 32);
812 else if (ID == "compute_pgm_rsrc2_tgid_y_en")
813 Header.compute_pgm_resource_registers |= (S_00B84C_TGID_Y_EN(Value) << 32);
814 else if (ID == "compute_pgm_rsrc2_tgid_z_en")
815 Header.compute_pgm_resource_registers |= (S_00B84C_TGID_Z_EN(Value) << 32);
816 else if (ID == "compute_pgm_rsrc2_tg_size_en")
817 Header.compute_pgm_resource_registers |= (S_00B84C_TG_SIZE_EN(Value) << 32);
818 else if (ID == "compute_pgm_rsrc2_tidig_comp_cnt")
819 Header.compute_pgm_resource_registers |=
820 (S_00B84C_TIDIG_COMP_CNT(Value) << 32);
821 else if (ID == "compute_pgm_rsrc2_excp_en_msb")
822 Header.compute_pgm_resource_registers |=
823 (S_00B84C_EXCP_EN_MSB(Value) << 32);
824 else if (ID == "compute_pgm_rsrc2_lds_size")
825 Header.compute_pgm_resource_registers |= (S_00B84C_LDS_SIZE(Value) << 32);
826 else if (ID == "compute_pgm_rsrc2_excp_en")
827 Header.compute_pgm_resource_registers |= (S_00B84C_EXCP_EN(Value) << 32);
828 else if (ID == "compute_pgm_resource_registers")
829 Header.compute_pgm_resource_registers = Value;
830 else if (ID == "enable_sgpr_private_segment_buffer")
831 Header.code_properties |=
832 (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT);
833 else if (ID == "enable_sgpr_dispatch_ptr")
834 Header.code_properties |=
835 (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_SHIFT);
836 else if (ID == "enable_sgpr_queue_ptr")
837 Header.code_properties |=
838 (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_SHIFT);
839 else if (ID == "enable_sgpr_kernarg_segment_ptr")
840 Header.code_properties |=
841 (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT);
842 else if (ID == "enable_sgpr_dispatch_id")
843 Header.code_properties |=
844 (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID_SHIFT);
845 else if (ID == "enable_sgpr_flat_scratch_init")
846 Header.code_properties |=
847 (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT);
848 else if (ID == "enable_sgpr_private_segment_size")
849 Header.code_properties |=
850 (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT);
851 else if (ID == "enable_sgpr_grid_workgroup_count_x")
852 Header.code_properties |=
853 (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X_SHIFT);
854 else if (ID == "enable_sgpr_grid_workgroup_count_y")
855 Header.code_properties |=
856 (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y_SHIFT);
857 else if (ID == "enable_sgpr_grid_workgroup_count_z")
858 Header.code_properties |=
859 (Value << AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z_SHIFT);
860 else if (ID == "enable_ordered_append_gds")
861 Header.code_properties |=
862 (Value << AMD_CODE_PROPERTY_ENABLE_ORDERED_APPEND_GDS_SHIFT);
863 else if (ID == "private_element_size")
864 Header.code_properties |=
865 (Value << AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE_SHIFT);
866 else if (ID == "is_ptr64")
867 Header.code_properties |=
868 (Value << AMD_CODE_PROPERTY_IS_PTR64_SHIFT);
869 else if (ID == "is_dynamic_callstack")
870 Header.code_properties |=
871 (Value << AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK_SHIFT);
872 else if (ID == "is_debug_enabled")
873 Header.code_properties |=
874 (Value << AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED_SHIFT);
875 else if (ID == "is_xnack_enabled")
876 Header.code_properties |=
877 (Value << AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED_SHIFT);
878 else if (ID == "workitem_private_segment_byte_size")
879 Header.workitem_private_segment_byte_size = Value;
880 else if (ID == "workgroup_group_segment_byte_size")
881 Header.workgroup_group_segment_byte_size = Value;
882 else if (ID == "gds_segment_byte_size")
883 Header.gds_segment_byte_size = Value;
884 else if (ID == "kernarg_segment_byte_size")
885 Header.kernarg_segment_byte_size = Value;
886 else if (ID == "workgroup_fbarrier_count")
887 Header.workgroup_fbarrier_count = Value;
888 else if (ID == "wavefront_sgpr_count")
889 Header.wavefront_sgpr_count = Value;
890 else if (ID == "workitem_vgpr_count")
891 Header.workitem_vgpr_count = Value;
892 else if (ID == "reserved_vgpr_first")
893 Header.reserved_vgpr_first = Value;
894 else if (ID == "reserved_vgpr_count")
895 Header.reserved_vgpr_count = Value;
896 else if (ID == "reserved_sgpr_first")
897 Header.reserved_sgpr_first = Value;
898 else if (ID == "reserved_sgpr_count")
899 Header.reserved_sgpr_count = Value;
900 else if (ID == "debug_wavefront_private_segment_offset_sgpr")
901 Header.debug_wavefront_private_segment_offset_sgpr = Value;
902 else if (ID == "debug_private_segment_buffer_sgpr")
903 Header.debug_private_segment_buffer_sgpr = Value;
904 else if (ID == "kernarg_segment_alignment")
905 Header.kernarg_segment_alignment = Value;
906 else if (ID == "group_segment_alignment")
907 Header.group_segment_alignment = Value;
908 else if (ID == "private_segment_alignment")
909 Header.private_segment_alignment = Value;
910 else if (ID == "wavefront_size")
911 Header.wavefront_size = Value;
912 else if (ID == "call_convention")
913 Header.call_convention = Value;
914 else if (ID == "runtime_loader_kernel_symbol")
915 Header.runtime_loader_kernel_symbol = Value;
917 return TokError("amd_kernel_code_t value not recognized.");
922 bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() {
924 amd_kernel_code_t Header;
925 AMDGPU::initDefaultAMDKernelCodeT(Header, getSTI().getFeatureBits());
929 if (getLexer().isNot(AsmToken::EndOfStatement))
930 return TokError("amd_kernel_code_t values must begin on a new line");
932 // Lex EndOfStatement. This is in a while loop, because lexing a comment
933 // will set the current token to EndOfStatement.
934 while(getLexer().is(AsmToken::EndOfStatement))
937 if (getLexer().isNot(AsmToken::Identifier))
938 return TokError("expected value identifier or .end_amd_kernel_code_t");
940 StringRef ID = getLexer().getTok().getIdentifier();
943 if (ID == ".end_amd_kernel_code_t")
946 if (ParseAMDKernelCodeTValue(ID, Header))
950 getTargetStreamer().EmitAMDKernelCodeT(Header);
955 bool AMDGPUAsmParser::ParseSectionDirectiveHSAText() {
956 getParser().getStreamer().SwitchSection(
957 AMDGPU::getHSATextSection(getContext()));
961 bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() {
962 if (getLexer().isNot(AsmToken::Identifier))
963 return TokError("expected symbol name");
965 StringRef KernelName = Parser.getTok().getString();
967 getTargetStreamer().EmitAMDGPUSymbolType(KernelName,
968 ELF::STT_AMDGPU_HSA_KERNEL);
973 bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaModuleGlobal() {
974 if (getLexer().isNot(AsmToken::Identifier))
975 return TokError("expected symbol name");
977 StringRef GlobalName = Parser.getTok().getIdentifier();
979 getTargetStreamer().EmitAMDGPUHsaModuleScopeGlobal(GlobalName);
984 bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaProgramGlobal() {
985 if (getLexer().isNot(AsmToken::Identifier))
986 return TokError("expected symbol name");
988 StringRef GlobalName = Parser.getTok().getIdentifier();
990 getTargetStreamer().EmitAMDGPUHsaProgramScopeGlobal(GlobalName);
995 bool AMDGPUAsmParser::ParseSectionDirectiveHSADataGlobalAgent() {
996 getParser().getStreamer().SwitchSection(
997 AMDGPU::getHSADataGlobalAgentSection(getContext()));
1001 bool AMDGPUAsmParser::ParseSectionDirectiveHSADataGlobalProgram() {
1002 getParser().getStreamer().SwitchSection(
1003 AMDGPU::getHSADataGlobalProgramSection(getContext()));
1007 bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
1008 StringRef IDVal = DirectiveID.getString();
1010 if (IDVal == ".hsa_code_object_version")
1011 return ParseDirectiveHSACodeObjectVersion();
1013 if (IDVal == ".hsa_code_object_isa")
1014 return ParseDirectiveHSACodeObjectISA();
1016 if (IDVal == ".amd_kernel_code_t")
1017 return ParseDirectiveAMDKernelCodeT();
1019 if (IDVal == ".hsatext" || IDVal == ".text")
1020 return ParseSectionDirectiveHSAText();
1022 if (IDVal == ".amdgpu_hsa_kernel")
1023 return ParseDirectiveAMDGPUHsaKernel();
1025 if (IDVal == ".amdgpu_hsa_module_global")
1026 return ParseDirectiveAMDGPUHsaModuleGlobal();
1028 if (IDVal == ".amdgpu_hsa_program_global")
1029 return ParseDirectiveAMDGPUHsaProgramGlobal();
1031 if (IDVal == ".hsadata_global_agent")
1032 return ParseSectionDirectiveHSADataGlobalAgent();
1034 if (IDVal == ".hsadata_global_program")
1035 return ParseSectionDirectiveHSADataGlobalProgram();
1040 bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
1041 unsigned RegNo) const {
1048 case AMDGPU::FLAT_SCR:
1049 case AMDGPU::FLAT_SCR_LO:
1050 case AMDGPU::FLAT_SCR_HI:
1057 // VI only has 102 SGPRs, so make sure we aren't trying to use the 2 more that
1059 for (MCRegAliasIterator R(AMDGPU::SGPR102_SGPR103, &MRI, true);
1068 static bool operandsHaveModifiers(const OperandVector &Operands) {
1070 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
1071 const AMDGPUOperand &Op = ((AMDGPUOperand&)*Operands[i]);
1072 if (Op.isRegKind() && Op.hasModifiers())
1074 if (Op.isImm() && (Op.getImmTy() == AMDGPUOperand::ImmTyOMod ||
1075 Op.getImmTy() == AMDGPUOperand::ImmTyClamp))
1081 AMDGPUAsmParser::OperandMatchResultTy
1082 AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
1084 // Try to parse with a custom parser
1085 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1087 // If we successfully parsed the operand or if there as an error parsing,
1090 // If we are parsing after we reach EndOfStatement then this means we
1091 // are appending default values to the Operands list. This is only done
1092 // by custom parser, so we shouldn't continue on to the generic parsing.
1093 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail ||
1094 getLexer().is(AsmToken::EndOfStatement))
1097 bool Negate = false, Abs = false;
1098 if (getLexer().getKind()== AsmToken::Minus) {
1103 if (getLexer().getKind() == AsmToken::Pipe) {
1108 switch(getLexer().getKind()) {
1109 case AsmToken::Integer: {
1110 SMLoc S = Parser.getTok().getLoc();
1112 if (getParser().parseAbsoluteExpression(IntVal))
1113 return MatchOperand_ParseFail;
1114 if (!isInt<32>(IntVal) && !isUInt<32>(IntVal)) {
1115 Error(S, "invalid immediate: only 32-bit values are legal");
1116 return MatchOperand_ParseFail;
1121 Operands.push_back(AMDGPUOperand::CreateImm(IntVal, S));
1122 return MatchOperand_Success;
1124 case AsmToken::Real: {
1125 // FIXME: We should emit an error if a double precisions floating-point
1126 // value is used. I'm not sure the best way to detect this.
1127 SMLoc S = Parser.getTok().getLoc();
1129 if (getParser().parseAbsoluteExpression(IntVal))
1130 return MatchOperand_ParseFail;
1132 APFloat F((float)BitsToDouble(IntVal));
1136 AMDGPUOperand::CreateImm(F.bitcastToAPInt().getZExtValue(), S));
1137 return MatchOperand_Success;
1139 case AsmToken::Identifier: {
1142 if (!ParseRegister(RegNo, S, E)) {
1144 bool HasModifiers = operandsHaveModifiers(Operands);
1145 unsigned Modifiers = 0;
1151 if (getLexer().getKind() != AsmToken::Pipe)
1152 return MatchOperand_ParseFail;
1157 if (Modifiers && !HasModifiers) {
1158 // We are adding a modifier to src1 or src2 and previous sources
1159 // don't have modifiers, so we need to go back and empty modifers
1160 // for each previous source.
1161 for (unsigned PrevRegIdx = Operands.size() - 1; PrevRegIdx > 1;
1164 AMDGPUOperand &RegOp = ((AMDGPUOperand&)*Operands[PrevRegIdx]);
1165 RegOp.setModifiers(0);
1170 Operands.push_back(AMDGPUOperand::CreateReg(
1171 RegNo, S, E, getContext().getRegisterInfo(),
1174 if (HasModifiers || Modifiers) {
1175 AMDGPUOperand &RegOp = ((AMDGPUOperand&)*Operands[Operands.size() - 1]);
1176 RegOp.setModifiers(Modifiers);
1180 Operands.push_back(AMDGPUOperand::CreateToken(Parser.getTok().getString(),
1184 return MatchOperand_Success;
1187 return MatchOperand_NoMatch;
1191 bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1193 SMLoc NameLoc, OperandVector &Operands) {
1195 // Clear any forced encodings from the previous instruction.
1196 setForcedEncodingSize(0);
1198 if (Name.endswith("_e64"))
1199 setForcedEncodingSize(64);
1200 else if (Name.endswith("_e32"))
1201 setForcedEncodingSize(32);
1203 // Add the instruction mnemonic
1204 Operands.push_back(AMDGPUOperand::CreateToken(Name, NameLoc));
1206 while (!getLexer().is(AsmToken::EndOfStatement)) {
1207 AMDGPUAsmParser::OperandMatchResultTy Res = parseOperand(Operands, Name);
1209 // Eat the comma or space if there is one.
1210 if (getLexer().is(AsmToken::Comma))
1214 case MatchOperand_Success: break;
1215 case MatchOperand_ParseFail: return Error(getLexer().getLoc(),
1216 "failed parsing operand.");
1217 case MatchOperand_NoMatch: return Error(getLexer().getLoc(),
1218 "not a valid operand.");
1222 // Once we reach end of statement, continue parsing so we can add default
1223 // values for optional arguments.
1224 AMDGPUAsmParser::OperandMatchResultTy Res;
1225 while ((Res = parseOperand(Operands, Name)) != MatchOperand_NoMatch) {
1226 if (Res != MatchOperand_Success)
1227 return Error(getLexer().getLoc(), "failed parsing operand.");
1232 //===----------------------------------------------------------------------===//
1233 // Utility functions
1234 //===----------------------------------------------------------------------===//
1236 AMDGPUAsmParser::OperandMatchResultTy
1237 AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, int64_t &Int,
1240 // We are at the end of the statement, and this is a default argument, so
1241 // use a default value.
1242 if (getLexer().is(AsmToken::EndOfStatement)) {
1244 return MatchOperand_Success;
1247 switch(getLexer().getKind()) {
1248 default: return MatchOperand_NoMatch;
1249 case AsmToken::Identifier: {
1250 StringRef OffsetName = Parser.getTok().getString();
1251 if (!OffsetName.equals(Prefix))
1252 return MatchOperand_NoMatch;
1255 if (getLexer().isNot(AsmToken::Colon))
1256 return MatchOperand_ParseFail;
1259 if (getLexer().isNot(AsmToken::Integer))
1260 return MatchOperand_ParseFail;
1262 if (getParser().parseAbsoluteExpression(Int))
1263 return MatchOperand_ParseFail;
1267 return MatchOperand_Success;
1270 AMDGPUAsmParser::OperandMatchResultTy
1271 AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, OperandVector &Operands,
1272 enum AMDGPUOperand::ImmTy ImmTy) {
1274 SMLoc S = Parser.getTok().getLoc();
1277 AMDGPUAsmParser::OperandMatchResultTy Res = parseIntWithPrefix(Prefix, Offset);
1278 if (Res != MatchOperand_Success)
1281 Operands.push_back(AMDGPUOperand::CreateImm(Offset, S, ImmTy));
1282 return MatchOperand_Success;
1285 AMDGPUAsmParser::OperandMatchResultTy
1286 AMDGPUAsmParser::parseNamedBit(const char *Name, OperandVector &Operands,
1287 enum AMDGPUOperand::ImmTy ImmTy) {
1289 SMLoc S = Parser.getTok().getLoc();
1291 // We are at the end of the statement, and this is a default argument, so
1292 // use a default value.
1293 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1294 switch(getLexer().getKind()) {
1295 case AsmToken::Identifier: {
1296 StringRef Tok = Parser.getTok().getString();
1300 } else if (Tok.startswith("no") && Tok.endswith(Name)) {
1304 return MatchOperand_NoMatch;
1309 return MatchOperand_NoMatch;
1313 Operands.push_back(AMDGPUOperand::CreateImm(Bit, S, ImmTy));
1314 return MatchOperand_Success;
1317 static bool operandsHasOptionalOp(const OperandVector &Operands,
1318 const OptionalOperand &OOp) {
1319 for (unsigned i = 0; i < Operands.size(); i++) {
1320 const AMDGPUOperand &ParsedOp = ((const AMDGPUOperand &)*Operands[i]);
1321 if ((ParsedOp.isImm() && ParsedOp.getImmTy() == OOp.Type) ||
1322 (ParsedOp.isToken() && ParsedOp.getToken() == OOp.Name))
1329 AMDGPUAsmParser::OperandMatchResultTy
1330 AMDGPUAsmParser::parseOptionalOps(const ArrayRef<OptionalOperand> &OptionalOps,
1331 OperandVector &Operands) {
1332 SMLoc S = Parser.getTok().getLoc();
1333 for (const OptionalOperand &Op : OptionalOps) {
1334 if (operandsHasOptionalOp(Operands, Op))
1336 AMDGPUAsmParser::OperandMatchResultTy Res;
1339 Res = parseNamedBit(Op.Name, Operands, Op.Type);
1340 if (Res == MatchOperand_NoMatch)
1345 Res = parseIntWithPrefix(Op.Name, Value, Op.Default);
1347 if (Res == MatchOperand_NoMatch)
1350 if (Res != MatchOperand_Success)
1353 if (Op.ConvertResult && !Op.ConvertResult(Value)) {
1354 return MatchOperand_ParseFail;
1357 Operands.push_back(AMDGPUOperand::CreateImm(Value, S, Op.Type));
1358 return MatchOperand_Success;
1360 return MatchOperand_NoMatch;
1363 //===----------------------------------------------------------------------===//
1365 //===----------------------------------------------------------------------===//
1367 static const OptionalOperand DSOptionalOps [] = {
1368 {"offset", AMDGPUOperand::ImmTyOffset, false, 0, nullptr},
1369 {"gds", AMDGPUOperand::ImmTyGDS, true, 0, nullptr}
1372 static const OptionalOperand DSOptionalOpsOff01 [] = {
1373 {"offset0", AMDGPUOperand::ImmTyDSOffset0, false, 0, nullptr},
1374 {"offset1", AMDGPUOperand::ImmTyDSOffset1, false, 0, nullptr},
1375 {"gds", AMDGPUOperand::ImmTyGDS, true, 0, nullptr}
1378 AMDGPUAsmParser::OperandMatchResultTy
1379 AMDGPUAsmParser::parseDSOptionalOps(OperandVector &Operands) {
1380 return parseOptionalOps(DSOptionalOps, Operands);
1382 AMDGPUAsmParser::OperandMatchResultTy
1383 AMDGPUAsmParser::parseDSOff01OptionalOps(OperandVector &Operands) {
1384 return parseOptionalOps(DSOptionalOpsOff01, Operands);
1387 AMDGPUAsmParser::OperandMatchResultTy
1388 AMDGPUAsmParser::parseDSOffsetOptional(OperandVector &Operands) {
1389 SMLoc S = Parser.getTok().getLoc();
1390 AMDGPUAsmParser::OperandMatchResultTy Res =
1391 parseIntWithPrefix("offset", Operands, AMDGPUOperand::ImmTyOffset);
1392 if (Res == MatchOperand_NoMatch) {
1393 Operands.push_back(AMDGPUOperand::CreateImm(0, S,
1394 AMDGPUOperand::ImmTyOffset));
1395 Res = MatchOperand_Success;
1400 bool AMDGPUOperand::isDSOffset() const {
1401 return isImm() && isUInt<16>(getImm());
1404 bool AMDGPUOperand::isDSOffset01() const {
1405 return isImm() && isUInt<8>(getImm());
1408 void AMDGPUAsmParser::cvtDSOffset01(MCInst &Inst,
1409 const OperandVector &Operands) {
1411 std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx;
1413 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
1414 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
1416 // Add the register arguments
1418 Op.addRegOperands(Inst, 1);
1422 // Handle optional arguments
1423 OptionalIdx[Op.getImmTy()] = i;
1426 unsigned Offset0Idx = OptionalIdx[AMDGPUOperand::ImmTyDSOffset0];
1427 unsigned Offset1Idx = OptionalIdx[AMDGPUOperand::ImmTyDSOffset1];
1428 unsigned GDSIdx = OptionalIdx[AMDGPUOperand::ImmTyGDS];
1430 ((AMDGPUOperand &)*Operands[Offset0Idx]).addImmOperands(Inst, 1); // offset0
1431 ((AMDGPUOperand &)*Operands[Offset1Idx]).addImmOperands(Inst, 1); // offset1
1432 ((AMDGPUOperand &)*Operands[GDSIdx]).addImmOperands(Inst, 1); // gds
1433 Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0
1436 void AMDGPUAsmParser::cvtDS(MCInst &Inst, const OperandVector &Operands) {
1438 std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx;
1439 bool GDSOnly = false;
1441 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
1442 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
1444 // Add the register arguments
1446 Op.addRegOperands(Inst, 1);
1450 if (Op.isToken() && Op.getToken() == "gds") {
1455 // Handle optional arguments
1456 OptionalIdx[Op.getImmTy()] = i;
1459 unsigned OffsetIdx = OptionalIdx[AMDGPUOperand::ImmTyOffset];
1460 ((AMDGPUOperand &)*Operands[OffsetIdx]).addImmOperands(Inst, 1); // offset
1463 unsigned GDSIdx = OptionalIdx[AMDGPUOperand::ImmTyGDS];
1464 ((AMDGPUOperand &)*Operands[GDSIdx]).addImmOperands(Inst, 1); // gds
1466 Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0
1470 //===----------------------------------------------------------------------===//
1472 //===----------------------------------------------------------------------===//
1474 bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {
1475 StringRef CntName = Parser.getTok().getString();
1479 if (getLexer().isNot(AsmToken::LParen))
1483 if (getLexer().isNot(AsmToken::Integer))
1486 if (getParser().parseAbsoluteExpression(CntVal))
1489 if (getLexer().isNot(AsmToken::RParen))
1493 if (getLexer().is(AsmToken::Amp) || getLexer().is(AsmToken::Comma))
1499 if (CntName == "vmcnt") {
1502 } else if (CntName == "expcnt") {
1505 } else if (CntName == "lgkmcnt") {
1512 IntVal &= ~(CntMask << CntShift);
1513 IntVal |= (CntVal << CntShift);
1517 AMDGPUAsmParser::OperandMatchResultTy
1518 AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) {
1519 // Disable all counters by default.
1523 int64_t CntVal = 0x77f;
1524 SMLoc S = Parser.getTok().getLoc();
1526 switch(getLexer().getKind()) {
1527 default: return MatchOperand_ParseFail;
1528 case AsmToken::Integer:
1529 // The operand can be an integer value.
1530 if (getParser().parseAbsoluteExpression(CntVal))
1531 return MatchOperand_ParseFail;
1534 case AsmToken::Identifier:
1536 if (parseCnt(CntVal))
1537 return MatchOperand_ParseFail;
1538 } while(getLexer().isNot(AsmToken::EndOfStatement));
1541 Operands.push_back(AMDGPUOperand::CreateImm(CntVal, S));
1542 return MatchOperand_Success;
1545 bool AMDGPUOperand::isSWaitCnt() const {
1549 //===----------------------------------------------------------------------===//
1550 // sopp branch targets
1551 //===----------------------------------------------------------------------===//
1553 AMDGPUAsmParser::OperandMatchResultTy
1554 AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) {
1555 SMLoc S = Parser.getTok().getLoc();
1557 switch (getLexer().getKind()) {
1558 default: return MatchOperand_ParseFail;
1559 case AsmToken::Integer: {
1561 if (getParser().parseAbsoluteExpression(Imm))
1562 return MatchOperand_ParseFail;
1563 Operands.push_back(AMDGPUOperand::CreateImm(Imm, S));
1564 return MatchOperand_Success;
1567 case AsmToken::Identifier:
1568 Operands.push_back(AMDGPUOperand::CreateExpr(
1569 MCSymbolRefExpr::create(getContext().getOrCreateSymbol(
1570 Parser.getTok().getString()), getContext()), S));
1572 return MatchOperand_Success;
1576 //===----------------------------------------------------------------------===//
1578 //===----------------------------------------------------------------------===//
1580 static const OptionalOperand FlatOptionalOps [] = {
1581 {"glc", AMDGPUOperand::ImmTyGLC, true, 0, nullptr},
1582 {"slc", AMDGPUOperand::ImmTySLC, true, 0, nullptr},
1583 {"tfe", AMDGPUOperand::ImmTyTFE, true, 0, nullptr}
1586 static const OptionalOperand FlatAtomicOptionalOps [] = {
1587 {"slc", AMDGPUOperand::ImmTySLC, true, 0, nullptr},
1588 {"tfe", AMDGPUOperand::ImmTyTFE, true, 0, nullptr}
1591 AMDGPUAsmParser::OperandMatchResultTy
1592 AMDGPUAsmParser::parseFlatOptionalOps(OperandVector &Operands) {
1593 return parseOptionalOps(FlatOptionalOps, Operands);
1596 AMDGPUAsmParser::OperandMatchResultTy
1597 AMDGPUAsmParser::parseFlatAtomicOptionalOps(OperandVector &Operands) {
1598 return parseOptionalOps(FlatAtomicOptionalOps, Operands);
1601 void AMDGPUAsmParser::cvtFlat(MCInst &Inst,
1602 const OperandVector &Operands) {
1603 std::map<AMDGPUOperand::ImmTy, unsigned> OptionalIdx;
1605 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
1606 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
1608 // Add the register arguments
1610 Op.addRegOperands(Inst, 1);
1614 // Handle 'glc' token which is sometimes hard-coded into the
1615 // asm string. There are no MCInst operands for these.
1619 // Handle optional arguments
1620 OptionalIdx[Op.getImmTy()] = i;
1624 // flat atomic instructions don't have a glc argument.
1625 if (OptionalIdx.count(AMDGPUOperand::ImmTyGLC)) {
1626 unsigned GLCIdx = OptionalIdx[AMDGPUOperand::ImmTyGLC];
1627 ((AMDGPUOperand &)*Operands[GLCIdx]).addImmOperands(Inst, 1);
1630 unsigned SLCIdx = OptionalIdx[AMDGPUOperand::ImmTySLC];
1631 unsigned TFEIdx = OptionalIdx[AMDGPUOperand::ImmTyTFE];
1633 ((AMDGPUOperand &)*Operands[SLCIdx]).addImmOperands(Inst, 1);
1634 ((AMDGPUOperand &)*Operands[TFEIdx]).addImmOperands(Inst, 1);
1637 //===----------------------------------------------------------------------===//
1639 //===----------------------------------------------------------------------===//
1641 static const OptionalOperand MubufOptionalOps [] = {
1642 {"offset", AMDGPUOperand::ImmTyOffset, false, 0, nullptr},
1643 {"glc", AMDGPUOperand::ImmTyGLC, true, 0, nullptr},
1644 {"slc", AMDGPUOperand::ImmTySLC, true, 0, nullptr},
1645 {"tfe", AMDGPUOperand::ImmTyTFE, true, 0, nullptr}
1648 AMDGPUAsmParser::OperandMatchResultTy
1649 AMDGPUAsmParser::parseMubufOptionalOps(OperandVector &Operands) {
1650 return parseOptionalOps(MubufOptionalOps, Operands);
1653 AMDGPUAsmParser::OperandMatchResultTy
1654 AMDGPUAsmParser::parseOffset(OperandVector &Operands) {
1655 return parseIntWithPrefix("offset", Operands);
1658 AMDGPUAsmParser::OperandMatchResultTy
1659 AMDGPUAsmParser::parseGLC(OperandVector &Operands) {
1660 return parseNamedBit("glc", Operands);
1663 AMDGPUAsmParser::OperandMatchResultTy
1664 AMDGPUAsmParser::parseSLC(OperandVector &Operands) {
1665 return parseNamedBit("slc", Operands);
1668 AMDGPUAsmParser::OperandMatchResultTy
1669 AMDGPUAsmParser::parseTFE(OperandVector &Operands) {
1670 return parseNamedBit("tfe", Operands);
1673 bool AMDGPUOperand::isMubufOffset() const {
1674 return isImm() && isUInt<12>(getImm());
1677 void AMDGPUAsmParser::cvtMubuf(MCInst &Inst,
1678 const OperandVector &Operands) {
1679 std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx;
1681 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
1682 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
1684 // Add the register arguments
1686 Op.addRegOperands(Inst, 1);
1690 // Handle the case where soffset is an immediate
1691 if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) {
1692 Op.addImmOperands(Inst, 1);
1696 // Handle tokens like 'offen' which are sometimes hard-coded into the
1697 // asm string. There are no MCInst operands for these.
1703 // Handle optional arguments
1704 OptionalIdx[Op.getImmTy()] = i;
1707 assert(OptionalIdx.size() == 4);
1709 unsigned OffsetIdx = OptionalIdx[AMDGPUOperand::ImmTyOffset];
1710 unsigned GLCIdx = OptionalIdx[AMDGPUOperand::ImmTyGLC];
1711 unsigned SLCIdx = OptionalIdx[AMDGPUOperand::ImmTySLC];
1712 unsigned TFEIdx = OptionalIdx[AMDGPUOperand::ImmTyTFE];
1714 ((AMDGPUOperand &)*Operands[OffsetIdx]).addImmOperands(Inst, 1);
1715 ((AMDGPUOperand &)*Operands[GLCIdx]).addImmOperands(Inst, 1);
1716 ((AMDGPUOperand &)*Operands[SLCIdx]).addImmOperands(Inst, 1);
1717 ((AMDGPUOperand &)*Operands[TFEIdx]).addImmOperands(Inst, 1);
1720 //===----------------------------------------------------------------------===//
1722 //===----------------------------------------------------------------------===//
1724 AMDGPUAsmParser::OperandMatchResultTy
1725 AMDGPUAsmParser::parseDMask(OperandVector &Operands) {
1726 return parseIntWithPrefix("dmask", Operands);
1729 AMDGPUAsmParser::OperandMatchResultTy
1730 AMDGPUAsmParser::parseUNorm(OperandVector &Operands) {
1731 return parseNamedBit("unorm", Operands);
1734 AMDGPUAsmParser::OperandMatchResultTy
1735 AMDGPUAsmParser::parseR128(OperandVector &Operands) {
1736 return parseNamedBit("r128", Operands);
1739 //===----------------------------------------------------------------------===//
1741 //===----------------------------------------------------------------------===//
1743 bool AMDGPUOperand::isSMRDOffset() const {
1745 // FIXME: Support 20-bit offsets on VI. We need to to pass subtarget
1746 // information here.
1747 return isImm() && isUInt<8>(getImm());
1750 bool AMDGPUOperand::isSMRDLiteralOffset() const {
1751 // 32-bit literals are only supported on CI and we only want to use them
1752 // when the offset is > 8-bits.
1753 return isImm() && !isUInt<8>(getImm()) && isUInt<32>(getImm());
1756 //===----------------------------------------------------------------------===//
1758 //===----------------------------------------------------------------------===//
1760 static bool ConvertOmodMul(int64_t &Mul) {
1761 if (Mul != 1 && Mul != 2 && Mul != 4)
1768 static bool ConvertOmodDiv(int64_t &Div) {
1782 static const OptionalOperand VOP3OptionalOps [] = {
1783 {"clamp", AMDGPUOperand::ImmTyClamp, true, 0, nullptr},
1784 {"mul", AMDGPUOperand::ImmTyOMod, false, 1, ConvertOmodMul},
1785 {"div", AMDGPUOperand::ImmTyOMod, false, 1, ConvertOmodDiv},
1788 static bool isVOP3(OperandVector &Operands) {
1789 if (operandsHaveModifiers(Operands))
1792 AMDGPUOperand &DstOp = ((AMDGPUOperand&)*Operands[1]);
1794 if (DstOp.isReg() && DstOp.isRegClass(AMDGPU::SGPR_64RegClassID))
1797 if (Operands.size() >= 5)
1800 if (Operands.size() > 3) {
1801 AMDGPUOperand &Src1Op = ((AMDGPUOperand&)*Operands[3]);
1802 if (Src1Op.getReg() && (Src1Op.isRegClass(AMDGPU::SReg_32RegClassID) ||
1803 Src1Op.isRegClass(AMDGPU::SReg_64RegClassID)))
1809 AMDGPUAsmParser::OperandMatchResultTy
1810 AMDGPUAsmParser::parseVOP3OptionalOps(OperandVector &Operands) {
1812 // The value returned by this function may change after parsing
1813 // an operand so store the original value here.
1814 bool HasModifiers = operandsHaveModifiers(Operands);
1816 bool IsVOP3 = isVOP3(Operands);
1817 if (HasModifiers || IsVOP3 ||
1818 getLexer().isNot(AsmToken::EndOfStatement) ||
1819 getForcedEncodingSize() == 64) {
1821 AMDGPUAsmParser::OperandMatchResultTy Res =
1822 parseOptionalOps(VOP3OptionalOps, Operands);
1824 if (!HasModifiers && Res == MatchOperand_Success) {
1825 // We have added a modifier operation, so we need to make sure all
1826 // previous register operands have modifiers
1827 for (unsigned i = 2, e = Operands.size(); i != e; ++i) {
1828 AMDGPUOperand &Op = ((AMDGPUOperand&)*Operands[i]);
1835 return MatchOperand_NoMatch;
1838 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
1841 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
1842 if (Desc.getNumDefs() > 0) {
1843 ((AMDGPUOperand &)*Operands[i++]).addRegOperands(Inst, 1);
1846 std::map<enum AMDGPUOperand::ImmTy, unsigned> OptionalIdx;
1848 if (operandsHaveModifiers(Operands)) {
1849 for (unsigned e = Operands.size(); i != e; ++i) {
1850 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
1852 if (Op.isRegWithInputMods()) {
1853 ((AMDGPUOperand &)*Operands[i]).addRegWithInputModsOperands(Inst, 2);
1856 OptionalIdx[Op.getImmTy()] = i;
1859 unsigned ClampIdx = OptionalIdx[AMDGPUOperand::ImmTyClamp];
1860 unsigned OModIdx = OptionalIdx[AMDGPUOperand::ImmTyOMod];
1862 ((AMDGPUOperand &)*Operands[ClampIdx]).addImmOperands(Inst, 1);
1863 ((AMDGPUOperand &)*Operands[OModIdx]).addImmOperands(Inst, 1);
1865 for (unsigned e = Operands.size(); i != e; ++i)
1866 ((AMDGPUOperand &)*Operands[i]).addRegOrImmOperands(Inst, 1);
1870 /// Force static initialization.
1871 extern "C" void LLVMInitializeAMDGPUAsmParser() {
1872 RegisterMCAsmParser<AMDGPUAsmParser> A(TheAMDGPUTarget);
1873 RegisterMCAsmParser<AMDGPUAsmParser> B(TheGCNTarget);
1876 #define GET_REGISTER_MATCHER
1877 #define GET_MATCHER_IMPLEMENTATION
1878 #include "AMDGPUGenAsmMatcher.inc"