1 //===-- CIInstructions.td - CI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Instruction definitions for CI and newer.
10 //===----------------------------------------------------------------------===//
11 // Remaining instructions:
15 // S_CBRANCH_CDBGSYS_OR_USER
16 // S_CBRANCH_CDBGSYS_AND_USER
19 // DS_GWS_SEMA_RELEASE_ALL
21 // DS_CNDXCHG32_RTN_B64
24 // DS_CONDXCHG32_RTN_B128
27 // BUFFER_LOAD_DWORDX3
28 // BUFFER_STORE_DWORDX3
31 def isCIVI : Predicate <
32 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS || "
33 "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS"
34 >, AssemblerPredicate<"FeatureCIInsts">;
36 def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">;
38 //===----------------------------------------------------------------------===//
40 //===----------------------------------------------------------------------===//
42 let SubtargetPredicate = isCIVI in {
44 let SchedRW = [WriteDoubleAdd] in {
45 defm V_TRUNC_F64 : VOP1Inst <vop1<0x17>, "v_trunc_f64",
48 defm V_CEIL_F64 : VOP1Inst <vop1<0x18>, "v_ceil_f64",
51 defm V_FLOOR_F64 : VOP1Inst <vop1<0x1A>, "v_floor_f64",
54 defm V_RNDNE_F64 : VOP1Inst <vop1<0x19>, "v_rndne_f64",
57 } // End SchedRW = [WriteDoubleAdd]
59 let SchedRW = [WriteQuarterRate32] in {
60 defm V_LOG_LEGACY_F32 : VOP1Inst <vop1<0x45, 0x4c>, "v_log_legacy_f32",
63 defm V_EXP_LEGACY_F32 : VOP1Inst <vop1<0x46, 0x4b>, "v_exp_legacy_f32",
66 } // End SchedRW = [WriteQuarterRate32]
68 //===----------------------------------------------------------------------===//
70 //===----------------------------------------------------------------------===//
72 defm V_QSAD_PK_U16_U8 : VOP3Inst <vop3<0x173>, "v_qsad_pk_u16_u8",
75 defm V_MQSAD_U16_U8 : VOP3Inst <vop3<0x172>, "v_mqsad_u16_u8",
78 defm V_MQSAD_U32_U8 : VOP3Inst <vop3<0x175>, "v_mqsad_u32_u8",
82 let isCommutable = 1 in {
83 defm V_MAD_U64_U32 : VOP3Inst <vop3<0x176>, "v_mad_u64_u32",
87 // XXX - Does this set VCC?
88 defm V_MAD_I64_I32 : VOP3Inst <vop3<0x177>, "v_mad_i64_i32",
91 } // End isCommutable = 1
94 //===----------------------------------------------------------------------===//
96 //===----------------------------------------------------------------------===//
97 defm DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "ds_wrap_rtn_f32", VGPR_32, "ds_wrap_f32">;
99 // DS_CONDXCHG32_RTN_B64
100 // DS_CONDXCHG32_RTN_B128
102 //===----------------------------------------------------------------------===//
104 //===----------------------------------------------------------------------===//
106 def FLAT_LOAD_UBYTE : FLAT_Load_Helper <0x8, "flat_load_ubyte", VGPR_32>;
107 def FLAT_LOAD_SBYTE : FLAT_Load_Helper <0x9, "flat_load_sbyte", VGPR_32>;
108 def FLAT_LOAD_USHORT : FLAT_Load_Helper <0xa, "flat_load_ushort", VGPR_32>;
109 def FLAT_LOAD_SSHORT : FLAT_Load_Helper <0xb, "flat_load_sshort", VGPR_32>;
110 def FLAT_LOAD_DWORD : FLAT_Load_Helper <0xc, "flat_load_dword", VGPR_32>;
111 def FLAT_LOAD_DWORDX2 : FLAT_Load_Helper <0xd, "flat_load_dwordx2", VReg_64>;
112 def FLAT_LOAD_DWORDX4 : FLAT_Load_Helper <0xe, "flat_load_dwordx4", VReg_128>;
113 def FLAT_LOAD_DWORDX3 : FLAT_Load_Helper <0xf, "flat_load_dwordx3", VReg_96>;
114 def FLAT_STORE_BYTE : FLAT_Store_Helper <0x18, "flat_store_byte", VGPR_32>;
115 def FLAT_STORE_SHORT : FLAT_Store_Helper <0x1a, "flat_store_short", VGPR_32>;
116 def FLAT_STORE_DWORD : FLAT_Store_Helper <0x1c, "flat_store_dword", VGPR_32>;
117 def FLAT_STORE_DWORDX2 : FLAT_Store_Helper <
118 0x1d, "flat_store_dwordx2", VReg_64
120 def FLAT_STORE_DWORDX4 : FLAT_Store_Helper <
121 0x1e, "flat_store_dwordx4", VReg_128
123 def FLAT_STORE_DWORDX3 : FLAT_Store_Helper <
124 0x1f, "flat_store_dwordx3", VReg_96
126 defm FLAT_ATOMIC_SWAP : FLAT_ATOMIC <0x30, "flat_atomic_swap", VGPR_32>;
127 defm FLAT_ATOMIC_CMPSWAP : FLAT_ATOMIC <
128 0x31, "flat_atomic_cmpswap", VGPR_32, VReg_64
130 defm FLAT_ATOMIC_ADD : FLAT_ATOMIC <0x32, "flat_atomic_add", VGPR_32>;
131 defm FLAT_ATOMIC_SUB : FLAT_ATOMIC <0x33, "flat_atomic_sub", VGPR_32>;
132 defm FLAT_ATOMIC_RSUB : FLAT_ATOMIC <0x34, "flat_atomic_rsub", VGPR_32>;
133 defm FLAT_ATOMIC_SMIN : FLAT_ATOMIC <0x35, "flat_atomic_smin", VGPR_32>;
134 defm FLAT_ATOMIC_UMIN : FLAT_ATOMIC <0x36, "flat_atomic_umin", VGPR_32>;
135 defm FLAT_ATOMIC_SMAX : FLAT_ATOMIC <0x37, "flat_atomic_smax", VGPR_32>;
136 defm FLAT_ATOMIC_UMAX : FLAT_ATOMIC <0x38, "flat_atomic_umax", VGPR_32>;
137 defm FLAT_ATOMIC_AND : FLAT_ATOMIC <0x39, "flat_atomic_and", VGPR_32>;
138 defm FLAT_ATOMIC_OR : FLAT_ATOMIC <0x3a, "flat_atomic_or", VGPR_32>;
139 defm FLAT_ATOMIC_XOR : FLAT_ATOMIC <0x3b, "flat_atomic_xor", VGPR_32>;
140 defm FLAT_ATOMIC_INC : FLAT_ATOMIC <0x3c, "flat_atomic_inc", VGPR_32>;
141 defm FLAT_ATOMIC_DEC : FLAT_ATOMIC <0x3d, "flat_atomic_dec", VGPR_32>;
142 defm FLAT_ATOMIC_FCMPSWAP : FLAT_ATOMIC <
143 0x3e, "flat_atomic_fcmpswap", VGPR_32, VReg_64
145 defm FLAT_ATOMIC_FMIN : FLAT_ATOMIC <0x3f, "flat_atomic_fmin", VGPR_32>;
146 defm FLAT_ATOMIC_FMAX : FLAT_ATOMIC <0x40, "flat_atomic_fmax", VGPR_32>;
147 defm FLAT_ATOMIC_SWAP_X2 : FLAT_ATOMIC <0x50, "flat_atomic_swap_x2", VReg_64>;
148 defm FLAT_ATOMIC_CMPSWAP_X2 : FLAT_ATOMIC <
149 0x51, "flat_atomic_cmpswap_x2", VReg_64, VReg_128
151 defm FLAT_ATOMIC_ADD_X2 : FLAT_ATOMIC <0x52, "flat_atomic_add_x2", VReg_64>;
152 defm FLAT_ATOMIC_SUB_X2 : FLAT_ATOMIC <0x53, "flat_atomic_sub_x2", VReg_64>;
153 defm FLAT_ATOMIC_RSUB_X2 : FLAT_ATOMIC <0x54, "flat_atomic_rsub_x2", VReg_64>;
154 defm FLAT_ATOMIC_SMIN_X2 : FLAT_ATOMIC <0x55, "flat_atomic_smin_x2", VReg_64>;
155 defm FLAT_ATOMIC_UMIN_X2 : FLAT_ATOMIC <0x56, "flat_atomic_umin_x2", VReg_64>;
156 defm FLAT_ATOMIC_SMAX_X2 : FLAT_ATOMIC <0x57, "flat_atomic_smax_x2", VReg_64>;
157 defm FLAT_ATOMIC_UMAX_X2 : FLAT_ATOMIC <0x58, "flat_atomic_umax_x2", VReg_64>;
158 defm FLAT_ATOMIC_AND_X2 : FLAT_ATOMIC <0x59, "flat_atomic_and_x2", VReg_64>;
159 defm FLAT_ATOMIC_OR_X2 : FLAT_ATOMIC <0x5a, "flat_atomic_or_x2", VReg_64>;
160 defm FLAT_ATOMIC_XOR_X2 : FLAT_ATOMIC <0x5b, "flat_atomic_xor_x2", VReg_64>;
161 defm FLAT_ATOMIC_INC_X2 : FLAT_ATOMIC <0x5c, "flat_atomic_inc_x2", VReg_64>;
162 defm FLAT_ATOMIC_DEC_X2 : FLAT_ATOMIC <0x5d, "flat_atomic_dec_x2", VReg_64>;
163 defm FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_ATOMIC <
164 0x5e, "flat_atomic_fcmpswap_x2", VReg_64, VReg_128
166 defm FLAT_ATOMIC_FMIN_X2 : FLAT_ATOMIC <0x5f, "flat_atomic_fmin_x2", VReg_64>;
167 defm FLAT_ATOMIC_FMAX_X2 : FLAT_ATOMIC <0x60, "flat_atomic_fmax_x2", VReg_64>;
169 } // End SubtargetPredicate = isCIVI
171 //===----------------------------------------------------------------------===//
173 //===----------------------------------------------------------------------===//
175 let Predicates = [HasFlatAddressSpace] in {
177 class FLATLoad_Pattern <FLAT Instr_ADDR64, ValueType vt,
179 Pat <(vt (flat_ld i64:$ptr)),
180 (Instr_ADDR64 $ptr, 0, 0, 0)
183 def : FLATLoad_Pattern <FLAT_LOAD_SBYTE, i32, sextloadi8_flat>;
184 def : FLATLoad_Pattern <FLAT_LOAD_UBYTE, i32, az_extloadi8_flat>;
185 def : FLATLoad_Pattern <FLAT_LOAD_SSHORT, i32, sextloadi16_flat>;
186 def : FLATLoad_Pattern <FLAT_LOAD_USHORT, i32, az_extloadi16_flat>;
187 def : FLATLoad_Pattern <FLAT_LOAD_DWORD, i32, flat_load>;
188 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, i64, flat_load>;
189 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, i64, az_extloadi32_flat>;
190 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, v2i32, flat_load>;
191 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX4, v4i32, flat_load>;
193 class FLATStore_Pattern <FLAT Instr, ValueType vt, PatFrag st> :
194 Pat <(st vt:$value, i64:$ptr),
195 (Instr $value, $ptr, 0, 0, 0)
198 def : FLATStore_Pattern <FLAT_STORE_BYTE, i32, truncstorei8_flat>;
199 def : FLATStore_Pattern <FLAT_STORE_SHORT, i32, truncstorei16_flat>;
200 def : FLATStore_Pattern <FLAT_STORE_DWORD, i32, flat_store>;
201 def : FLATStore_Pattern <FLAT_STORE_DWORDX2, i64, flat_store>;
202 def : FLATStore_Pattern <FLAT_STORE_DWORDX2, v2i32, flat_store>;
203 def : FLATStore_Pattern <FLAT_STORE_DWORDX4, v4i32, flat_store>;
205 } // End HasFlatAddressSpace predicate
207 let Predicates = [isCI] in {
209 // Convert (x - floor(x)) to fract(x)
211 (f32 (fsub (f32 (VOP3Mods f32:$x, i32:$mods)),
212 (f32 (ffloor (f32 (VOP3Mods f32:$x, i32:$mods)))))),
213 (V_FRACT_F32_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
216 // Convert (x + (-floor(x))) to fract(x)
218 (f64 (fadd (f64 (VOP3Mods f64:$x, i32:$mods)),
219 (f64 (fneg (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))))))),
220 (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
223 } // End Predicates = [isCI]