1 set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
3 tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
4 tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
5 tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
6 tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
7 tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
8 tablegen(LLVM AMDGPUGenIntrinsics.inc -gen-tgt-intrinsic)
9 tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
10 tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer)
11 tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
12 tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
13 add_public_tablegen_target(AMDGPUCommonTableGen)
15 add_llvm_target(AMDGPUCodeGen
16 AMDILCFGStructurizer.cpp
17 AMDGPUAlwaysInlinePass.cpp
19 AMDGPUFrameLowering.cpp
20 AMDGPUHSATargetObjectFile.cpp
21 AMDGPUIntrinsicInfo.cpp
22 AMDGPUISelDAGToDAG.cpp
24 AMDGPUMachineFunction.cpp
25 AMDGPUOpenCLImageTypeLoweringPass.cpp
27 AMDGPUTargetMachine.cpp
28 AMDGPUTargetTransformInfo.cpp
29 AMDGPUISelLowering.cpp
31 AMDGPUPromoteAlloca.cpp
32 AMDGPURegisterInfo.cpp
33 R600ClauseMergePass.cpp
34 R600ControlFlowFinalizer.cpp
35 R600EmitClauseMarkers.cpp
36 R600ExpandSpecialInstrs.cpp
39 R600MachineFunctionInfo.cpp
40 R600MachineScheduler.cpp
41 R600OptimizeVectorRegisters.cpp
44 R600TextureIntrinsicsReplacer.cpp
45 SIAnnotateControlFlow.cpp
46 SIFixControlFlowLiveIntervals.cpp
48 SIFixSGPRLiveRanges.cpp
53 SILoadStoreOptimizer.cpp
54 SILowerControlFlow.cpp
56 SIMachineFunctionInfo.cpp
57 SIPrepareScratchRegs.cpp
59 SIShrinkInstructions.cpp
63 add_subdirectory(AsmParser)
64 add_subdirectory(InstPrinter)
65 add_subdirectory(TargetInfo)
66 add_subdirectory(MCTargetDesc)
67 add_subdirectory(Utils)