1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "AMDGPUInstPrinter.h"
12 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
13 #include "SIDefines.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCInstrInfo.h"
17 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/Support/MathExtras.h"
22 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
23 StringRef Annot, const MCSubtargetInfo &STI) {
25 printInstruction(MI, OS);
27 printAnnotation(OS, Annot);
30 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
32 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
35 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
37 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff);
40 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
42 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
45 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
47 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
50 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
52 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
55 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
57 if (MI->getOperand(OpNo).getImm())
61 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
63 if (MI->getOperand(OpNo).getImm())
67 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
69 if (MI->getOperand(OpNo).getImm())
73 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
75 if (MI->getOperand(OpNo).getImm()) {
77 printU16ImmDecOperand(MI, OpNo, O);
81 void AMDGPUInstPrinter::printDSOffset(const MCInst *MI, unsigned OpNo,
83 uint16_t Imm = MI->getOperand(OpNo).getImm();
86 printU16ImmDecOperand(MI, OpNo, O);
90 void AMDGPUInstPrinter::printDSOffset0(const MCInst *MI, unsigned OpNo,
92 if (MI->getOperand(OpNo).getImm()) {
94 printU8ImmDecOperand(MI, OpNo, O);
98 void AMDGPUInstPrinter::printDSOffset1(const MCInst *MI, unsigned OpNo,
100 if (MI->getOperand(OpNo).getImm()) {
102 printU8ImmDecOperand(MI, OpNo, O);
106 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
108 if (MI->getOperand(OpNo).getImm())
112 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
114 if (MI->getOperand(OpNo).getImm())
118 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
120 if (MI->getOperand(OpNo).getImm())
124 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
126 if (MI->getOperand(OpNo).getImm())
130 void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O,
131 const MCRegisterInfo &MRI) {
145 case AMDGPU::FLAT_SCR:
154 case AMDGPU::EXEC_LO:
157 case AMDGPU::EXEC_HI:
160 case AMDGPU::FLAT_SCR_LO:
161 O << "flat_scratch_lo";
163 case AMDGPU::FLAT_SCR_HI:
164 O << "flat_scratch_hi";
173 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) {
176 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) {
179 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) {
182 } else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) {
185 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) {
188 } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) {
191 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) {
194 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) {
197 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) {
200 } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) {
203 } else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(reg)) {
207 O << getRegisterName(reg);
211 // The low 8 bits of the encoding value is the register index, for both VGPRs
213 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1);
219 O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
222 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
224 if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3)
229 printOperand(MI, OpNo, O);
232 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, raw_ostream &O) {
233 int32_t SImm = static_cast<int32_t>(Imm);
234 if (SImm >= -16 && SImm <= 64) {
239 if (Imm == FloatToBits(0.0f))
241 else if (Imm == FloatToBits(1.0f))
243 else if (Imm == FloatToBits(-1.0f))
245 else if (Imm == FloatToBits(0.5f))
247 else if (Imm == FloatToBits(-0.5f))
249 else if (Imm == FloatToBits(2.0f))
251 else if (Imm == FloatToBits(-2.0f))
253 else if (Imm == FloatToBits(4.0f))
255 else if (Imm == FloatToBits(-4.0f))
258 O << formatHex(static_cast<uint64_t>(Imm));
261 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm, raw_ostream &O) {
262 int64_t SImm = static_cast<int64_t>(Imm);
263 if (SImm >= -16 && SImm <= 64) {
268 if (Imm == DoubleToBits(0.0))
270 else if (Imm == DoubleToBits(1.0))
272 else if (Imm == DoubleToBits(-1.0))
274 else if (Imm == DoubleToBits(0.5))
276 else if (Imm == DoubleToBits(-0.5))
278 else if (Imm == DoubleToBits(2.0))
280 else if (Imm == DoubleToBits(-2.0))
282 else if (Imm == DoubleToBits(4.0))
284 else if (Imm == DoubleToBits(-4.0))
287 llvm_unreachable("64-bit literal constants not supported");
290 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
293 const MCOperand &Op = MI->getOperand(OpNo);
295 switch (Op.getReg()) {
296 // This is the default predicate state, so we don't need to print it.
297 case AMDGPU::PRED_SEL_OFF:
301 printRegOperand(Op.getReg(), O, MRI);
304 } else if (Op.isImm()) {
305 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
306 int RCID = Desc.OpInfo[OpNo].RegClass;
308 const MCRegisterClass &ImmRC = MRI.getRegClass(RCID);
309 if (ImmRC.getSize() == 4)
310 printImmediate32(Op.getImm(), O);
311 else if (ImmRC.getSize() == 8)
312 printImmediate64(Op.getImm(), O);
314 llvm_unreachable("Invalid register class size");
315 } else if (Desc.OpInfo[OpNo].OperandType == MCOI::OPERAND_IMMEDIATE) {
316 printImmediate32(Op.getImm(), O);
318 // We hit this for the immediate instruction bits that don't yet have a
320 // TODO: Eventually this should be unnecessary.
321 O << formatDec(Op.getImm());
323 } else if (Op.isFPImm()) {
324 // We special case 0.0 because otherwise it will be printed as an integer.
325 if (Op.getFPImm() == 0.0)
328 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
329 const MCRegisterClass &ImmRC = MRI.getRegClass(Desc.OpInfo[OpNo].RegClass);
331 if (ImmRC.getSize() == 4)
332 printImmediate32(FloatToBits(Op.getFPImm()), O);
333 else if (ImmRC.getSize() == 8)
334 printImmediate64(DoubleToBits(Op.getFPImm()), O);
336 llvm_unreachable("Invalid register class size");
338 } else if (Op.isExpr()) {
339 const MCExpr *Exp = Op.getExpr();
342 llvm_unreachable("unknown operand type in printOperand");
346 void AMDGPUInstPrinter::printOperandAndMods(const MCInst *MI, unsigned OpNo,
348 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
349 if (InputModifiers & SISrcMods::NEG)
351 if (InputModifiers & SISrcMods::ABS)
353 printOperand(MI, OpNo + 1, O);
354 if (InputModifiers & SISrcMods::ABS)
358 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
360 unsigned Imm = MI->getOperand(OpNum).getImm();
364 } else if (Imm == 1) {
366 } else if (Imm == 0) {
369 llvm_unreachable("Invalid interpolation parameter slot");
373 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
375 printOperand(MI, OpNo, O);
377 printOperand(MI, OpNo + 1, O);
380 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
381 raw_ostream &O, StringRef Asm,
383 const MCOperand &Op = MI->getOperand(OpNo);
385 if (Op.getImm() == 1) {
392 void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
394 printIfSet(MI, OpNo, O, "|");
397 void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
399 printIfSet(MI, OpNo, O, "_SAT");
402 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
404 if (MI->getOperand(OpNo).getImm())
408 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
410 int Imm = MI->getOperand(OpNo).getImm();
411 if (Imm == SIOutMods::MUL2)
413 else if (Imm == SIOutMods::MUL4)
415 else if (Imm == SIOutMods::DIV2)
419 void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
421 int32_t Imm = MI->getOperand(OpNo).getImm();
422 O << Imm << '(' << BitsToFloat(Imm) << ')';
425 void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
427 printIfSet(MI, OpNo, O, "*", " ");
430 void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
432 printIfSet(MI, OpNo, O, "-");
435 void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
437 switch (MI->getOperand(OpNo).getImm()) {
451 void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
453 printIfSet(MI, OpNo, O, "+");
456 void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
458 printIfSet(MI, OpNo, O, "ExecMask,");
461 void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
463 printIfSet(MI, OpNo, O, "Pred,");
466 void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
468 const MCOperand &Op = MI->getOperand(OpNo);
469 if (Op.getImm() == 0) {
474 void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
476 const char * chans = "XYZW";
477 int sel = MI->getOperand(OpNo).getImm();
486 O << cb << '[' << sel << ']';
487 } else if (sel >= 448) {
490 } else if (sel >= 0){
495 O << '.' << chans[chan];
498 void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
500 int BankSwizzle = MI->getOperand(OpNo).getImm();
501 switch (BankSwizzle) {
503 O << "BS:VEC_021/SCL_122";
506 O << "BS:VEC_120/SCL_212";
509 O << "BS:VEC_102/SCL_221";
523 void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
525 unsigned Sel = MI->getOperand(OpNo).getImm();
553 void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo,
555 unsigned CT = MI->getOperand(OpNo).getImm();
568 void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
570 int KCacheMode = MI->getOperand(OpNo).getImm();
571 if (KCacheMode > 0) {
572 int KCacheBank = MI->getOperand(OpNo - 2).getImm();
573 O << "CB" << KCacheBank << ':';
574 int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
575 int LineSize = (KCacheMode == 1) ? 16 : 32;
576 O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize;
580 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
582 unsigned SImm16 = MI->getOperand(OpNo).getImm();
583 unsigned Msg = SImm16 & 0xF;
584 if (Msg == 2 || Msg == 3) {
585 unsigned Op = (SImm16 >> 4) & 0xF;
593 unsigned Stream = (SImm16 >> 8) & 0x3;
600 O << " stream " << Stream;
608 O << "unknown(" << Msg << ") ";
611 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
613 // Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
614 // SIInsertWaits.cpp bits usage does not match ISA docs description but it
615 // works so it might be a misprint in docs.
616 unsigned SImm16 = MI->getOperand(OpNo).getImm();
617 unsigned Vmcnt = SImm16 & 0xF;
618 unsigned Expcnt = (SImm16 >> 4) & 0xF;
619 unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
621 bool NeedSpace = false;
624 O << "vmcnt(" << Vmcnt << ')';
631 O << "expcnt(" << Expcnt << ')';
635 if (Lgkmcnt != 0x7) {
638 O << "lgkmcnt(" << Lgkmcnt << ')';
642 #include "AMDGPUGenAsmWriter.inc"