1 //===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 #include "AMDGPUInstPrinter.h"
12 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
13 #include "SIDefines.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCInstrInfo.h"
17 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/Support/MathExtras.h"
19 #include "llvm/Support/raw_ostream.h"
23 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
24 StringRef Annot, const MCSubtargetInfo &STI) {
26 printInstruction(MI, OS);
28 printAnnotation(OS, Annot);
31 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
33 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff);
36 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
38 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff);
41 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
43 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff);
46 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo,
48 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff);
51 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
53 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
56 void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
58 if (MI->getOperand(OpNo).getImm())
62 void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
64 if (MI->getOperand(OpNo).getImm())
68 void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
70 if (MI->getOperand(OpNo).getImm())
74 void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
76 if (MI->getOperand(OpNo).getImm()) {
78 printU16ImmDecOperand(MI, OpNo, O);
82 void AMDGPUInstPrinter::printDSOffset(const MCInst *MI, unsigned OpNo,
84 uint16_t Imm = MI->getOperand(OpNo).getImm();
87 printU16ImmDecOperand(MI, OpNo, O);
91 void AMDGPUInstPrinter::printDSOffset0(const MCInst *MI, unsigned OpNo,
93 if (MI->getOperand(OpNo).getImm()) {
95 printU8ImmDecOperand(MI, OpNo, O);
99 void AMDGPUInstPrinter::printDSOffset1(const MCInst *MI, unsigned OpNo,
101 if (MI->getOperand(OpNo).getImm()) {
103 printU8ImmDecOperand(MI, OpNo, O);
107 void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
109 if (MI->getOperand(OpNo).getImm())
113 void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
115 if (MI->getOperand(OpNo).getImm())
119 void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
121 if (MI->getOperand(OpNo).getImm())
125 void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
127 if (MI->getOperand(OpNo).getImm())
131 void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O,
132 const MCRegisterInfo &MRI) {
146 case AMDGPU::FLAT_SCR:
155 case AMDGPU::EXEC_LO:
158 case AMDGPU::EXEC_HI:
161 case AMDGPU::FLAT_SCR_LO:
162 O << "flat_scratch_lo";
164 case AMDGPU::FLAT_SCR_HI:
165 O << "flat_scratch_hi";
174 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) {
177 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) {
180 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) {
183 } else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) {
186 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) {
189 } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) {
192 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) {
195 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) {
198 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) {
201 } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) {
204 } else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(reg)) {
208 O << getRegisterName(reg);
212 // The low 8 bits of the encoding value is the register index, for both VGPRs
214 unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1);
220 O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
223 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
225 if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3)
230 printOperand(MI, OpNo, O);
233 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, raw_ostream &O) {
234 int32_t SImm = static_cast<int32_t>(Imm);
235 if (SImm >= -16 && SImm <= 64) {
240 if (Imm == FloatToBits(0.0f))
242 else if (Imm == FloatToBits(1.0f))
244 else if (Imm == FloatToBits(-1.0f))
246 else if (Imm == FloatToBits(0.5f))
248 else if (Imm == FloatToBits(-0.5f))
250 else if (Imm == FloatToBits(2.0f))
252 else if (Imm == FloatToBits(-2.0f))
254 else if (Imm == FloatToBits(4.0f))
256 else if (Imm == FloatToBits(-4.0f))
259 O << formatHex(static_cast<uint64_t>(Imm));
262 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm, raw_ostream &O) {
263 int64_t SImm = static_cast<int64_t>(Imm);
264 if (SImm >= -16 && SImm <= 64) {
269 if (Imm == DoubleToBits(0.0))
271 else if (Imm == DoubleToBits(1.0))
273 else if (Imm == DoubleToBits(-1.0))
275 else if (Imm == DoubleToBits(0.5))
277 else if (Imm == DoubleToBits(-0.5))
279 else if (Imm == DoubleToBits(2.0))
281 else if (Imm == DoubleToBits(-2.0))
283 else if (Imm == DoubleToBits(4.0))
285 else if (Imm == DoubleToBits(-4.0))
288 assert(isUInt<32>(Imm));
290 // In rare situations, we will have a 32-bit literal in a 64-bit
291 // operand. This is technically allowed for the encoding of s_mov_b64.
292 O << formatHex(static_cast<uint64_t>(Imm));
296 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
299 const MCOperand &Op = MI->getOperand(OpNo);
301 switch (Op.getReg()) {
302 // This is the default predicate state, so we don't need to print it.
303 case AMDGPU::PRED_SEL_OFF:
307 printRegOperand(Op.getReg(), O, MRI);
310 } else if (Op.isImm()) {
311 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
312 int RCID = Desc.OpInfo[OpNo].RegClass;
314 const MCRegisterClass &ImmRC = MRI.getRegClass(RCID);
315 if (ImmRC.getSize() == 4)
316 printImmediate32(Op.getImm(), O);
317 else if (ImmRC.getSize() == 8)
318 printImmediate64(Op.getImm(), O);
320 llvm_unreachable("Invalid register class size");
321 } else if (Desc.OpInfo[OpNo].OperandType == MCOI::OPERAND_IMMEDIATE) {
322 printImmediate32(Op.getImm(), O);
324 // We hit this for the immediate instruction bits that don't yet have a
326 // TODO: Eventually this should be unnecessary.
327 O << formatDec(Op.getImm());
329 } else if (Op.isFPImm()) {
330 // We special case 0.0 because otherwise it will be printed as an integer.
331 if (Op.getFPImm() == 0.0)
334 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
335 const MCRegisterClass &ImmRC = MRI.getRegClass(Desc.OpInfo[OpNo].RegClass);
337 if (ImmRC.getSize() == 4)
338 printImmediate32(FloatToBits(Op.getFPImm()), O);
339 else if (ImmRC.getSize() == 8)
340 printImmediate64(DoubleToBits(Op.getFPImm()), O);
342 llvm_unreachable("Invalid register class size");
344 } else if (Op.isExpr()) {
345 const MCExpr *Exp = Op.getExpr();
348 llvm_unreachable("unknown operand type in printOperand");
352 void AMDGPUInstPrinter::printOperandAndMods(const MCInst *MI, unsigned OpNo,
354 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
355 if (InputModifiers & SISrcMods::NEG)
357 if (InputModifiers & SISrcMods::ABS)
359 printOperand(MI, OpNo + 1, O);
360 if (InputModifiers & SISrcMods::ABS)
364 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
366 unsigned Imm = MI->getOperand(OpNum).getImm();
370 } else if (Imm == 1) {
372 } else if (Imm == 0) {
375 llvm_unreachable("Invalid interpolation parameter slot");
379 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
381 printOperand(MI, OpNo, O);
383 printOperand(MI, OpNo + 1, O);
386 void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
387 raw_ostream &O, StringRef Asm,
389 const MCOperand &Op = MI->getOperand(OpNo);
391 if (Op.getImm() == 1) {
398 void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
400 printIfSet(MI, OpNo, O, "|");
403 void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
405 printIfSet(MI, OpNo, O, "_SAT");
408 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
410 if (MI->getOperand(OpNo).getImm())
414 void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
416 int Imm = MI->getOperand(OpNo).getImm();
417 if (Imm == SIOutMods::MUL2)
419 else if (Imm == SIOutMods::MUL4)
421 else if (Imm == SIOutMods::DIV2)
425 void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
427 int32_t Imm = MI->getOperand(OpNo).getImm();
428 O << Imm << '(' << BitsToFloat(Imm) << ')';
431 void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
433 printIfSet(MI, OpNo, O, "*", " ");
436 void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
438 printIfSet(MI, OpNo, O, "-");
441 void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
443 switch (MI->getOperand(OpNo).getImm()) {
457 void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
459 printIfSet(MI, OpNo, O, "+");
462 void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
464 printIfSet(MI, OpNo, O, "ExecMask,");
467 void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
469 printIfSet(MI, OpNo, O, "Pred,");
472 void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
474 const MCOperand &Op = MI->getOperand(OpNo);
475 if (Op.getImm() == 0) {
480 void AMDGPUInstPrinter::printSel(const MCInst *MI, unsigned OpNo,
482 const char * chans = "XYZW";
483 int sel = MI->getOperand(OpNo).getImm();
492 O << cb << '[' << sel << ']';
493 } else if (sel >= 448) {
496 } else if (sel >= 0){
501 O << '.' << chans[chan];
504 void AMDGPUInstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo,
506 int BankSwizzle = MI->getOperand(OpNo).getImm();
507 switch (BankSwizzle) {
509 O << "BS:VEC_021/SCL_122";
512 O << "BS:VEC_120/SCL_212";
515 O << "BS:VEC_102/SCL_221";
529 void AMDGPUInstPrinter::printRSel(const MCInst *MI, unsigned OpNo,
531 unsigned Sel = MI->getOperand(OpNo).getImm();
559 void AMDGPUInstPrinter::printCT(const MCInst *MI, unsigned OpNo,
561 unsigned CT = MI->getOperand(OpNo).getImm();
574 void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
576 int KCacheMode = MI->getOperand(OpNo).getImm();
577 if (KCacheMode > 0) {
578 int KCacheBank = MI->getOperand(OpNo - 2).getImm();
579 O << "CB" << KCacheBank << ':';
580 int KCacheAddr = MI->getOperand(OpNo + 2).getImm();
581 int LineSize = (KCacheMode == 1) ? 16 : 32;
582 O << KCacheAddr * 16 << '-' << KCacheAddr * 16 + LineSize;
586 void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
588 unsigned SImm16 = MI->getOperand(OpNo).getImm();
589 unsigned Msg = SImm16 & 0xF;
590 if (Msg == 2 || Msg == 3) {
591 unsigned Op = (SImm16 >> 4) & 0xF;
599 unsigned Stream = (SImm16 >> 8) & 0x3;
606 O << " stream " << Stream;
614 O << "unknown(" << Msg << ") ";
617 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
619 // Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
620 // SIInsertWaits.cpp bits usage does not match ISA docs description but it
621 // works so it might be a misprint in docs.
622 unsigned SImm16 = MI->getOperand(OpNo).getImm();
623 unsigned Vmcnt = SImm16 & 0xF;
624 unsigned Expcnt = (SImm16 >> 4) & 0xF;
625 unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
627 bool NeedSpace = false;
630 O << "vmcnt(" << Vmcnt << ')';
637 O << "expcnt(" << Expcnt << ')';
641 if (Lgkmcnt != 0x7) {
644 O << "lgkmcnt(" << Lgkmcnt << ')';
648 #include "AMDGPUGenAsmWriter.inc"