1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for R600
13 //===----------------------------------------------------------------------===//
15 #include "R600ISelLowering.h"
16 #include "AMDGPUFrameLowering.h"
17 #include "AMDGPUIntrinsicInfo.h"
18 #include "AMDGPUSubtarget.h"
19 #include "R600Defines.h"
20 #include "R600InstrInfo.h"
21 #include "R600MachineFunctionInfo.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/IR/Argument.h"
29 #include "llvm/IR/Function.h"
33 R600TargetLowering::R600TargetLowering(TargetMachine &TM,
34 const AMDGPUSubtarget &STI)
35 : AMDGPUTargetLowering(TM, STI), Gen(STI.getGeneration()) {
36 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
37 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
38 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
39 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
40 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
41 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
43 computeRegisterProperties(STI.getRegisterInfo());
45 // Set condition code actions
46 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
47 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
48 setCondCodeAction(ISD::SETLT, MVT::f32, Expand);
49 setCondCodeAction(ISD::SETLE, MVT::f32, Expand);
50 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
51 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
52 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
53 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
54 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
55 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
56 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
57 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
59 setCondCodeAction(ISD::SETLE, MVT::i32, Expand);
60 setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
61 setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
62 setCondCodeAction(ISD::SETULT, MVT::i32, Expand);
64 setOperationAction(ISD::FCOS, MVT::f32, Custom);
65 setOperationAction(ISD::FSIN, MVT::f32, Custom);
67 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
68 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
70 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
71 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
72 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
74 setOperationAction(ISD::FSUB, MVT::f32, Expand);
76 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
77 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
78 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
80 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
81 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
83 setOperationAction(ISD::SETCC, MVT::i32, Expand);
84 setOperationAction(ISD::SETCC, MVT::f32, Expand);
85 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
86 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
87 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
89 setOperationAction(ISD::SELECT, MVT::i32, Expand);
90 setOperationAction(ISD::SELECT, MVT::f32, Expand);
91 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
92 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
95 // TODO: turn these into Legal?
96 if (Subtarget->hasCARRY())
97 setOperationAction(ISD::UADDO, MVT::i32, Custom);
99 if (Subtarget->hasBORROW())
100 setOperationAction(ISD::USUBO, MVT::i32, Custom);
102 // Expand sign extension of vectors
103 if (!Subtarget->hasBFE())
104 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand);
107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand);
109 if (!Subtarget->hasBFE())
110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
111 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand);
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand);
114 if (!Subtarget->hasBFE())
115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand);
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
126 // Legalize loads and stores to the private address space.
127 setOperationAction(ISD::LOAD, MVT::i32, Custom);
128 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
129 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
131 // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
132 // spaces, so it is custom lowered to handle those where it isn't.
133 for (MVT VT : MVT::integer_valuetypes()) {
134 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom);
136 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom);
138 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
139 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom);
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom);
142 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
143 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom);
144 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom);
147 setOperationAction(ISD::STORE, MVT::i8, Custom);
148 setOperationAction(ISD::STORE, MVT::i32, Custom);
149 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
150 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
151 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
152 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
154 setOperationAction(ISD::LOAD, MVT::i32, Custom);
155 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
156 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
158 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom);
159 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom);
160 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
161 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
163 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom);
164 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);
165 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
166 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
168 setTargetDAGCombine(ISD::FP_ROUND);
169 setTargetDAGCombine(ISD::FP_TO_SINT);
170 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
171 setTargetDAGCombine(ISD::SELECT_CC);
172 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
174 // We don't have 64-bit shifts. Thus we need either SHX i64 or SHX_PARTS i32
175 // to be Legal/Custom in order to avoid library calls.
176 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
177 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
178 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
180 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
182 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
183 for (MVT VT : ScalarIntVTs) {
184 setOperationAction(ISD::ADDC, VT, Expand);
185 setOperationAction(ISD::SUBC, VT, Expand);
186 setOperationAction(ISD::ADDE, VT, Expand);
187 setOperationAction(ISD::SUBE, VT, Expand);
190 setSchedulingPreference(Sched::Source);
193 static inline bool isEOP(MachineBasicBlock::iterator I) {
194 return std::next(I)->getOpcode() == AMDGPU::RETURN;
197 MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
198 MachineInstr * MI, MachineBasicBlock * BB) const {
199 MachineFunction * MF = BB->getParent();
200 MachineRegisterInfo &MRI = MF->getRegInfo();
201 MachineBasicBlock::iterator I = *MI;
202 const R600InstrInfo *TII =
203 static_cast<const R600InstrInfo *>(Subtarget->getInstrInfo());
205 switch (MI->getOpcode()) {
207 // Replace LDS_*_RET instruction that don't have any uses with the
208 // equivalent LDS_*_NORET instruction.
209 if (TII->isLDSRetInstr(MI->getOpcode())) {
210 int DstIdx = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
211 assert(DstIdx != -1);
212 MachineInstrBuilder NewMI;
213 // FIXME: getLDSNoRetOp method only handles LDS_1A1D LDS ops. Add
214 // LDS_1A2D support and remove this special case.
215 if (!MRI.use_empty(MI->getOperand(DstIdx).getReg()) ||
216 MI->getOpcode() == AMDGPU::LDS_CMPST_RET)
219 NewMI = BuildMI(*BB, I, BB->findDebugLoc(I),
220 TII->get(AMDGPU::getLDSNoRetOp(MI->getOpcode())));
221 for (unsigned i = 1, e = MI->getNumOperands(); i < e; ++i) {
222 NewMI.addOperand(MI->getOperand(i));
225 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
228 case AMDGPU::CLAMP_R600: {
229 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
231 MI->getOperand(0).getReg(),
232 MI->getOperand(1).getReg());
233 TII->addFlag(NewMI, 0, MO_FLAG_CLAMP);
237 case AMDGPU::FABS_R600: {
238 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
240 MI->getOperand(0).getReg(),
241 MI->getOperand(1).getReg());
242 TII->addFlag(NewMI, 0, MO_FLAG_ABS);
246 case AMDGPU::FNEG_R600: {
247 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, I,
249 MI->getOperand(0).getReg(),
250 MI->getOperand(1).getReg());
251 TII->addFlag(NewMI, 0, MO_FLAG_NEG);
255 case AMDGPU::MASK_WRITE: {
256 unsigned maskedRegister = MI->getOperand(0).getReg();
257 assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
258 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
259 TII->addFlag(defInstr, 0, MO_FLAG_MASK);
263 case AMDGPU::MOV_IMM_F32:
264 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
265 MI->getOperand(1).getFPImm()->getValueAPF()
266 .bitcastToAPInt().getZExtValue());
268 case AMDGPU::MOV_IMM_I32:
269 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
270 MI->getOperand(1).getImm());
272 case AMDGPU::CONST_COPY: {
273 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
274 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
275 TII->setImmOperand(NewMI, AMDGPU::OpName::src0_sel,
276 MI->getOperand(1).getImm());
280 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
281 case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
282 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
283 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
284 .addOperand(MI->getOperand(0))
285 .addOperand(MI->getOperand(1))
286 .addImm(isEOP(I)); // Set End of program bit
289 case AMDGPU::RAT_STORE_TYPED_eg: {
290 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
291 .addOperand(MI->getOperand(0))
292 .addOperand(MI->getOperand(1))
293 .addOperand(MI->getOperand(2))
294 .addImm(isEOP(I)); // Set End of program bit
299 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
300 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
301 MachineOperand &RID = MI->getOperand(4);
302 MachineOperand &SID = MI->getOperand(5);
303 unsigned TextureId = MI->getOperand(6).getImm();
304 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
305 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
317 case 8: // ShadowRect
328 case 11: // Shadow1DArray
332 case 12: // Shadow2DArray
336 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
337 .addOperand(MI->getOperand(3))
355 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
356 .addOperand(MI->getOperand(2))
374 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
375 .addOperand(MI->getOperand(0))
376 .addOperand(MI->getOperand(1))
394 .addReg(T0, RegState::Implicit)
395 .addReg(T1, RegState::Implicit);
399 case AMDGPU::TXD_SHADOW: {
400 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
401 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
402 MachineOperand &RID = MI->getOperand(4);
403 MachineOperand &SID = MI->getOperand(5);
404 unsigned TextureId = MI->getOperand(6).getImm();
405 unsigned SrcX = 0, SrcY = 1, SrcZ = 2, SrcW = 3;
406 unsigned CTX = 1, CTY = 1, CTZ = 1, CTW = 1;
418 case 8: // ShadowRect
429 case 11: // Shadow1DArray
433 case 12: // Shadow2DArray
438 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
439 .addOperand(MI->getOperand(3))
457 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
458 .addOperand(MI->getOperand(2))
476 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
477 .addOperand(MI->getOperand(0))
478 .addOperand(MI->getOperand(1))
496 .addReg(T0, RegState::Implicit)
497 .addReg(T1, RegState::Implicit);
502 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
503 .addOperand(MI->getOperand(0));
506 case AMDGPU::BRANCH_COND_f32: {
507 MachineInstr *NewMI =
508 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
509 AMDGPU::PREDICATE_BIT)
510 .addOperand(MI->getOperand(1))
511 .addImm(OPCODE_IS_NOT_ZERO)
513 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
514 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
515 .addOperand(MI->getOperand(0))
516 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
520 case AMDGPU::BRANCH_COND_i32: {
521 MachineInstr *NewMI =
522 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
523 AMDGPU::PREDICATE_BIT)
524 .addOperand(MI->getOperand(1))
525 .addImm(OPCODE_IS_NOT_ZERO_INT)
527 TII->addFlag(NewMI, 0, MO_FLAG_PUSH);
528 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
529 .addOperand(MI->getOperand(0))
530 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
534 case AMDGPU::EG_ExportSwz:
535 case AMDGPU::R600_ExportSwz: {
536 // Instruction is left unmodified if its not the last one of its type
537 bool isLastInstructionOfItsType = true;
538 unsigned InstExportType = MI->getOperand(1).getImm();
539 for (MachineBasicBlock::iterator NextExportInst = std::next(I),
540 EndBlock = BB->end(); NextExportInst != EndBlock;
541 NextExportInst = std::next(NextExportInst)) {
542 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
543 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
544 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
546 if (CurrentInstExportType == InstExportType) {
547 isLastInstructionOfItsType = false;
553 if (!EOP && !isLastInstructionOfItsType)
555 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
556 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
557 .addOperand(MI->getOperand(0))
558 .addOperand(MI->getOperand(1))
559 .addOperand(MI->getOperand(2))
560 .addOperand(MI->getOperand(3))
561 .addOperand(MI->getOperand(4))
562 .addOperand(MI->getOperand(5))
563 .addOperand(MI->getOperand(6))
568 case AMDGPU::RETURN: {
569 // RETURN instructions must have the live-out registers as implicit uses,
570 // otherwise they appear dead.
571 R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
572 MachineInstrBuilder MIB(*MF, MI);
573 for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
574 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
579 MI->eraseFromParent();
583 //===----------------------------------------------------------------------===//
584 // Custom DAG Lowering Operations
585 //===----------------------------------------------------------------------===//
587 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
588 MachineFunction &MF = DAG.getMachineFunction();
589 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
590 switch (Op.getOpcode()) {
591 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
592 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
593 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
594 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
596 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
597 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY);
598 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW);
600 case ISD::FSIN: return LowerTrig(Op, DAG);
601 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
602 case ISD::STORE: return LowerSTORE(Op, DAG);
604 SDValue Result = LowerLOAD(Op, DAG);
605 assert((!Result.getNode() ||
606 Result.getNode()->getNumValues() == 2) &&
607 "Load should return a value and a chain");
611 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
612 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
613 case ISD::INTRINSIC_VOID: {
614 SDValue Chain = Op.getOperand(0);
615 unsigned IntrinsicID =
616 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
617 switch (IntrinsicID) {
618 case AMDGPUIntrinsic::AMDGPU_store_output: {
619 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
620 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
621 MFI->LiveOuts.push_back(Reg);
622 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
624 case AMDGPUIntrinsic::R600_store_swizzle: {
626 const SDValue Args[8] = {
628 Op.getOperand(2), // Export Value
629 Op.getOperand(3), // ArrayBase
630 Op.getOperand(4), // Type
631 DAG.getConstant(0, DL, MVT::i32), // SWZ_X
632 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y
633 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z
634 DAG.getConstant(3, DL, MVT::i32) // SWZ_W
636 return DAG.getNode(AMDGPUISD::EXPORT, DL, Op.getValueType(), Args);
639 // default for switch(IntrinsicID)
642 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
645 case ISD::INTRINSIC_WO_CHAIN: {
646 unsigned IntrinsicID =
647 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
648 EVT VT = Op.getValueType();
650 switch(IntrinsicID) {
651 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
652 case AMDGPUIntrinsic::R600_load_input: {
653 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
654 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
655 MachineFunction &MF = DAG.getMachineFunction();
656 MachineRegisterInfo &MRI = MF.getRegInfo();
658 return DAG.getCopyFromReg(DAG.getEntryNode(),
659 SDLoc(DAG.getEntryNode()), Reg, VT);
662 case AMDGPUIntrinsic::R600_interp_input: {
663 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
664 int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
665 MachineSDNode *interp;
667 const R600InstrInfo *TII =
668 static_cast<const R600InstrInfo *>(Subtarget->getInstrInfo());
669 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
670 MVT::v4f32, DAG.getTargetConstant(slot / 4, DL, MVT::i32));
671 return DAG.getTargetExtractSubreg(
672 TII->getRegisterInfo().getSubRegFromChannel(slot % 4),
673 DL, MVT::f32, SDValue(interp, 0));
675 MachineFunction &MF = DAG.getMachineFunction();
676 MachineRegisterInfo &MRI = MF.getRegInfo();
677 unsigned RegisterI = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb);
678 unsigned RegisterJ = AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1);
679 MRI.addLiveIn(RegisterI);
680 MRI.addLiveIn(RegisterJ);
681 SDValue RegisterINode = DAG.getCopyFromReg(DAG.getEntryNode(),
682 SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32);
683 SDValue RegisterJNode = DAG.getCopyFromReg(DAG.getEntryNode(),
684 SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32);
687 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
688 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4, DL, MVT::i32),
689 RegisterJNode, RegisterINode);
691 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
692 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4, DL, MVT::i32),
693 RegisterJNode, RegisterINode);
694 return SDValue(interp, slot % 2);
696 case AMDGPUIntrinsic::R600_interp_xy:
697 case AMDGPUIntrinsic::R600_interp_zw: {
698 int slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
699 MachineSDNode *interp;
700 SDValue RegisterINode = Op.getOperand(2);
701 SDValue RegisterJNode = Op.getOperand(3);
703 if (IntrinsicID == AMDGPUIntrinsic::R600_interp_xy)
704 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
705 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, DL, MVT::i32),
706 RegisterJNode, RegisterINode);
708 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
709 MVT::f32, MVT::f32, DAG.getTargetConstant(slot, DL, MVT::i32),
710 RegisterJNode, RegisterINode);
711 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32,
712 SDValue(interp, 0), SDValue(interp, 1));
714 case AMDGPUIntrinsic::R600_tex:
715 case AMDGPUIntrinsic::R600_texc:
716 case AMDGPUIntrinsic::R600_txl:
717 case AMDGPUIntrinsic::R600_txlc:
718 case AMDGPUIntrinsic::R600_txb:
719 case AMDGPUIntrinsic::R600_txbc:
720 case AMDGPUIntrinsic::R600_txf:
721 case AMDGPUIntrinsic::R600_txq:
722 case AMDGPUIntrinsic::R600_ddx:
723 case AMDGPUIntrinsic::R600_ddy:
724 case AMDGPUIntrinsic::R600_ldptr: {
726 switch (IntrinsicID) {
727 case AMDGPUIntrinsic::R600_tex:
730 case AMDGPUIntrinsic::R600_texc:
733 case AMDGPUIntrinsic::R600_txl:
736 case AMDGPUIntrinsic::R600_txlc:
739 case AMDGPUIntrinsic::R600_txb:
742 case AMDGPUIntrinsic::R600_txbc:
745 case AMDGPUIntrinsic::R600_txf:
748 case AMDGPUIntrinsic::R600_txq:
751 case AMDGPUIntrinsic::R600_ddx:
754 case AMDGPUIntrinsic::R600_ddy:
757 case AMDGPUIntrinsic::R600_ldptr:
761 llvm_unreachable("Unknow Texture Operation");
764 SDValue TexArgs[19] = {
765 DAG.getConstant(TextureOp, DL, MVT::i32),
767 DAG.getConstant(0, DL, MVT::i32),
768 DAG.getConstant(1, DL, MVT::i32),
769 DAG.getConstant(2, DL, MVT::i32),
770 DAG.getConstant(3, DL, MVT::i32),
774 DAG.getConstant(0, DL, MVT::i32),
775 DAG.getConstant(1, DL, MVT::i32),
776 DAG.getConstant(2, DL, MVT::i32),
777 DAG.getConstant(3, DL, MVT::i32),
785 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
787 case AMDGPUIntrinsic::AMDGPU_dp4: {
789 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
790 DAG.getConstant(0, DL, MVT::i32)),
791 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
792 DAG.getConstant(0, DL, MVT::i32)),
793 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
794 DAG.getConstant(1, DL, MVT::i32)),
795 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
796 DAG.getConstant(1, DL, MVT::i32)),
797 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
798 DAG.getConstant(2, DL, MVT::i32)),
799 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
800 DAG.getConstant(2, DL, MVT::i32)),
801 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
802 DAG.getConstant(3, DL, MVT::i32)),
803 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
804 DAG.getConstant(3, DL, MVT::i32))
806 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args);
809 case Intrinsic::r600_read_ngroups_x:
810 return LowerImplicitParameter(DAG, VT, DL, 0);
811 case Intrinsic::r600_read_ngroups_y:
812 return LowerImplicitParameter(DAG, VT, DL, 1);
813 case Intrinsic::r600_read_ngroups_z:
814 return LowerImplicitParameter(DAG, VT, DL, 2);
815 case Intrinsic::r600_read_global_size_x:
816 return LowerImplicitParameter(DAG, VT, DL, 3);
817 case Intrinsic::r600_read_global_size_y:
818 return LowerImplicitParameter(DAG, VT, DL, 4);
819 case Intrinsic::r600_read_global_size_z:
820 return LowerImplicitParameter(DAG, VT, DL, 5);
821 case Intrinsic::r600_read_local_size_x:
822 return LowerImplicitParameter(DAG, VT, DL, 6);
823 case Intrinsic::r600_read_local_size_y:
824 return LowerImplicitParameter(DAG, VT, DL, 7);
825 case Intrinsic::r600_read_local_size_z:
826 return LowerImplicitParameter(DAG, VT, DL, 8);
828 case Intrinsic::AMDGPU_read_workdim: {
829 uint32_t ByteOffset = getImplicitParameterOffset(MFI, GRID_DIM);
830 return LowerImplicitParameter(DAG, VT, DL, ByteOffset / 4);
833 case Intrinsic::r600_read_tgid_x:
834 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
836 case Intrinsic::r600_read_tgid_y:
837 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
839 case Intrinsic::r600_read_tgid_z:
840 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
842 case Intrinsic::r600_read_tidig_x:
843 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
845 case Intrinsic::r600_read_tidig_y:
846 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
848 case Intrinsic::r600_read_tidig_z:
849 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
851 case Intrinsic::AMDGPU_rsq:
852 // XXX - I'm assuming SI's RSQ_LEGACY matches R600's behavior.
853 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
855 case AMDGPUIntrinsic::AMDGPU_fract:
856 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
857 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
859 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
862 } // end switch(Op.getOpcode())
866 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
867 SmallVectorImpl<SDValue> &Results,
868 SelectionDAG &DAG) const {
869 switch (N->getOpcode()) {
871 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG);
873 case ISD::FP_TO_UINT:
874 if (N->getValueType(0) == MVT::i1) {
875 Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
878 // Fall-through. Since we don't care about out of bounds values
879 // we can use FP_TO_SINT for uints too. The DAGLegalizer code for uint
880 // considers some extra cases which are not necessary here.
881 case ISD::FP_TO_SINT: {
883 if (expandFP_TO_SINT(N, Result, DAG))
884 Results.push_back(Result);
888 SDValue Op = SDValue(N, 1);
889 SDValue RES = LowerSDIVREM(Op, DAG);
890 Results.push_back(RES);
891 Results.push_back(RES.getValue(1));
895 SDValue Op = SDValue(N, 0);
896 LowerUDIVREM64(Op, DAG, Results);
902 SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG,
903 SDValue Vector) const {
906 EVT VecVT = Vector.getValueType();
907 EVT EltVT = VecVT.getVectorElementType();
908 SmallVector<SDValue, 8> Args;
910 for (unsigned i = 0, e = VecVT.getVectorNumElements();
912 Args.push_back(DAG.getNode(
913 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vector,
914 DAG.getConstant(i, DL, getVectorIdxTy(DAG.getDataLayout()))));
917 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args);
920 SDValue R600TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
921 SelectionDAG &DAG) const {
924 SDValue Vector = Op.getOperand(0);
925 SDValue Index = Op.getOperand(1);
927 if (isa<ConstantSDNode>(Index) ||
928 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
931 Vector = vectorToVerticalVector(DAG, Vector);
932 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(),
936 SDValue R600TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
937 SelectionDAG &DAG) const {
939 SDValue Vector = Op.getOperand(0);
940 SDValue Value = Op.getOperand(1);
941 SDValue Index = Op.getOperand(2);
943 if (isa<ConstantSDNode>(Index) ||
944 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
947 Vector = vectorToVerticalVector(DAG, Vector);
948 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(),
949 Vector, Value, Index);
950 return vectorToVerticalVector(DAG, Insert);
953 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
954 // On hw >= R700, COS/SIN input must be between -1. and 1.
955 // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
956 EVT VT = Op.getValueType();
957 SDValue Arg = Op.getOperand(0);
960 // TODO: Should this propagate fast-math-flags?
961 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT,
962 DAG.getNode(ISD::FADD, DL, VT,
963 DAG.getNode(ISD::FMUL, DL, VT, Arg,
964 DAG.getConstantFP(0.15915494309, DL, MVT::f32)),
965 DAG.getConstantFP(0.5, DL, MVT::f32)));
967 switch (Op.getOpcode()) {
969 TrigNode = AMDGPUISD::COS_HW;
972 TrigNode = AMDGPUISD::SIN_HW;
975 llvm_unreachable("Wrong trig opcode");
977 SDValue TrigVal = DAG.getNode(TrigNode, DL, VT,
978 DAG.getNode(ISD::FADD, DL, VT, FractPart,
979 DAG.getConstantFP(-0.5, DL, MVT::f32)));
980 if (Gen >= AMDGPUSubtarget::R700)
982 // On R600 hw, COS/SIN input must be between -Pi and Pi.
983 return DAG.getNode(ISD::FMUL, DL, VT, TrigVal,
984 DAG.getConstantFP(3.14159265359, DL, MVT::f32));
987 SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const {
989 EVT VT = Op.getValueType();
991 SDValue Lo = Op.getOperand(0);
992 SDValue Hi = Op.getOperand(1);
993 SDValue Shift = Op.getOperand(2);
994 SDValue Zero = DAG.getConstant(0, DL, VT);
995 SDValue One = DAG.getConstant(1, DL, VT);
997 SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT);
998 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT);
999 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
1000 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
1002 // The dance around Width1 is necessary for 0 special case.
1003 // Without it the CompShift might be 32, producing incorrect results in
1004 // Overflow. So we do the shift in two steps, the alternative is to
1005 // add a conditional to filter the special case.
1007 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift);
1008 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One);
1010 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift);
1011 HiSmall = DAG.getNode(ISD::OR, DL, VT, HiSmall, Overflow);
1012 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift);
1014 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift);
1015 SDValue LoBig = Zero;
1017 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
1018 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
1020 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
1023 SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const {
1025 EVT VT = Op.getValueType();
1027 SDValue Lo = Op.getOperand(0);
1028 SDValue Hi = Op.getOperand(1);
1029 SDValue Shift = Op.getOperand(2);
1030 SDValue Zero = DAG.getConstant(0, DL, VT);
1031 SDValue One = DAG.getConstant(1, DL, VT);
1033 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS;
1035 SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT);
1036 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT);
1037 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width);
1038 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift);
1040 // The dance around Width1 is necessary for 0 special case.
1041 // Without it the CompShift might be 32, producing incorrect results in
1042 // Overflow. So we do the shift in two steps, the alternative is to
1043 // add a conditional to filter the special case.
1045 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift);
1046 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One);
1048 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift);
1049 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift);
1050 LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow);
1052 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift);
1053 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero;
1055 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT);
1056 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
1058 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi);
1061 SDValue R600TargetLowering::LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
1062 unsigned mainop, unsigned ovf) const {
1064 EVT VT = Op.getValueType();
1066 SDValue Lo = Op.getOperand(0);
1067 SDValue Hi = Op.getOperand(1);
1069 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi);
1071 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF,
1072 DAG.getValueType(MVT::i1));
1074 SDValue Res = DAG.getNode(mainop, DL, VT, Lo, Hi);
1076 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF);
1079 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const {
1085 Op, DAG.getConstantFP(0.0f, DL, MVT::f32),
1086 DAG.getCondCode(ISD::SETNE)
1090 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
1092 unsigned DwordOffset) const {
1093 unsigned ByteOffset = DwordOffset * 4;
1094 PointerType * PtrType = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1095 AMDGPUAS::CONSTANT_BUFFER_0);
1097 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
1098 assert(isInt<16>(ByteOffset));
1100 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
1101 DAG.getConstant(ByteOffset, DL, MVT::i32), // PTR
1102 MachinePointerInfo(ConstantPointerNull::get(PtrType)),
1103 false, false, false, 0);
1106 bool R600TargetLowering::isZero(SDValue Op) const {
1107 if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
1108 return Cst->isNullValue();
1109 } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
1110 return CstFP->isZero();
1116 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
1118 EVT VT = Op.getValueType();
1120 SDValue LHS = Op.getOperand(0);
1121 SDValue RHS = Op.getOperand(1);
1122 SDValue True = Op.getOperand(2);
1123 SDValue False = Op.getOperand(3);
1124 SDValue CC = Op.getOperand(4);
1127 if (VT == MVT::f32) {
1128 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
1129 SDValue MinMax = CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
1134 // LHS and RHS are guaranteed to be the same value type
1135 EVT CompareVT = LHS.getValueType();
1137 // Check if we can lower this to a native operation.
1139 // Try to lower to a SET* instruction:
1141 // SET* can match the following patterns:
1143 // select_cc f32, f32, -1, 0, cc_supported
1144 // select_cc f32, f32, 1.0f, 0.0f, cc_supported
1145 // select_cc i32, i32, -1, 0, cc_supported
1148 // Move hardware True/False values to the correct operand.
1149 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1150 ISD::CondCode InverseCC =
1151 ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
1152 if (isHWTrueValue(False) && isHWFalseValue(True)) {
1153 if (isCondCodeLegal(InverseCC, CompareVT.getSimpleVT())) {
1154 std::swap(False, True);
1155 CC = DAG.getCondCode(InverseCC);
1157 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InverseCC);
1158 if (isCondCodeLegal(SwapInvCC, CompareVT.getSimpleVT())) {
1159 std::swap(False, True);
1160 std::swap(LHS, RHS);
1161 CC = DAG.getCondCode(SwapInvCC);
1166 if (isHWTrueValue(True) && isHWFalseValue(False) &&
1167 (CompareVT == VT || VT == MVT::i32)) {
1168 // This can be matched by a SET* instruction.
1169 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
1172 // Try to lower to a CND* instruction:
1174 // CND* can match the following patterns:
1176 // select_cc f32, 0.0, f32, f32, cc_supported
1177 // select_cc f32, 0.0, i32, i32, cc_supported
1178 // select_cc i32, 0, f32, f32, cc_supported
1179 // select_cc i32, 0, i32, i32, cc_supported
1182 // Try to move the zero value to the RHS
1184 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1185 // Try swapping the operands
1186 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode);
1187 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
1188 std::swap(LHS, RHS);
1189 CC = DAG.getCondCode(CCSwapped);
1191 // Try inverting the conditon and then swapping the operands
1192 ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger());
1193 CCSwapped = ISD::getSetCCSwappedOperands(CCInv);
1194 if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
1195 std::swap(True, False);
1196 std::swap(LHS, RHS);
1197 CC = DAG.getCondCode(CCSwapped);
1204 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1205 if (CompareVT != VT) {
1206 // Bitcast True / False to the correct types. This will end up being
1207 // a nop, but it allows us to define only a single pattern in the
1208 // .TD files for each CND* instruction rather than having to have
1209 // one pattern for integer True/False and one for fp True/False
1210 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
1211 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
1218 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
1226 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
1229 DAG.getCondCode(CCOpcode));
1230 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
1233 // If we make it this for it means we have no native instructions to handle
1234 // this SELECT_CC, so we must lower it.
1235 SDValue HWTrue, HWFalse;
1237 if (CompareVT == MVT::f32) {
1238 HWTrue = DAG.getConstantFP(1.0f, DL, CompareVT);
1239 HWFalse = DAG.getConstantFP(0.0f, DL, CompareVT);
1240 } else if (CompareVT == MVT::i32) {
1241 HWTrue = DAG.getConstant(-1, DL, CompareVT);
1242 HWFalse = DAG.getConstant(0, DL, CompareVT);
1245 llvm_unreachable("Unhandled value type in LowerSELECT_CC");
1248 // Lower this unsupported SELECT_CC into a combination of two supported
1249 // SELECT_CC operations.
1250 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
1252 return DAG.getNode(ISD::SELECT_CC, DL, VT,
1255 DAG.getCondCode(ISD::SETNE));
1258 /// LLVM generates byte-addressed pointers. For indirect addressing, we need to
1259 /// convert these pointers to a register index. Each register holds
1260 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
1261 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
1262 /// for indirect addressing.
1263 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
1264 unsigned StackWidth,
1265 SelectionDAG &DAG) const {
1267 switch(StackWidth) {
1277 default: llvm_unreachable("Invalid stack width");
1281 return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr,
1282 DAG.getConstant(SRLPad, DL, MVT::i32));
1285 void R600TargetLowering::getStackAddress(unsigned StackWidth,
1288 unsigned &PtrIncr) const {
1289 switch (StackWidth) {
1300 Channel = ElemIdx % 2;
1314 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1316 StoreSDNode *StoreNode = cast<StoreSDNode>(Op);
1317 SDValue Chain = Op.getOperand(0);
1318 SDValue Value = Op.getOperand(1);
1319 SDValue Ptr = Op.getOperand(2);
1321 SDValue Result = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1322 if (Result.getNode()) {
1326 if (StoreNode->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS) {
1327 if (StoreNode->isTruncatingStore()) {
1328 EVT VT = Value.getValueType();
1329 assert(VT.bitsLE(MVT::i32));
1330 EVT MemVT = StoreNode->getMemoryVT();
1331 SDValue MaskConstant;
1332 if (MemVT == MVT::i8) {
1333 MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32);
1335 assert(MemVT == MVT::i16);
1336 MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32);
1338 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr,
1339 DAG.getConstant(2, DL, MVT::i32));
1340 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, Ptr.getValueType(), Ptr,
1341 DAG.getConstant(0x00000003, DL, VT));
1342 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
1343 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
1344 DAG.getConstant(3, DL, VT));
1345 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift);
1346 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift);
1347 // XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32
1351 DAG.getConstant(0, DL, MVT::i32),
1352 DAG.getConstant(0, DL, MVT::i32),
1355 SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src);
1356 SDValue Args[3] = { Chain, Input, DWordAddr };
1357 return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL,
1358 Op->getVTList(), Args, MemVT,
1359 StoreNode->getMemOperand());
1360 } else if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR &&
1361 Value.getValueType().bitsGE(MVT::i32)) {
1362 // Convert pointer from byte address to dword address.
1363 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, Ptr.getValueType(),
1364 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
1365 Ptr, DAG.getConstant(2, DL, MVT::i32)));
1367 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
1368 llvm_unreachable("Truncated and indexed stores not supported yet");
1370 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
1376 EVT ValueVT = Value.getValueType();
1378 if (StoreNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1382 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1383 if (Ret.getNode()) {
1386 // Lowering for indirect addressing
1388 const MachineFunction &MF = DAG.getMachineFunction();
1389 const AMDGPUFrameLowering *TFL =
1390 static_cast<const AMDGPUFrameLowering *>(Subtarget->getFrameLowering());
1391 unsigned StackWidth = TFL->getStackWidth(MF);
1393 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1395 if (ValueVT.isVector()) {
1396 unsigned NumElemVT = ValueVT.getVectorNumElements();
1397 EVT ElemVT = ValueVT.getVectorElementType();
1398 SmallVector<SDValue, 4> Stores(NumElemVT);
1400 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1401 "vector width in load");
1403 for (unsigned i = 0; i < NumElemVT; ++i) {
1404 unsigned Channel, PtrIncr;
1405 getStackAddress(StackWidth, i, Channel, PtrIncr);
1406 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1407 DAG.getConstant(PtrIncr, DL, MVT::i32));
1408 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
1409 Value, DAG.getConstant(i, DL, MVT::i32));
1411 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1413 DAG.getTargetConstant(Channel, DL, MVT::i32));
1415 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores);
1417 if (ValueVT == MVT::i8) {
1418 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1420 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
1421 DAG.getTargetConstant(0, DL, MVT::i32)); // Channel
1427 // return (512 + (kc_bank << 12)
1429 ConstantAddressBlock(unsigned AddressSpace) {
1430 switch (AddressSpace) {
1431 case AMDGPUAS::CONSTANT_BUFFER_0:
1433 case AMDGPUAS::CONSTANT_BUFFER_1:
1435 case AMDGPUAS::CONSTANT_BUFFER_2:
1436 return 512 + 4096 * 2;
1437 case AMDGPUAS::CONSTANT_BUFFER_3:
1438 return 512 + 4096 * 3;
1439 case AMDGPUAS::CONSTANT_BUFFER_4:
1440 return 512 + 4096 * 4;
1441 case AMDGPUAS::CONSTANT_BUFFER_5:
1442 return 512 + 4096 * 5;
1443 case AMDGPUAS::CONSTANT_BUFFER_6:
1444 return 512 + 4096 * 6;
1445 case AMDGPUAS::CONSTANT_BUFFER_7:
1446 return 512 + 4096 * 7;
1447 case AMDGPUAS::CONSTANT_BUFFER_8:
1448 return 512 + 4096 * 8;
1449 case AMDGPUAS::CONSTANT_BUFFER_9:
1450 return 512 + 4096 * 9;
1451 case AMDGPUAS::CONSTANT_BUFFER_10:
1452 return 512 + 4096 * 10;
1453 case AMDGPUAS::CONSTANT_BUFFER_11:
1454 return 512 + 4096 * 11;
1455 case AMDGPUAS::CONSTANT_BUFFER_12:
1456 return 512 + 4096 * 12;
1457 case AMDGPUAS::CONSTANT_BUFFER_13:
1458 return 512 + 4096 * 13;
1459 case AMDGPUAS::CONSTANT_BUFFER_14:
1460 return 512 + 4096 * 14;
1461 case AMDGPUAS::CONSTANT_BUFFER_15:
1462 return 512 + 4096 * 15;
1468 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
1470 EVT VT = Op.getValueType();
1472 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1473 SDValue Chain = Op.getOperand(0);
1474 SDValue Ptr = Op.getOperand(1);
1475 SDValue LoweredLoad;
1477 if (SDValue Ret = AMDGPUTargetLowering::LowerLOAD(Op, DAG))
1480 // Lower loads constant address space global variable loads
1481 if (LoadNode->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
1482 isa<GlobalVariable>(GetUnderlyingObject(
1483 LoadNode->getMemOperand()->getValue(), DAG.getDataLayout()))) {
1485 SDValue Ptr = DAG.getZExtOrTrunc(
1486 LoadNode->getBasePtr(), DL,
1487 getPointerTy(DAG.getDataLayout(), AMDGPUAS::PRIVATE_ADDRESS));
1488 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1489 DAG.getConstant(2, DL, MVT::i32));
1490 return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op->getVTList(),
1491 LoadNode->getChain(), Ptr,
1492 DAG.getTargetConstant(0, DL, MVT::i32),
1496 if (LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS && VT.isVector()) {
1497 SDValue MergedValues[2] = {
1498 ScalarizeVectorLoad(Op, DAG),
1501 return DAG.getMergeValues(MergedValues, DL);
1504 int ConstantBlock = ConstantAddressBlock(LoadNode->getAddressSpace());
1505 if (ConstantBlock > -1 &&
1506 ((LoadNode->getExtensionType() == ISD::NON_EXTLOAD) ||
1507 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) {
1509 if (isa<ConstantExpr>(LoadNode->getMemOperand()->getValue()) ||
1510 isa<Constant>(LoadNode->getMemOperand()->getValue()) ||
1511 isa<ConstantSDNode>(Ptr)) {
1513 for (unsigned i = 0; i < 4; i++) {
1514 // We want Const position encoded with the following formula :
1515 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1516 // const_index is Ptr computed by llvm using an alignment of 16.
1517 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1518 // then div by 4 at the ISel step
1519 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1520 DAG.getConstant(4 * i + ConstantBlock * 16, DL, MVT::i32));
1521 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1523 EVT NewVT = MVT::v4i32;
1524 unsigned NumElements = 4;
1525 if (VT.isVector()) {
1527 NumElements = VT.getVectorNumElements();
1529 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT,
1530 makeArrayRef(Slots, NumElements));
1532 // non-constant ptr can't be folded, keeps it as a v4f32 load
1533 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1534 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1535 DAG.getConstant(4, DL, MVT::i32)),
1536 DAG.getConstant(LoadNode->getAddressSpace() -
1537 AMDGPUAS::CONSTANT_BUFFER_0, DL, MVT::i32)
1541 if (!VT.isVector()) {
1542 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1543 DAG.getConstant(0, DL, MVT::i32));
1546 SDValue MergedValues[2] = {
1550 return DAG.getMergeValues(MergedValues, DL);
1553 // For most operations returning SDValue() will result in the node being
1554 // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so we
1555 // need to manually expand loads that may be legal in some address spaces and
1556 // illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported for
1557 // compute shaders, since the data is sign extended when it is uploaded to the
1558 // buffer. However SEXT loads from other address spaces are not supported, so
1559 // we need to expand them here.
1560 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1561 EVT MemVT = LoadNode->getMemoryVT();
1562 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1563 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr,
1564 LoadNode->getPointerInfo(), MemVT,
1565 LoadNode->isVolatile(),
1566 LoadNode->isNonTemporal(),
1567 LoadNode->isInvariant(),
1568 LoadNode->getAlignment());
1569 SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad,
1570 DAG.getValueType(MemVT));
1572 SDValue MergedValues[2] = { Res, Chain };
1573 return DAG.getMergeValues(MergedValues, DL);
1576 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1580 // Lowering for indirect addressing
1581 const MachineFunction &MF = DAG.getMachineFunction();
1582 const AMDGPUFrameLowering *TFL =
1583 static_cast<const AMDGPUFrameLowering *>(Subtarget->getFrameLowering());
1584 unsigned StackWidth = TFL->getStackWidth(MF);
1586 Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
1588 if (VT.isVector()) {
1589 unsigned NumElemVT = VT.getVectorNumElements();
1590 EVT ElemVT = VT.getVectorElementType();
1593 assert(NumElemVT >= StackWidth && "Stack width cannot be greater than "
1594 "vector width in load");
1596 for (unsigned i = 0; i < NumElemVT; ++i) {
1597 unsigned Channel, PtrIncr;
1598 getStackAddress(StackWidth, i, Channel, PtrIncr);
1599 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1600 DAG.getConstant(PtrIncr, DL, MVT::i32));
1601 Loads[i] = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, ElemVT,
1603 DAG.getTargetConstant(Channel, DL, MVT::i32),
1606 for (unsigned i = NumElemVT; i < 4; ++i) {
1607 Loads[i] = DAG.getUNDEF(ElemVT);
1609 EVT TargetVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, 4);
1610 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads);
1612 LoweredLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, VT,
1614 DAG.getTargetConstant(0, DL, MVT::i32), // Channel
1623 return DAG.getMergeValues(Ops, DL);
1626 SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1627 SDValue Chain = Op.getOperand(0);
1628 SDValue Cond = Op.getOperand(1);
1629 SDValue Jump = Op.getOperand(2);
1631 return DAG.getNode(AMDGPUISD::BRANCH_COND, SDLoc(Op), Op.getValueType(),
1635 /// XXX Only kernel functions are supported, so we can assume for now that
1636 /// every function is a kernel function, but in the future we should use
1637 /// separate calling conventions for kernel and non-kernel functions.
1638 SDValue R600TargetLowering::LowerFormalArguments(
1640 CallingConv::ID CallConv,
1642 const SmallVectorImpl<ISD::InputArg> &Ins,
1643 SDLoc DL, SelectionDAG &DAG,
1644 SmallVectorImpl<SDValue> &InVals) const {
1645 SmallVector<CCValAssign, 16> ArgLocs;
1646 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1648 MachineFunction &MF = DAG.getMachineFunction();
1649 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
1651 SmallVector<ISD::InputArg, 8> LocalIns;
1653 getOriginalFunctionArgs(DAG, MF.getFunction(), Ins, LocalIns);
1655 AnalyzeFormalArguments(CCInfo, LocalIns);
1657 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1658 CCValAssign &VA = ArgLocs[i];
1659 const ISD::InputArg &In = Ins[i];
1661 EVT MemVT = VA.getLocVT();
1662 if (!VT.isVector() && MemVT.isVector()) {
1663 // Get load source type if scalarized.
1664 MemVT = MemVT.getVectorElementType();
1667 if (MFI->getShaderType() != ShaderType::COMPUTE) {
1668 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass);
1669 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT);
1670 InVals.push_back(Register);
1674 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
1675 AMDGPUAS::CONSTANT_BUFFER_0);
1677 // i64 isn't a legal type, so the register type used ends up as i32, which
1678 // isn't expected here. It attempts to create this sextload, but it ends up
1679 // being invalid. Somehow this seems to work with i64 arguments, but breaks
1682 // The first 36 bytes of the input buffer contains information about
1683 // thread group and global sizes.
1684 ISD::LoadExtType Ext = ISD::NON_EXTLOAD;
1685 if (MemVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) {
1686 // FIXME: This should really check the extload type, but the handling of
1687 // extload vector parameters seems to be broken.
1689 // Ext = In.Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
1690 Ext = ISD::SEXTLOAD;
1693 // Compute the offset from the value.
1694 // XXX - I think PartOffset should give you this, but it seems to give the
1695 // size of the register which isn't useful.
1697 unsigned ValBase = ArgLocs[In.getOrigArgIndex()].getLocMemOffset();
1698 unsigned PartOffset = VA.getLocMemOffset();
1699 unsigned Offset = 36 + VA.getLocMemOffset();
1701 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy), PartOffset - ValBase);
1702 SDValue Arg = DAG.getLoad(ISD::UNINDEXED, Ext, VT, DL, Chain,
1703 DAG.getConstant(Offset, DL, MVT::i32),
1704 DAG.getUNDEF(MVT::i32),
1706 MemVT, false, true, true, 4);
1708 // 4 is the preferred alignment for the CONSTANT memory space.
1709 InVals.push_back(Arg);
1710 MFI->ABIArgOffset = Offset + MemVT.getStoreSize();
1715 EVT R600TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1719 return VT.changeVectorElementTypeToInteger();
1722 static SDValue CompactSwizzlableVector(
1723 SelectionDAG &DAG, SDValue VectorEntry,
1724 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1725 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1726 assert(RemapSwizzle.empty());
1727 SDValue NewBldVec[4] = {
1728 VectorEntry.getOperand(0),
1729 VectorEntry.getOperand(1),
1730 VectorEntry.getOperand(2),
1731 VectorEntry.getOperand(3)
1734 for (unsigned i = 0; i < 4; i++) {
1735 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1736 // We mask write here to teach later passes that the ith element of this
1737 // vector is undef. Thus we can use it to reduce 128 bits reg usage,
1738 // break false dependencies and additionnaly make assembly easier to read.
1739 RemapSwizzle[i] = 7; // SEL_MASK_WRITE
1740 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
1742 RemapSwizzle[i] = 4; // SEL_0
1743 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1744 } else if (C->isExactlyValue(1.0)) {
1745 RemapSwizzle[i] = 5; // SEL_1
1746 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1750 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1752 for (unsigned j = 0; j < i; j++) {
1753 if (NewBldVec[i] == NewBldVec[j]) {
1754 NewBldVec[i] = DAG.getUNDEF(NewBldVec[i].getValueType());
1755 RemapSwizzle[i] = j;
1761 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1762 VectorEntry.getValueType(), NewBldVec);
1765 static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1766 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1767 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1768 assert(RemapSwizzle.empty());
1769 SDValue NewBldVec[4] = {
1770 VectorEntry.getOperand(0),
1771 VectorEntry.getOperand(1),
1772 VectorEntry.getOperand(2),
1773 VectorEntry.getOperand(3)
1775 bool isUnmovable[4] = { false, false, false, false };
1776 for (unsigned i = 0; i < 4; i++) {
1777 RemapSwizzle[i] = i;
1778 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1779 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1782 isUnmovable[Idx] = true;
1786 for (unsigned i = 0; i < 4; i++) {
1787 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1788 unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
1790 if (isUnmovable[Idx])
1793 std::swap(NewBldVec[Idx], NewBldVec[i]);
1794 std::swap(RemapSwizzle[i], RemapSwizzle[Idx]);
1799 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1800 VectorEntry.getValueType(), NewBldVec);
1804 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector,
1805 SDValue Swz[4], SelectionDAG &DAG,
1807 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
1808 // Old -> New swizzle values
1809 DenseMap<unsigned, unsigned> SwizzleRemap;
1811 BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
1812 for (unsigned i = 0; i < 4; i++) {
1813 unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
1814 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1815 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
1818 SwizzleRemap.clear();
1819 BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
1820 for (unsigned i = 0; i < 4; i++) {
1821 unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
1822 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1823 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
1830 //===----------------------------------------------------------------------===//
1831 // Custom DAG Optimizations
1832 //===----------------------------------------------------------------------===//
1834 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1835 DAGCombinerInfo &DCI) const {
1836 SelectionDAG &DAG = DCI.DAG;
1838 switch (N->getOpcode()) {
1839 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1840 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1841 case ISD::FP_ROUND: {
1842 SDValue Arg = N->getOperand(0);
1843 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1844 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0),
1850 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1851 // (i32 select_cc f32, f32, -1, 0 cc)
1853 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1854 // this to one of the SET*_DX10 instructions.
1855 case ISD::FP_TO_SINT: {
1856 SDValue FNeg = N->getOperand(0);
1857 if (FNeg.getOpcode() != ISD::FNEG) {
1860 SDValue SelectCC = FNeg.getOperand(0);
1861 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1862 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1863 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1864 !isHWTrueValue(SelectCC.getOperand(2)) ||
1865 !isHWFalseValue(SelectCC.getOperand(3))) {
1870 return DAG.getNode(ISD::SELECT_CC, dl, N->getValueType(0),
1871 SelectCC.getOperand(0), // LHS
1872 SelectCC.getOperand(1), // RHS
1873 DAG.getConstant(-1, dl, MVT::i32), // True
1874 DAG.getConstant(0, dl, MVT::i32), // False
1875 SelectCC.getOperand(4)); // CC
1880 // insert_vector_elt (build_vector elt0, ... , eltN), NewEltIdx, idx
1881 // => build_vector elt0, ... , NewEltIdx, ... , eltN
1882 case ISD::INSERT_VECTOR_ELT: {
1883 SDValue InVec = N->getOperand(0);
1884 SDValue InVal = N->getOperand(1);
1885 SDValue EltNo = N->getOperand(2);
1888 // If the inserted element is an UNDEF, just use the input vector.
1889 if (InVal.getOpcode() == ISD::UNDEF)
1892 EVT VT = InVec.getValueType();
1894 // If we can't generate a legal BUILD_VECTOR, exit
1895 if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
1898 // Check that we know which element is being inserted
1899 if (!isa<ConstantSDNode>(EltNo))
1901 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
1903 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
1904 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
1906 SmallVector<SDValue, 8> Ops;
1907 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1908 Ops.append(InVec.getNode()->op_begin(),
1909 InVec.getNode()->op_end());
1910 } else if (InVec.getOpcode() == ISD::UNDEF) {
1911 unsigned NElts = VT.getVectorNumElements();
1912 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
1917 // Insert the element
1918 if (Elt < Ops.size()) {
1919 // All the operands of BUILD_VECTOR must have the same type;
1920 // we enforce that here.
1921 EVT OpVT = Ops[0].getValueType();
1922 if (InVal.getValueType() != OpVT)
1923 InVal = OpVT.bitsGT(InVal.getValueType()) ?
1924 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
1925 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
1929 // Return the new vector
1930 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
1933 // Extract_vec (Build_vector) generated by custom lowering
1934 // also needs to be customly combined
1935 case ISD::EXTRACT_VECTOR_ELT: {
1936 SDValue Arg = N->getOperand(0);
1937 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1938 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1939 unsigned Element = Const->getZExtValue();
1940 return Arg->getOperand(Element);
1943 if (Arg.getOpcode() == ISD::BITCAST &&
1944 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1945 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1946 unsigned Element = Const->getZExtValue();
1947 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(),
1948 Arg->getOperand(0).getOperand(Element));
1954 case ISD::SELECT_CC: {
1955 // Try common optimizations
1956 SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1960 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1961 // selectcc x, y, a, b, inv(cc)
1963 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1964 // selectcc x, y, a, b, cc
1965 SDValue LHS = N->getOperand(0);
1966 if (LHS.getOpcode() != ISD::SELECT_CC) {
1970 SDValue RHS = N->getOperand(1);
1971 SDValue True = N->getOperand(2);
1972 SDValue False = N->getOperand(3);
1973 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1975 if (LHS.getOperand(2).getNode() != True.getNode() ||
1976 LHS.getOperand(3).getNode() != False.getNode() ||
1977 RHS.getNode() != False.getNode()) {
1982 default: return SDValue();
1983 case ISD::SETNE: return LHS;
1985 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1986 LHSCC = ISD::getSetCCInverse(LHSCC,
1987 LHS.getOperand(0).getValueType().isInteger());
1988 if (DCI.isBeforeLegalizeOps() ||
1989 isCondCodeLegal(LHSCC, LHS.getOperand(0).getSimpleValueType()))
1990 return DAG.getSelectCC(SDLoc(N),
2002 case AMDGPUISD::EXPORT: {
2003 SDValue Arg = N->getOperand(1);
2004 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
2007 SDValue NewArgs[8] = {
2008 N->getOperand(0), // Chain
2010 N->getOperand(2), // ArrayBase
2011 N->getOperand(3), // Type
2012 N->getOperand(4), // SWZ_X
2013 N->getOperand(5), // SWZ_Y
2014 N->getOperand(6), // SWZ_Z
2015 N->getOperand(7) // SWZ_W
2018 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG, DL);
2019 return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs);
2021 case AMDGPUISD::TEXTURE_FETCH: {
2022 SDValue Arg = N->getOperand(1);
2023 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
2026 SDValue NewArgs[19] = {
2048 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG, DL);
2049 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, N->getVTList(), NewArgs);
2053 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
2057 FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg,
2058 SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG) {
2059 const R600InstrInfo *TII =
2060 static_cast<const R600InstrInfo *>(DAG.getSubtarget().getInstrInfo());
2061 if (!Src.isMachineOpcode())
2063 switch (Src.getMachineOpcode()) {
2064 case AMDGPU::FNEG_R600:
2067 Src = Src.getOperand(0);
2068 Neg = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32);
2070 case AMDGPU::FABS_R600:
2073 Src = Src.getOperand(0);
2074 Abs = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32);
2076 case AMDGPU::CONST_COPY: {
2077 unsigned Opcode = ParentNode->getMachineOpcode();
2078 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2083 SDValue CstOffset = Src.getOperand(0);
2084 if (ParentNode->getValueType(0).isVector())
2087 // Gather constants values
2088 int SrcIndices[] = {
2089 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
2090 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
2091 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2),
2092 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
2093 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
2094 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
2095 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
2096 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
2097 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
2098 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
2099 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
2101 std::vector<unsigned> Consts;
2102 for (int OtherSrcIdx : SrcIndices) {
2103 int OtherSelIdx = TII->getSelIdx(Opcode, OtherSrcIdx);
2104 if (OtherSrcIdx < 0 || OtherSelIdx < 0)
2110 if (RegisterSDNode *Reg =
2111 dyn_cast<RegisterSDNode>(ParentNode->getOperand(OtherSrcIdx))) {
2112 if (Reg->getReg() == AMDGPU::ALU_CONST) {
2114 = cast<ConstantSDNode>(ParentNode->getOperand(OtherSelIdx));
2115 Consts.push_back(Cst->getZExtValue());
2120 ConstantSDNode *Cst = cast<ConstantSDNode>(CstOffset);
2121 Consts.push_back(Cst->getZExtValue());
2122 if (!TII->fitsConstReadLimitations(Consts)) {
2127 Src = DAG.getRegister(AMDGPU::ALU_CONST, MVT::f32);
2130 case AMDGPU::MOV_IMM_I32:
2131 case AMDGPU::MOV_IMM_F32: {
2132 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
2133 uint64_t ImmValue = 0;
2136 if (Src.getMachineOpcode() == AMDGPU::MOV_IMM_F32) {
2137 ConstantFPSDNode *FPC = dyn_cast<ConstantFPSDNode>(Src.getOperand(0));
2138 float FloatValue = FPC->getValueAPF().convertToFloat();
2139 if (FloatValue == 0.0) {
2140 ImmReg = AMDGPU::ZERO;
2141 } else if (FloatValue == 0.5) {
2142 ImmReg = AMDGPU::HALF;
2143 } else if (FloatValue == 1.0) {
2144 ImmReg = AMDGPU::ONE;
2146 ImmValue = FPC->getValueAPF().bitcastToAPInt().getZExtValue();
2149 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src.getOperand(0));
2150 uint64_t Value = C->getZExtValue();
2152 ImmReg = AMDGPU::ZERO;
2153 } else if (Value == 1) {
2154 ImmReg = AMDGPU::ONE_INT;
2160 // Check that we aren't already using an immediate.
2161 // XXX: It's possible for an instruction to have more than one
2162 // immediate operand, but this is not supported yet.
2163 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
2166 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Imm);
2168 if (C->getZExtValue())
2170 Imm = DAG.getTargetConstant(ImmValue, SDLoc(ParentNode), MVT::i32);
2172 Src = DAG.getRegister(ImmReg, MVT::i32);
2181 /// \brief Fold the instructions after selecting them
2182 SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node,
2183 SelectionDAG &DAG) const {
2184 const R600InstrInfo *TII =
2185 static_cast<const R600InstrInfo *>(DAG.getSubtarget().getInstrInfo());
2186 if (!Node->isMachineOpcode())
2188 unsigned Opcode = Node->getMachineOpcode();
2191 std::vector<SDValue> Ops(Node->op_begin(), Node->op_end());
2193 if (Opcode == AMDGPU::DOT_4) {
2194 int OperandIdx[] = {
2195 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
2196 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
2197 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
2198 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
2199 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
2200 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
2201 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
2202 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
2205 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_X),
2206 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Y),
2207 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Z),
2208 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_W),
2209 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_X),
2210 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Y),
2211 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Z),
2212 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_W)
2215 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_X),
2216 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Y),
2217 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Z),
2218 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_W),
2219 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_X),
2220 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Y),
2221 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Z),
2222 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_W)
2224 for (unsigned i = 0; i < 8; i++) {
2225 if (OperandIdx[i] < 0)
2227 SDValue &Src = Ops[OperandIdx[i] - 1];
2228 SDValue &Neg = Ops[NegIdx[i] - 1];
2229 SDValue &Abs = Ops[AbsIdx[i] - 1];
2230 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2231 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2234 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2235 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, FakeOp, DAG))
2236 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2238 } else if (Opcode == AMDGPU::REG_SEQUENCE) {
2239 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) {
2240 SDValue &Src = Ops[i];
2241 if (FoldOperand(Node, i, Src, FakeOp, FakeOp, FakeOp, FakeOp, DAG))
2242 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
2244 } else if (Opcode == AMDGPU::CLAMP_R600) {
2245 SDValue Src = Node->getOperand(0);
2246 if (!Src.isMachineOpcode() ||
2247 !TII->hasInstrModifiers(Src.getMachineOpcode()))
2249 int ClampIdx = TII->getOperandIdx(Src.getMachineOpcode(),
2250 AMDGPU::OpName::clamp);
2254 std::vector<SDValue> Ops(Src->op_begin(), Src->op_end());
2255 Ops[ClampIdx - 1] = DAG.getTargetConstant(1, DL, MVT::i32);
2256 return DAG.getMachineNode(Src.getMachineOpcode(), DL,
2257 Node->getVTList(), Ops);
2259 if (!TII->hasInstrModifiers(Opcode))
2261 int OperandIdx[] = {
2262 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
2263 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
2264 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2)
2267 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg),
2268 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg),
2269 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2_neg)
2272 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs),
2273 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs),
2276 for (unsigned i = 0; i < 3; i++) {
2277 if (OperandIdx[i] < 0)
2279 SDValue &Src = Ops[OperandIdx[i] - 1];
2280 SDValue &Neg = Ops[NegIdx[i] - 1];
2282 SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
2283 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2284 int SelIdx = TII->getSelIdx(Opcode, OperandIdx[i]);
2285 int ImmIdx = TII->getOperandIdx(Opcode, AMDGPU::OpName::literal);
2290 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2291 SDValue &Imm = Ops[ImmIdx];
2292 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG))
2293 return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);