1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for R600InstrInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_R600_R600INSTRINFO_H
16 #define LLVM_LIB_TARGET_R600_R600INSTRINFO_H
18 #include "AMDGPUInstrInfo.h"
19 #include "R600Defines.h"
20 #include "R600RegisterInfo.h"
25 class AMDGPUTargetMachine;
28 class MachineFunction;
30 class MachineInstrBuilder;
32 class R600InstrInfo : public AMDGPUInstrInfo {
34 const R600RegisterInfo RI;
36 std::vector<std::pair<int, unsigned> >
37 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
40 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
41 MachineBasicBlock::iterator I,
42 unsigned ValueReg, unsigned Address,
44 unsigned AddrChan) const;
46 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
47 MachineBasicBlock::iterator I,
48 unsigned ValueReg, unsigned Address,
50 unsigned AddrChan) const;
53 ALU_VEC_012_SCL_210 = 0,
61 explicit R600InstrInfo(const AMDGPUSubtarget &st);
63 const R600RegisterInfo &getRegisterInfo() const override;
64 void copyPhysReg(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator MI, DebugLoc DL,
66 unsigned DestReg, unsigned SrcReg,
67 bool KillSrc) const override;
68 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator MBBI) const override;
71 bool isTrig(const MachineInstr &MI) const;
72 bool isPlaceHolderOpcode(unsigned opcode) const;
73 bool isReductionOp(unsigned opcode) const;
74 bool isCubeOp(unsigned opcode) const;
76 /// \returns true if this \p Opcode represents an ALU instruction.
77 bool isALUInstr(unsigned Opcode) const;
78 bool hasInstrModifiers(unsigned Opcode) const;
79 bool isLDSInstr(unsigned Opcode) const;
80 bool isLDSNoRetInstr(unsigned Opcode) const;
81 bool isLDSRetInstr(unsigned Opcode) const;
83 /// \returns true if this \p Opcode represents an ALU instruction or an
84 /// instruction that will be lowered in ExpandSpecialInstrs Pass.
85 bool canBeConsideredALU(const MachineInstr *MI) const;
87 bool isTransOnly(unsigned Opcode) const;
88 bool isTransOnly(const MachineInstr *MI) const;
89 bool isVectorOnly(unsigned Opcode) const;
90 bool isVectorOnly(const MachineInstr *MI) const;
91 bool isExport(unsigned Opcode) const;
93 bool usesVertexCache(unsigned Opcode) const;
94 bool usesVertexCache(const MachineInstr *MI) const;
95 bool usesTextureCache(unsigned Opcode) const;
96 bool usesTextureCache(const MachineInstr *MI) const;
98 bool mustBeLastInClause(unsigned Opcode) const;
99 bool usesAddressRegister(MachineInstr *MI) const;
100 bool definesAddressRegister(MachineInstr *MI) const;
101 bool readsLDSSrcReg(const MachineInstr *MI) const;
103 /// \returns The operand index for the given source number. Legal values
104 /// for SrcNum are 0, 1, and 2.
105 int getSrcIdx(unsigned Opcode, unsigned SrcNum) const;
106 /// \returns The operand Index for the Sel operand given an index to one
107 /// of the instruction's src operands.
108 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
110 /// \returns a pair for each src of an ALU instructions.
111 /// The first member of a pair is the register id.
112 /// If register is ALU_CONST, second member is SEL.
113 /// If register is ALU_LITERAL, second member is IMM.
114 /// Otherwise, second member value is undefined.
115 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
116 getSrcs(MachineInstr *MI) const;
118 unsigned isLegalUpTo(
119 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
120 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
121 const std::vector<std::pair<int, unsigned> > &TransSrcs,
122 R600InstrInfo::BankSwizzle TransSwz) const;
124 bool FindSwizzleForVectorSlot(
125 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
126 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
127 const std::vector<std::pair<int, unsigned> > &TransSrcs,
128 R600InstrInfo::BankSwizzle TransSwz) const;
130 /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
131 /// returns true and the first (in lexical order) BankSwizzle affectation
132 /// starting from the one already provided in the Instruction Group MIs that
133 /// fits Read Port limitations in BS if available. Otherwise returns false
134 /// and undefined content in BS.
135 /// isLastAluTrans should be set if the last Alu of MIs will be executed on
136 /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
137 /// apply to the last instruction.
138 /// PV holds GPR to PV registers in the Instruction Group MIs.
139 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
140 const DenseMap<unsigned, unsigned> &PV,
141 std::vector<BankSwizzle> &BS,
142 bool isLastAluTrans) const;
144 /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
145 /// from KCache bank on R700+. This function check if MI set in input meet
147 bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
148 /// Same but using const index set instead of MI set.
149 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
151 /// \brief Vector instructions are instructions that must fill all
152 /// instruction slots within an instruction group.
153 bool isVector(const MachineInstr &MI) const;
155 bool isMov(unsigned Opcode) const override;
158 CreateTargetScheduleState(const TargetSubtargetInfo &) const override;
160 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
162 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
163 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override;
165 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
166 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
167 DebugLoc DL) const override;
169 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
171 bool isPredicated(const MachineInstr *MI) const override;
173 bool isPredicable(MachineInstr *MI) const override;
176 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
177 BranchProbability Probability) const override;
179 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
180 unsigned ExtraPredCycles,
181 BranchProbability Probability) const override ;
184 isProfitableToIfCvt(MachineBasicBlock &TMBB,
185 unsigned NumTCycles, unsigned ExtraTCycles,
186 MachineBasicBlock &FMBB,
187 unsigned NumFCycles, unsigned ExtraFCycles,
188 BranchProbability Probability) const override;
190 bool DefinesPredicate(MachineInstr *MI,
191 std::vector<MachineOperand> &Pred) const override;
193 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
194 ArrayRef<MachineOperand> Pred2) const override;
196 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
197 MachineBasicBlock &FMBB) const override;
199 bool PredicateInstruction(MachineInstr *MI,
200 ArrayRef<MachineOperand> Pred) const override;
202 unsigned int getPredicationCost(const MachineInstr *) const override;
204 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
205 const MachineInstr *MI,
206 unsigned *PredCost = nullptr) const override;
208 int getInstrLatency(const InstrItineraryData *ItinData,
209 SDNode *Node) const override { return 1;}
211 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
213 /// \brief Reserve the registers that may be accesed using indirect addressing.
214 void reserveIndirectRegisters(BitVector &Reserved,
215 const MachineFunction &MF) const;
217 unsigned calculateIndirectAddress(unsigned RegIndex,
218 unsigned Channel) const override;
220 const TargetRegisterClass *getIndirectAddrRegClass() const override;
222 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
223 MachineBasicBlock::iterator I,
224 unsigned ValueReg, unsigned Address,
225 unsigned OffsetReg) const override;
227 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
228 MachineBasicBlock::iterator I,
229 unsigned ValueReg, unsigned Address,
230 unsigned OffsetReg) const override;
232 unsigned getMaxAlusPerClause() const;
234 ///buildDefaultInstruction - This function returns a MachineInstr with
235 /// all the instruction modifiers initialized to their default values.
236 /// You can use this function to avoid manually specifying each instruction
237 /// modifier operand when building a new instruction.
239 /// \returns a MachineInstr with all the instruction modifiers initialized
240 /// to their default values.
241 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
242 MachineBasicBlock::iterator I,
246 unsigned Src1Reg = 0) const;
248 MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
251 unsigned DstReg) const;
253 MachineInstr *buildMovImm(MachineBasicBlock &BB,
254 MachineBasicBlock::iterator I,
258 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
259 MachineBasicBlock::iterator I,
260 unsigned DstReg, unsigned SrcReg) const override;
262 /// \brief Get the index of Op in the MachineInstr.
264 /// \returns -1 if the Instruction does not contain the specified \p Op.
265 int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
267 /// \brief Get the index of \p Op for the given Opcode.
269 /// \returns -1 if the Instruction does not contain the specified \p Op.
270 int getOperandIdx(unsigned Opcode, unsigned Op) const;
272 /// \brief Helper function for setting instruction flag values.
273 void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
275 /// \returns true if this instruction has an operand for storing target flags.
276 bool hasFlagOperand(const MachineInstr &MI) const;
278 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
279 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
281 ///\brief Determine if the specified \p Flag is set on this \p Operand.
282 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
284 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
285 /// \param Flag The flag being set.
287 /// \returns the operand containing the flags for this instruction.
288 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
289 unsigned Flag = 0) const;
291 /// \brief Clear the specified flag on the instruction.
292 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
297 int getLDSNoRetOp(uint16_t Opcode);
299 } //End namespace AMDGPU
301 } // End llvm namespace