1 //===-- SIFixControlFlowLiveIntervals.cpp - Fix CF live intervals ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Spilling of EXEC masks used for control flow messes up control flow
12 /// lowering, so mark all live intervals associated with CF instructions as
15 //===----------------------------------------------------------------------===//
18 #include "SIInstrInfo.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #define DEBUG_TYPE "si-fix-cf-live-intervals"
29 class SIFixControlFlowLiveIntervals : public MachineFunctionPass {
34 SIFixControlFlowLiveIntervals() : MachineFunctionPass(ID) {
35 initializeSIFixControlFlowLiveIntervalsPass(*PassRegistry::getPassRegistry());
38 bool runOnMachineFunction(MachineFunction &MF) override;
40 const char *getPassName() const override {
41 return "SI Fix CF Live Intervals";
44 void getAnalysisUsage(AnalysisUsage &AU) const override {
45 AU.addRequired<LiveIntervals>();
47 MachineFunctionPass::getAnalysisUsage(AU);
51 } // End anonymous namespace.
53 INITIALIZE_PASS_BEGIN(SIFixControlFlowLiveIntervals, DEBUG_TYPE,
54 "SI Fix CF Live Intervals", false, false)
55 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
56 INITIALIZE_PASS_END(SIFixControlFlowLiveIntervals, DEBUG_TYPE,
57 "SI Fix CF Live Intervals", false, false)
59 char SIFixControlFlowLiveIntervals::ID = 0;
61 char &llvm::SIFixControlFlowLiveIntervalsID = SIFixControlFlowLiveIntervals::ID;
63 FunctionPass *llvm::createSIFixControlFlowLiveIntervalsPass() {
64 return new SIFixControlFlowLiveIntervals();
67 bool SIFixControlFlowLiveIntervals::runOnMachineFunction(MachineFunction &MF) {
68 LiveIntervals *LIS = &getAnalysis<LiveIntervals>();
70 for (const MachineBasicBlock &MBB : MF) {
71 for (const MachineInstr &MI : MBB) {
72 switch (MI.getOpcode()) {
75 case AMDGPU::SI_BREAK:
76 case AMDGPU::SI_IF_BREAK:
77 case AMDGPU::SI_ELSE_BREAK:
78 case AMDGPU::SI_END_CF: {
79 unsigned Reg = MI.getOperand(0).getReg();
80 LIS->getInterval(Reg).markNotSpillable();