1 //===-- SIFixSGPRLiveRanges.cpp - Fix SGPR live ranges ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// \file SALU instructions ignore the execution mask, so we need to modify the
11 /// live ranges of the registers they define in some cases.
13 /// The main case we need to handle is when a def is used in one side of a
14 /// branch and not another. For example:
25 /// Here we need the register allocator to avoid assigning any of the defs
26 /// inside of the IF to the same register as %def. In traditional live
27 /// interval analysis %def is not live inside the IF branch, however, since
28 /// SALU instructions inside of IF will be executed even if the branch is not
29 /// taken, there is the chance that one of the instructions will overwrite the
30 /// value of %def, so the use in ELSE will see the wrong value.
32 /// The strategy we use for solving this is to add an extra use after the ENDIF:
44 /// Adding this use will make the def live throughout the IF branch, which is
48 #include "SIInstrInfo.h"
49 #include "SIRegisterInfo.h"
50 #include "llvm/ADT/DepthFirstIterator.h"
51 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
52 #include "llvm/CodeGen/LiveVariables.h"
53 #include "llvm/CodeGen/MachineFunctionPass.h"
54 #include "llvm/CodeGen/MachineInstrBuilder.h"
55 #include "llvm/CodeGen/MachinePostDominators.h"
56 #include "llvm/CodeGen/MachineRegisterInfo.h"
57 #include "llvm/Support/Debug.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetMachine.h"
63 #define DEBUG_TYPE "si-fix-sgpr-live-ranges"
67 class SIFixSGPRLiveRanges : public MachineFunctionPass {
72 SIFixSGPRLiveRanges() : MachineFunctionPass(ID) {
73 initializeSIFixSGPRLiveRangesPass(*PassRegistry::getPassRegistry());
76 bool runOnMachineFunction(MachineFunction &MF) override;
78 const char *getPassName() const override {
79 return "SI Fix SGPR live ranges";
82 void getAnalysisUsage(AnalysisUsage &AU) const override {
83 AU.addRequired<LiveIntervals>();
84 AU.addRequired<MachinePostDominatorTree>();
87 //AU.addPreserved<SlotIndexes>(); // XXX - This might be OK
88 AU.addPreserved<LiveIntervals>();
90 MachineFunctionPass::getAnalysisUsage(AU);
94 } // End anonymous namespace.
96 INITIALIZE_PASS_BEGIN(SIFixSGPRLiveRanges, DEBUG_TYPE,
97 "SI Fix SGPR Live Ranges", false, false)
98 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
99 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
100 INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree)
101 INITIALIZE_PASS_END(SIFixSGPRLiveRanges, DEBUG_TYPE,
102 "SI Fix SGPR Live Ranges", false, false)
104 char SIFixSGPRLiveRanges::ID = 0;
106 char &llvm::SIFixSGPRLiveRangesID = SIFixSGPRLiveRanges::ID;
108 FunctionPass *llvm::createSIFixSGPRLiveRangesPass() {
109 return new SIFixSGPRLiveRanges();
112 bool SIFixSGPRLiveRanges::runOnMachineFunction(MachineFunction &MF) {
113 MachineRegisterInfo &MRI = MF.getRegInfo();
114 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
115 const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
116 MF.getSubtarget().getRegisterInfo());
117 bool MadeChange = false;
119 MachinePostDominatorTree *PDT = &getAnalysis<MachinePostDominatorTree>();
120 std::vector<std::pair<unsigned, LiveRange *>> SGPRLiveRanges;
122 LiveIntervals *LIS = &getAnalysis<LiveIntervals>();
123 LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>();
124 MachineBasicBlock *Entry = MF.begin();
126 // Use a depth first order so that in SSA, we encounter all defs before
127 // uses. Once the defs of the block have been found, attempt to insert
128 // SGPR_USE instructions in successor blocks if required.
129 for (MachineBasicBlock *MBB : depth_first(Entry)) {
130 for (const MachineInstr &MI : *MBB) {
131 for (const MachineOperand &MO : MI.defs()) {
134 unsigned Def = MO.getReg();
135 if (TargetRegisterInfo::isVirtualRegister(Def)) {
136 if (TRI->isSGPRClass(MRI.getRegClass(Def))) {
137 // Only consider defs that are live outs. We don't care about def /
138 // use within the same block.
139 LiveRange &LR = LIS->getInterval(Def);
140 if (LIS->isLiveOutOfMBB(LR, MBB))
141 SGPRLiveRanges.push_back(std::make_pair(Def, &LR));
143 } else if (TRI->isSGPRClass(TRI->getPhysRegClass(Def))) {
144 SGPRLiveRanges.push_back(std::make_pair(Def, &LIS->getRegUnit(Def)));
149 if (MBB->succ_size() < 2)
152 // We have structured control flow, so the number of successors should be
154 assert(MBB->succ_size() == 2);
155 MachineBasicBlock *SuccA = *MBB->succ_begin();
156 MachineBasicBlock *SuccB = *(++MBB->succ_begin());
157 MachineBasicBlock *NCD = PDT->findNearestCommonDominator(SuccA, SuccB);
162 MachineBasicBlock::iterator NCDTerm = NCD->getFirstTerminator();
164 if (NCDTerm != NCD->end() && NCDTerm->getOpcode() == AMDGPU::SI_ELSE) {
165 assert(NCD->succ_size() == 2);
166 // We want to make sure we insert the Use after the ENDIF, not after
168 NCD = PDT->findNearestCommonDominator(*NCD->succ_begin(),
169 *(++NCD->succ_begin()));
172 for (std::pair<unsigned, LiveRange*> RegLR : SGPRLiveRanges) {
173 unsigned Reg = RegLR.first;
174 LiveRange *LR = RegLR.second;
176 // FIXME: We could be smarter here. If the register is Live-In to one
177 // block, but the other doesn't have any SGPR defs, then there won't be a
178 // conflict. Also, if the branch condition is uniform then there will be
180 bool LiveInToA = LIS->isLiveInToMBB(*LR, SuccA);
181 bool LiveInToB = LIS->isLiveInToMBB(*LR, SuccB);
183 if (!LiveInToA && !LiveInToB) {
184 DEBUG(dbgs() << PrintReg(Reg, TRI, 0)
185 << " is live into neither successor\n");
189 if (LiveInToA && LiveInToB) {
190 DEBUG(dbgs() << PrintReg(Reg, TRI, 0)
191 << " is live into both successors\n");
195 // This interval is live in to one successor, but not the other, so
196 // we need to update its range so it is live in to both.
197 DEBUG(dbgs() << "Possible SGPR conflict detected for "
198 << PrintReg(Reg, TRI, 0) << " in " << *LR
199 << " BB#" << SuccA->getNumber() << ", BB#"
200 << SuccB->getNumber()
201 << " with NCD = BB#" << NCD->getNumber() << '\n');
203 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
204 "Not expecting to extend live range of physreg");
206 // FIXME: Need to figure out how to update LiveRange here so this pass
207 // will be able to preserve LiveInterval analysis.
208 MachineInstr *NCDSGPRUse =
209 BuildMI(*NCD, NCD->getFirstNonPHI(), DebugLoc(),
210 TII->get(AMDGPU::SGPR_USE))
211 .addReg(Reg, RegState::Implicit);
215 SlotIndex SI = LIS->InsertMachineInstrInMaps(NCDSGPRUse);
216 LIS->extendToIndices(*LR, SI.getRegSlot());
219 // TODO: This won't work post-SSA
220 LV->HandleVirtRegUse(Reg, NCD, NCDSGPRUse);
223 DEBUG(NCDSGPRUse->dump());