1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for SI
13 //===----------------------------------------------------------------------===//
17 #define _USE_MATH_DEFINES
21 #include "SIISelLowering.h"
23 #include "AMDGPUDiagnosticInfoUnsupported.h"
24 #include "AMDGPUIntrinsicInfo.h"
25 #include "AMDGPUSubtarget.h"
26 #include "SIInstrInfo.h"
27 #include "SIMachineFunctionInfo.h"
28 #include "SIRegisterInfo.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/CodeGen/CallingConvLower.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/IR/Function.h"
35 #include "llvm/ADT/SmallString.h"
39 SITargetLowering::SITargetLowering(TargetMachine &TM,
40 const AMDGPUSubtarget &STI)
41 : AMDGPUTargetLowering(TM, STI) {
42 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
43 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
45 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
46 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
48 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
49 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
51 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
52 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
53 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
55 addRegisterClass(MVT::v2i64, &AMDGPU::SReg_128RegClass);
56 addRegisterClass(MVT::v2f64, &AMDGPU::SReg_128RegClass);
58 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
59 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
61 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
62 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
64 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
65 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
67 computeRegisterProperties(STI.getRegisterInfo());
69 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
70 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
71 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
72 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
74 setOperationAction(ISD::ADD, MVT::i32, Legal);
75 setOperationAction(ISD::ADDC, MVT::i32, Legal);
76 setOperationAction(ISD::ADDE, MVT::i32, Legal);
77 setOperationAction(ISD::SUBC, MVT::i32, Legal);
78 setOperationAction(ISD::SUBE, MVT::i32, Legal);
80 setOperationAction(ISD::FSIN, MVT::f32, Custom);
81 setOperationAction(ISD::FCOS, MVT::f32, Custom);
83 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
84 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
86 // We need to custom lower vector stores from local memory
87 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
88 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
89 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
91 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
92 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
94 setOperationAction(ISD::STORE, MVT::i1, Custom);
95 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
97 setOperationAction(ISD::SELECT, MVT::i64, Custom);
98 setOperationAction(ISD::SELECT, MVT::f64, Promote);
99 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
101 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
102 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
103 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
104 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
106 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
107 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
109 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
110 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
114 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
125 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
127 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
128 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
129 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
130 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
132 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
133 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
135 for (MVT VT : MVT::integer_valuetypes()) {
139 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal);
141 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal);
142 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
144 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
145 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
146 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
147 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
149 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
150 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal);
151 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal);
152 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
155 for (MVT VT : MVT::integer_vector_valuetypes()) {
156 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i16, Expand);
157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v16i16, Expand);
160 for (MVT VT : MVT::fp_valuetypes())
161 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
163 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
164 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
166 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
167 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
168 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand);
169 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
172 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand);
174 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
175 setTruncStoreAction(MVT::v2f64, MVT::v2f16, Expand);
177 setOperationAction(ISD::LOAD, MVT::i1, Custom);
179 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
180 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32);
182 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
183 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32);
185 setOperationAction(ISD::ConstantPool, MVT::v2i64, Expand);
187 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
188 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
189 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
191 // These should use UDIVREM, so set them to expand
192 setOperationAction(ISD::UDIV, MVT::i64, Expand);
193 setOperationAction(ISD::UREM, MVT::i64, Expand);
195 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
196 setOperationAction(ISD::SELECT, MVT::i1, Promote);
198 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand);
201 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
203 // We only support LOAD/STORE and vector manipulation ops for vectors
204 // with > 4 elements.
205 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64}) {
206 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
210 case ISD::BUILD_VECTOR:
212 case ISD::EXTRACT_VECTOR_ELT:
213 case ISD::INSERT_VECTOR_ELT:
214 case ISD::INSERT_SUBVECTOR:
215 case ISD::EXTRACT_SUBVECTOR:
216 case ISD::SCALAR_TO_VECTOR:
218 case ISD::CONCAT_VECTORS:
219 setOperationAction(Op, VT, Custom);
222 setOperationAction(Op, VT, Expand);
228 // Most operations are naturally 32-bit vector operations. We only support
229 // load and store of i64 vectors, so promote v2i64 vector operations to v4i32.
230 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
231 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
232 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
234 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
235 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
237 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
238 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
240 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
241 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
244 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
245 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
246 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
247 setOperationAction(ISD::FRINT, MVT::f64, Legal);
250 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
251 setOperationAction(ISD::FDIV, MVT::f32, Custom);
252 setOperationAction(ISD::FDIV, MVT::f64, Custom);
254 setTargetDAGCombine(ISD::FADD);
255 setTargetDAGCombine(ISD::FSUB);
256 setTargetDAGCombine(ISD::FMINNUM);
257 setTargetDAGCombine(ISD::FMAXNUM);
258 setTargetDAGCombine(ISD::SMIN);
259 setTargetDAGCombine(ISD::SMAX);
260 setTargetDAGCombine(ISD::UMIN);
261 setTargetDAGCombine(ISD::UMAX);
262 setTargetDAGCombine(ISD::SETCC);
263 setTargetDAGCombine(ISD::AND);
264 setTargetDAGCombine(ISD::OR);
265 setTargetDAGCombine(ISD::UINT_TO_FP);
267 // All memory operations. Some folding on the pointer operand is done to help
268 // matching the constant offsets in the addressing modes.
269 setTargetDAGCombine(ISD::LOAD);
270 setTargetDAGCombine(ISD::STORE);
271 setTargetDAGCombine(ISD::ATOMIC_LOAD);
272 setTargetDAGCombine(ISD::ATOMIC_STORE);
273 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
274 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
275 setTargetDAGCombine(ISD::ATOMIC_SWAP);
276 setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
277 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
278 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
279 setTargetDAGCombine(ISD::ATOMIC_LOAD_OR);
280 setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
281 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND);
282 setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN);
283 setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX);
284 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN);
285 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX);
287 setSchedulingPreference(Sched::RegPressure);
290 //===----------------------------------------------------------------------===//
291 // TargetLowering queries
292 //===----------------------------------------------------------------------===//
294 bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,
296 // SI has some legal vector types, but no legal vector operations. Say no
297 // shuffles are legal in order to prefer scalarizing some vector operations.
301 bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
302 // Flat instructions do not have offsets, and only have the register
304 return AM.BaseOffs == 0 && (AM.Scale == 0 || AM.Scale == 1);
307 bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
308 // MUBUF / MTBUF instructions have a 12-bit unsigned byte offset, and
309 // additionally can do r + r + i with addr64. 32-bit has more addressing
310 // mode options. Depending on the resource constant, it can also do
311 // (i64 r0) + (i32 r1) * (i14 i).
313 // Private arrays end up using a scratch buffer most of the time, so also
314 // assume those use MUBUF instructions. Scratch loads / stores are currently
315 // implemented as mubuf instructions with offen bit set, so slightly
316 // different than the normal addr64.
317 if (!isUInt<12>(AM.BaseOffs))
320 // FIXME: Since we can split immediate into soffset and immediate offset,
321 // would it make sense to allow any immediate?
324 case 0: // r + i or just i, depending on HasBaseReg.
327 return true; // We have r + r or r + i.
334 // Allow 2 * r as r + r
335 // Or 2 * r + i is allowed as r + r + i.
337 default: // Don't allow n * r
342 bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
343 const AddrMode &AM, Type *Ty,
345 // No global is ever allowed as a base.
350 case AMDGPUAS::GLOBAL_ADDRESS: {
351 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
352 // Assume the we will use FLAT for all global memory accesses
354 // FIXME: This assumption is currently wrong. On VI we still use
355 // MUBUF instructions for the r + i addressing mode. As currently
356 // implemented, the MUBUF instructions only work on buffer < 4GB.
357 // It may be possible to support > 4GB buffers with MUBUF instructions,
358 // by setting the stride value in the resource descriptor which would
359 // increase the size limit to (stride * 4GB). However, this is risky,
360 // because it has never been validated.
361 return isLegalFlatAddressingMode(AM);
364 return isLegalMUBUFAddressingMode(AM);
366 case AMDGPUAS::CONSTANT_ADDRESS: {
367 // If the offset isn't a multiple of 4, it probably isn't going to be
368 // correctly aligned.
369 if (AM.BaseOffs % 4 != 0)
370 return isLegalMUBUFAddressingMode(AM);
372 // There are no SMRD extloads, so if we have to do a small type access we
373 // will use a MUBUF load.
374 // FIXME?: We also need to do this if unaligned, but we don't know the
376 if (DL.getTypeStoreSize(Ty) < 4)
377 return isLegalMUBUFAddressingMode(AM);
379 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
380 // SMRD instructions have an 8-bit, dword offset on SI.
381 if (!isUInt<8>(AM.BaseOffs / 4))
383 } else if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS) {
384 // On CI+, this can also be a 32-bit literal constant offset. If it fits
385 // in 8-bits, it can use a smaller encoding.
386 if (!isUInt<32>(AM.BaseOffs / 4))
388 } else if (Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS) {
389 // On VI, these use the SMEM format and the offset is 20-bit in bytes.
390 if (!isUInt<20>(AM.BaseOffs))
393 llvm_unreachable("unhandled generation");
395 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
398 if (AM.Scale == 1 && AM.HasBaseReg)
404 case AMDGPUAS::PRIVATE_ADDRESS:
405 case AMDGPUAS::UNKNOWN_ADDRESS_SPACE:
406 return isLegalMUBUFAddressingMode(AM);
408 case AMDGPUAS::LOCAL_ADDRESS:
409 case AMDGPUAS::REGION_ADDRESS: {
410 // Basic, single offset DS instructions allow a 16-bit unsigned immediate
412 // XXX - If doing a 4-byte aligned 8-byte type access, we effectively have
413 // an 8-bit dword offset but we don't know the alignment here.
414 if (!isUInt<16>(AM.BaseOffs))
417 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
420 if (AM.Scale == 1 && AM.HasBaseReg)
425 case AMDGPUAS::FLAT_ADDRESS:
426 return isLegalFlatAddressingMode(AM);
429 llvm_unreachable("unhandled address space");
433 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
436 bool *IsFast) const {
440 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
441 // which isn't a simple VT.
442 if (!VT.isSimple() || VT == MVT::Other)
445 // TODO - CI+ supports unaligned memory accesses, but this requires driver
448 // XXX - The only mention I see of this in the ISA manual is for LDS direct
449 // reads the "byte address and must be dword aligned". Is it also true for the
450 // normal loads and stores?
451 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS) {
452 // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
453 // aligned, 8 byte access in a single operation using ds_read2/write2_b32
454 // with adjacent offsets.
455 bool AlignedBy4 = (Align % 4 == 0);
457 *IsFast = AlignedBy4;
461 // Smaller than dword value must be aligned.
462 // FIXME: This should be allowed on CI+
463 if (VT.bitsLT(MVT::i32))
466 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
467 // byte-address are ignored, thus forcing Dword alignment.
468 // This applies to private, global, and constant memory.
472 return VT.bitsGT(MVT::i32) && Align % 4 == 0;
475 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
476 unsigned SrcAlign, bool IsMemset,
479 MachineFunction &MF) const {
480 // FIXME: Should account for address space here.
482 // The default fallback uses the private pointer size as a guess for a type to
483 // use. Make sure we switch these to 64-bit accesses.
485 if (Size >= 16 && DstAlign >= 4) // XXX: Should only do for global
488 if (Size >= 8 && DstAlign >= 4)
495 static bool isFlatGlobalAddrSpace(unsigned AS) {
496 return AS == AMDGPUAS::GLOBAL_ADDRESS ||
497 AS == AMDGPUAS::FLAT_ADDRESS ||
498 AS == AMDGPUAS::CONSTANT_ADDRESS;
501 bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
502 unsigned DestAS) const {
503 return isFlatGlobalAddrSpace(SrcAS) && isFlatGlobalAddrSpace(DestAS);
507 bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
508 const MemSDNode *MemNode = cast<MemSDNode>(N);
509 const Value *Ptr = MemNode->getMemOperand()->getValue();
511 // UndefValue means this is a load of a kernel input. These are uniform.
512 // Sometimes LDS instructions have constant pointers
513 if (isa<UndefValue>(Ptr) || isa<Argument>(Ptr) || isa<Constant>(Ptr) ||
514 isa<GlobalValue>(Ptr))
517 const Instruction *I = dyn_cast_or_null<Instruction>(Ptr);
518 return I && I->getMetadata("amdgpu.uniform");
521 TargetLoweringBase::LegalizeTypeAction
522 SITargetLowering::getPreferredVectorAction(EVT VT) const {
523 if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
524 return TypeSplitVector;
526 return TargetLoweringBase::getPreferredVectorAction(VT);
529 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
531 const SIInstrInfo *TII =
532 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
533 return TII->isInlineConstant(Imm);
536 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
537 SDLoc SL, SDValue Chain,
538 unsigned Offset, bool Signed) const {
539 const DataLayout &DL = DAG.getDataLayout();
540 MachineFunction &MF = DAG.getMachineFunction();
541 const SIRegisterInfo *TRI =
542 static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
543 unsigned InputPtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::KERNARG_SEGMENT_PTR);
545 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
547 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
548 MVT PtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
549 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
550 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
551 MRI.getLiveInVirtReg(InputPtrReg), PtrVT);
552 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
553 DAG.getConstant(Offset, SL, PtrVT));
554 SDValue PtrOffset = DAG.getUNDEF(PtrVT);
555 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
557 unsigned Align = DL.getABITypeAlignment(Ty);
559 ISD::LoadExtType ExtTy = Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
560 if (MemVT.isFloatingPoint())
561 ExtTy = ISD::EXTLOAD;
563 return DAG.getLoad(ISD::UNINDEXED, ExtTy,
564 VT, SL, Chain, Ptr, PtrOffset, PtrInfo, MemVT,
566 true, // isNonTemporal
571 SDValue SITargetLowering::LowerFormalArguments(
572 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
573 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
574 SmallVectorImpl<SDValue> &InVals) const {
575 const SIRegisterInfo *TRI =
576 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
578 MachineFunction &MF = DAG.getMachineFunction();
579 FunctionType *FType = MF.getFunction()->getFunctionType();
580 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
581 const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
583 if (Subtarget->isAmdHsaOS() && Info->getShaderType() != ShaderType::COMPUTE) {
584 const Function *Fn = MF.getFunction();
585 DiagnosticInfoUnsupported NoGraphicsHSA(*Fn, "non-compute shaders with HSA");
586 DAG.getContext()->diagnose(NoGraphicsHSA);
590 // FIXME: We currently assume all calling conventions are kernels.
592 SmallVector<ISD::InputArg, 16> Splits;
593 BitVector Skipped(Ins.size());
595 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
596 const ISD::InputArg &Arg = Ins[i];
598 // First check if it's a PS input addr
599 if (Info->getShaderType() == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
600 !Arg.Flags.isByVal() && PSInputNum <= 15) {
602 if (!Arg.Used && !Info->isPSInputAllocated(PSInputNum)) {
603 // We can safely skip PS inputs
609 Info->markPSInputAllocated(PSInputNum);
611 Info->PSInputEna |= 1 << PSInputNum;
616 // Second split vertices into their elements
617 if (Info->getShaderType() != ShaderType::COMPUTE && Arg.VT.isVector()) {
618 ISD::InputArg NewArg = Arg;
619 NewArg.Flags.setSplit();
620 NewArg.VT = Arg.VT.getVectorElementType();
622 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
623 // three or five element vertex only needs three or five registers,
624 // NOT four or eight.
625 Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
626 unsigned NumElements = ParamType->getVectorNumElements();
628 for (unsigned j = 0; j != NumElements; ++j) {
629 Splits.push_back(NewArg);
630 NewArg.PartOffset += NewArg.VT.getStoreSize();
633 } else if (Info->getShaderType() != ShaderType::COMPUTE) {
634 Splits.push_back(Arg);
638 SmallVector<CCValAssign, 16> ArgLocs;
639 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
642 // At least one interpolation mode must be enabled or else the GPU will hang.
644 // Check PSInputAddr instead of PSInputEna. The idea is that if the user set
645 // PSInputAddr, the user wants to enable some bits after the compilation
646 // based on run-time states. Since we can't know what the final PSInputEna
647 // will look like, so we shouldn't do anything here and the user should take
648 // responsibility for the correct programming.
649 if (Info->getShaderType() == ShaderType::PIXEL &&
650 (Info->getPSInputAddr() & 0x7F) == 0) {
651 CCInfo.AllocateReg(AMDGPU::VGPR0);
652 CCInfo.AllocateReg(AMDGPU::VGPR1);
653 Info->markPSInputAllocated(0);
654 Info->PSInputEna |= 1;
657 if (Info->getShaderType() == ShaderType::COMPUTE) {
658 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
662 // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
663 if (Info->hasPrivateSegmentBuffer()) {
664 unsigned PrivateSegmentBufferReg = Info->addPrivateSegmentBuffer(*TRI);
665 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SReg_128RegClass);
666 CCInfo.AllocateReg(PrivateSegmentBufferReg);
669 if (Info->hasDispatchPtr()) {
670 unsigned DispatchPtrReg = Info->addDispatchPtr(*TRI);
671 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SReg_64RegClass);
672 CCInfo.AllocateReg(DispatchPtrReg);
675 if (Info->hasKernargSegmentPtr()) {
676 unsigned InputPtrReg = Info->addKernargSegmentPtr(*TRI);
677 MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass);
678 CCInfo.AllocateReg(InputPtrReg);
681 AnalyzeFormalArguments(CCInfo, Splits);
683 SmallVector<SDValue, 16> Chains;
685 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
687 const ISD::InputArg &Arg = Ins[i];
689 InVals.push_back(DAG.getUNDEF(Arg.VT));
693 CCValAssign &VA = ArgLocs[ArgIdx++];
694 MVT VT = VA.getLocVT();
698 EVT MemVT = Splits[i].VT;
699 const unsigned Offset = Subtarget->getExplicitKernelArgOffset() +
700 VA.getLocMemOffset();
701 // The first 36 bytes of the input buffer contains information about
702 // thread group and global sizes.
703 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, Chain,
704 Offset, Ins[i].Flags.isSExt());
705 Chains.push_back(Arg.getValue(1));
708 dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
709 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
710 ParamTy && ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
711 // On SI local pointers are just offsets into LDS, so they are always
712 // less than 16-bits. On CI and newer they could potentially be
713 // real pointers, so we can't guarantee their size.
714 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
715 DAG.getValueType(MVT::i16));
718 InVals.push_back(Arg);
719 Info->ABIArgOffset = Offset + MemVT.getStoreSize();
722 assert(VA.isRegLoc() && "Parameter must be in a register!");
724 unsigned Reg = VA.getLocReg();
726 if (VT == MVT::i64) {
727 // For now assume it is a pointer
728 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
729 &AMDGPU::SReg_64RegClass);
730 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
731 SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT);
732 InVals.push_back(Copy);
736 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
738 Reg = MF.addLiveIn(Reg, RC);
739 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
741 if (Arg.VT.isVector()) {
743 // Build a vector from the registers
744 Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
745 unsigned NumElements = ParamType->getVectorNumElements();
747 SmallVector<SDValue, 4> Regs;
749 for (unsigned j = 1; j != NumElements; ++j) {
750 Reg = ArgLocs[ArgIdx++].getLocReg();
751 Reg = MF.addLiveIn(Reg, RC);
753 SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT);
754 Regs.push_back(Copy);
757 // Fill up the missing vector elements
758 NumElements = Arg.VT.getVectorNumElements() - NumElements;
759 Regs.append(NumElements, DAG.getUNDEF(VT));
761 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
765 InVals.push_back(Val);
768 // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
769 // these from the dispatch pointer.
771 // Start adding system SGPRs.
772 if (Info->hasWorkGroupIDX()) {
773 unsigned Reg = Info->addWorkGroupIDX();
774 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
775 CCInfo.AllocateReg(Reg);
777 llvm_unreachable("work group id x is always enabled");
779 if (Info->hasWorkGroupIDY()) {
780 unsigned Reg = Info->addWorkGroupIDY();
781 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
782 CCInfo.AllocateReg(Reg);
785 if (Info->hasWorkGroupIDZ()) {
786 unsigned Reg = Info->addWorkGroupIDZ();
787 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
788 CCInfo.AllocateReg(Reg);
791 if (Info->hasWorkGroupInfo()) {
792 unsigned Reg = Info->addWorkGroupInfo();
793 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
794 CCInfo.AllocateReg(Reg);
797 if (Info->hasPrivateSegmentWaveByteOffset()) {
798 // Scratch wave offset passed in system SGPR.
799 unsigned PrivateSegmentWaveByteOffsetReg
800 = Info->addPrivateSegmentWaveByteOffset();
802 MF.addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
803 CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);
806 // Now that we've figured out where the scratch register inputs are, see if
807 // should reserve the arguments and use them directly.
809 bool HasStackObjects = MF.getFrameInfo()->hasStackObjects();
811 if (ST.isAmdHsaOS()) {
812 // TODO: Assume we will spill without optimizations.
813 if (HasStackObjects) {
814 // If we have stack objects, we unquestionably need the private buffer
815 // resource. For the HSA ABI, this will be the first 4 user SGPR
816 // inputs. We can reserve those and use them directly.
818 unsigned PrivateSegmentBufferReg = TRI->getPreloadedValue(
819 MF, SIRegisterInfo::PRIVATE_SEGMENT_BUFFER);
820 Info->setScratchRSrcReg(PrivateSegmentBufferReg);
822 unsigned PrivateSegmentWaveByteOffsetReg = TRI->getPreloadedValue(
823 MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
824 Info->setScratchWaveOffsetReg(PrivateSegmentWaveByteOffsetReg);
826 unsigned ReservedBufferReg
827 = TRI->reservedPrivateSegmentBufferReg(MF);
828 unsigned ReservedOffsetReg
829 = TRI->reservedPrivateSegmentWaveByteOffsetReg(MF);
831 // We tentatively reserve the last registers (skipping the last two
832 // which may contain VCC). After register allocation, we'll replace
833 // these with the ones immediately after those which were really
834 // allocated. In the prologue copies will be inserted from the argument
835 // to these reserved registers.
836 Info->setScratchRSrcReg(ReservedBufferReg);
837 Info->setScratchWaveOffsetReg(ReservedOffsetReg);
840 unsigned ReservedBufferReg = TRI->reservedPrivateSegmentBufferReg(MF);
842 // Without HSA, relocations are used for the scratch pointer and the
843 // buffer resource setup is always inserted in the prologue. Scratch wave
844 // offset is still in an input SGPR.
845 Info->setScratchRSrcReg(ReservedBufferReg);
847 if (HasStackObjects) {
848 unsigned ScratchWaveOffsetReg = TRI->getPreloadedValue(
849 MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
850 Info->setScratchWaveOffsetReg(ScratchWaveOffsetReg);
852 unsigned ReservedOffsetReg
853 = TRI->reservedPrivateSegmentWaveByteOffsetReg(MF);
854 Info->setScratchWaveOffsetReg(ReservedOffsetReg);
858 if (Info->hasWorkItemIDX()) {
859 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_X);
860 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
861 CCInfo.AllocateReg(Reg);
863 llvm_unreachable("workitem id x should always be enabled");
865 if (Info->hasWorkItemIDY()) {
866 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Y);
867 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
868 CCInfo.AllocateReg(Reg);
871 if (Info->hasWorkItemIDZ()) {
872 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Z);
873 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
874 CCInfo.AllocateReg(Reg);
880 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
883 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
884 MachineInstr * MI, MachineBasicBlock * BB) const {
886 switch (MI->getOpcode()) {
888 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
895 bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
896 // This currently forces unfolding various combinations of fsub into fma with
897 // free fneg'd operands. As long as we have fast FMA (controlled by
898 // isFMAFasterThanFMulAndFAdd), we should perform these.
900 // When fma is quarter rate, for f64 where add / sub are at best half rate,
901 // most of these combines appear to be cycle neutral but save on instruction
902 // count / code size.
906 EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
908 if (!VT.isVector()) {
911 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
914 MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT) const {
918 // Answering this is somewhat tricky and depends on the specific device which
919 // have different rates for fma or all f64 operations.
921 // v_fma_f64 and v_mul_f64 always take the same number of cycles as each other
922 // regardless of which device (although the number of cycles differs between
923 // devices), so it is always profitable for f64.
925 // v_fma_f32 takes 4 or 16 cycles depending on the device, so it is profitable
926 // only on full rate devices. Normally, we should prefer selecting v_mad_f32
927 // which we can always do even without fused FP ops since it returns the same
928 // result as the separate operations and since it is always full
929 // rate. Therefore, we lie and report that it is not faster for f32. v_mad_f32
930 // however does not support denormals, so we do report fma as faster if we have
931 // a fast fma device and require denormals.
933 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
934 VT = VT.getScalarType();
939 switch (VT.getSimpleVT().SimpleTy) {
941 // This is as fast on some subtargets. However, we always have full rate f32
942 // mad available which returns the same result as the separate operations
943 // which we should prefer over fma. We can't use this if we want to support
944 // denormals, so only report this in these cases.
945 return Subtarget->hasFP32Denormals() && Subtarget->hasFastFMAF32();
955 //===----------------------------------------------------------------------===//
956 // Custom DAG Lowering Operations
957 //===----------------------------------------------------------------------===//
959 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
960 switch (Op.getOpcode()) {
961 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
962 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
963 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
965 SDValue Result = LowerLOAD(Op, DAG);
966 assert((!Result.getNode() ||
967 Result.getNode()->getNumValues() == 2) &&
968 "Load should return a value and a chain");
974 return LowerTrig(Op, DAG);
975 case ISD::SELECT: return LowerSELECT(Op, DAG);
976 case ISD::FDIV: return LowerFDIV(Op, DAG);
977 case ISD::STORE: return LowerSTORE(Op, DAG);
978 case ISD::GlobalAddress: {
979 MachineFunction &MF = DAG.getMachineFunction();
980 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
981 return LowerGlobalAddress(MFI, Op, DAG);
983 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
984 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
989 /// \brief Helper function for LowerBRCOND
990 static SDNode *findUser(SDValue Value, unsigned Opcode) {
992 SDNode *Parent = Value.getNode();
993 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
996 if (I.getUse().get() != Value)
999 if (I->getOpcode() == Opcode)
1005 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
1008 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Op);
1009 unsigned FrameIndex = FINode->getIndex();
1011 // A FrameIndex node represents a 32-bit offset into scratch memory. If
1012 // the high bit of a frame index offset were to be set, this would mean
1013 // that it represented an offset of ~2GB * 64 = ~128GB from the start of the
1014 // scratch buffer, with 64 being the number of threads per wave.
1016 // If we know the machine uses less than 128GB of scratch, then we can
1017 // amrk the high bit of the FrameIndex node as known zero,
1018 // which is important, because it means in most situations we can
1019 // prove that values derived from FrameIndex nodes are non-negative.
1020 // This enables us to take advantage of more addressing modes when
1021 // accessing scratch buffers, since for scratch reads/writes, the register
1022 // offset must always be positive.
1024 SDValue TFI = DAG.getTargetFrameIndex(FrameIndex, MVT::i32);
1025 if (Subtarget->enableHugeScratchBuffer())
1028 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, TFI,
1029 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 31)));
1032 /// This transforms the control flow intrinsics to get the branch destination as
1033 /// last parameter, also switches branch target with BR if the need arise
1034 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
1035 SelectionDAG &DAG) const {
1039 SDNode *Intr = BRCOND.getOperand(1).getNode();
1040 SDValue Target = BRCOND.getOperand(2);
1041 SDNode *BR = nullptr;
1043 if (Intr->getOpcode() == ISD::SETCC) {
1044 // As long as we negate the condition everything is fine
1045 SDNode *SetCC = Intr;
1046 assert(SetCC->getConstantOperandVal(1) == 1);
1047 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
1049 Intr = SetCC->getOperand(0).getNode();
1052 // Get the target from BR if we don't negate the condition
1053 BR = findUser(BRCOND, ISD::BR);
1054 Target = BR->getOperand(1);
1057 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
1059 // Build the result and
1060 ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());
1062 // operands of the new intrinsic call
1063 SmallVector<SDValue, 4> Ops;
1064 Ops.push_back(BRCOND.getOperand(0));
1065 Ops.append(Intr->op_begin() + 1, Intr->op_end());
1066 Ops.push_back(Target);
1068 // build the new intrinsic call
1069 SDNode *Result = DAG.getNode(
1070 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
1071 DAG.getVTList(Res), Ops).getNode();
1074 // Give the branch instruction our target
1077 BRCOND.getOperand(2)
1079 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
1080 DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
1081 BR = NewBR.getNode();
1084 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
1086 // Copy the intrinsic results to registers
1087 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
1088 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
1092 Chain = DAG.getCopyToReg(
1094 CopyToReg->getOperand(1),
1095 SDValue(Result, i - 1),
1098 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
1101 // Remove the old intrinsic from the chain
1102 DAG.ReplaceAllUsesOfValueWith(
1103 SDValue(Intr, Intr->getNumValues() - 1),
1104 Intr->getOperand(0));
1109 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
1111 SelectionDAG &DAG) const {
1112 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
1114 if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
1115 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
1118 const GlobalValue *GV = GSD->getGlobal();
1119 MVT PtrVT = getPointerTy(DAG.getDataLayout(), GSD->getAddressSpace());
1121 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
1122 return DAG.getNode(AMDGPUISD::CONST_DATA_PTR, DL, PtrVT, GA);
1125 SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL,
1127 // We can't use CopyToReg, because MachineCSE won't combine COPY instructions,
1128 // so we will end up with redundant moves to m0.
1130 // We can't use S_MOV_B32, because there is no way to specify m0 as the
1131 // destination register.
1133 // We have to use them both. Machine cse will combine all the S_MOV_B32
1134 // instructions and the register coalescer eliminate the extra copies.
1135 SDNode *M0 = DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, V.getValueType(), V);
1136 return DAG.getCopyToReg(Chain, DL, DAG.getRegister(AMDGPU::M0, MVT::i32),
1137 SDValue(M0, 0), SDValue()); // Glue
1138 // A Null SDValue creates
1142 SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,
1145 unsigned Offset) const {
1147 SDValue Param = LowerParameter(DAG, MVT::i32, MVT::i32, SL,
1148 DAG.getEntryNode(), Offset, false);
1149 // The local size values will have the hi 16-bits as zero.
1150 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param,
1151 DAG.getValueType(VT));
1154 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
1155 SelectionDAG &DAG) const {
1156 MachineFunction &MF = DAG.getMachineFunction();
1157 auto MFI = MF.getInfo<SIMachineFunctionInfo>();
1158 const SIRegisterInfo *TRI =
1159 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
1161 EVT VT = Op.getValueType();
1163 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1165 // TODO: Should this propagate fast-math-flags?
1167 switch (IntrinsicID) {
1168 case Intrinsic::amdgcn_dispatch_ptr:
1169 if (!Subtarget->isAmdHsaOS()) {
1170 DiagnosticInfoUnsupported BadIntrin(*MF.getFunction(),
1171 "hsa intrinsic without hsa target");
1172 DAG.getContext()->diagnose(BadIntrin);
1173 return DAG.getUNDEF(VT);
1176 return CreateLiveInRegister(DAG, &AMDGPU::SReg_64RegClass,
1177 TRI->getPreloadedValue(MF, SIRegisterInfo::DISPATCH_PTR), VT);
1179 case Intrinsic::r600_read_ngroups_x:
1180 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1181 SI::KernelInputOffsets::NGROUPS_X, false);
1182 case Intrinsic::r600_read_ngroups_y:
1183 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1184 SI::KernelInputOffsets::NGROUPS_Y, false);
1185 case Intrinsic::r600_read_ngroups_z:
1186 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1187 SI::KernelInputOffsets::NGROUPS_Z, false);
1188 case Intrinsic::r600_read_global_size_x:
1189 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1190 SI::KernelInputOffsets::GLOBAL_SIZE_X, false);
1191 case Intrinsic::r600_read_global_size_y:
1192 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1193 SI::KernelInputOffsets::GLOBAL_SIZE_Y, false);
1194 case Intrinsic::r600_read_global_size_z:
1195 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1196 SI::KernelInputOffsets::GLOBAL_SIZE_Z, false);
1197 case Intrinsic::r600_read_local_size_x:
1198 return lowerImplicitZextParam(DAG, Op, MVT::i16,
1199 SI::KernelInputOffsets::LOCAL_SIZE_X);
1200 case Intrinsic::r600_read_local_size_y:
1201 return lowerImplicitZextParam(DAG, Op, MVT::i16,
1202 SI::KernelInputOffsets::LOCAL_SIZE_Y);
1203 case Intrinsic::r600_read_local_size_z:
1204 return lowerImplicitZextParam(DAG, Op, MVT::i16,
1205 SI::KernelInputOffsets::LOCAL_SIZE_Z);
1206 case Intrinsic::AMDGPU_read_workdim:
1207 // Really only 2 bits.
1208 return lowerImplicitZextParam(DAG, Op, MVT::i8,
1209 getImplicitParameterOffset(MFI, GRID_DIM));
1210 case Intrinsic::r600_read_tgid_x:
1211 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1212 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_X), VT);
1213 case Intrinsic::r600_read_tgid_y:
1214 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1215 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_Y), VT);
1216 case Intrinsic::r600_read_tgid_z:
1217 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1218 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_Z), VT);
1219 case Intrinsic::r600_read_tidig_x:
1220 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1221 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_X), VT);
1222 case Intrinsic::r600_read_tidig_y:
1223 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1224 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Y), VT);
1225 case Intrinsic::r600_read_tidig_z:
1226 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1227 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Z), VT);
1228 case AMDGPUIntrinsic::SI_load_const: {
1234 MachineMemOperand *MMO = MF.getMachineMemOperand(
1235 MachinePointerInfo(),
1236 MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
1237 VT.getStoreSize(), 4);
1238 return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
1239 Op->getVTList(), Ops, VT, MMO);
1241 case AMDGPUIntrinsic::SI_sample:
1242 return LowerSampleIntrinsic(AMDGPUISD::SAMPLE, Op, DAG);
1243 case AMDGPUIntrinsic::SI_sampleb:
1244 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEB, Op, DAG);
1245 case AMDGPUIntrinsic::SI_sampled:
1246 return LowerSampleIntrinsic(AMDGPUISD::SAMPLED, Op, DAG);
1247 case AMDGPUIntrinsic::SI_samplel:
1248 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEL, Op, DAG);
1249 case AMDGPUIntrinsic::SI_vs_load_input:
1250 return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
1255 case AMDGPUIntrinsic::AMDGPU_fract:
1256 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
1257 return DAG.getNode(ISD::FSUB, DL, VT, Op.getOperand(1),
1258 DAG.getNode(ISD::FFLOOR, DL, VT, Op.getOperand(1)));
1259 case AMDGPUIntrinsic::SI_fs_constant: {
1260 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
1261 SDValue Glue = M0.getValue(1);
1262 return DAG.getNode(AMDGPUISD::INTERP_MOV, DL, MVT::f32,
1263 DAG.getConstant(2, DL, MVT::i32), // P0
1264 Op.getOperand(1), Op.getOperand(2), Glue);
1266 case AMDGPUIntrinsic::SI_packf16:
1267 if (Op.getOperand(1).isUndef() && Op.getOperand(2).isUndef())
1268 return DAG.getUNDEF(MVT::i32);
1270 case AMDGPUIntrinsic::SI_fs_interp: {
1271 SDValue IJ = Op.getOperand(4);
1272 SDValue I = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ,
1273 DAG.getConstant(0, DL, MVT::i32));
1274 SDValue J = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ,
1275 DAG.getConstant(1, DL, MVT::i32));
1276 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
1277 SDValue Glue = M0.getValue(1);
1278 SDValue P1 = DAG.getNode(AMDGPUISD::INTERP_P1, DL,
1279 DAG.getVTList(MVT::f32, MVT::Glue),
1280 I, Op.getOperand(1), Op.getOperand(2), Glue);
1281 Glue = SDValue(P1.getNode(), 1);
1282 return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, P1, J,
1283 Op.getOperand(1), Op.getOperand(2), Glue);
1285 case Intrinsic::amdgcn_interp_p1: {
1286 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(4));
1287 SDValue Glue = M0.getValue(1);
1288 return DAG.getNode(AMDGPUISD::INTERP_P1, DL, MVT::f32, Op.getOperand(1),
1289 Op.getOperand(2), Op.getOperand(3), Glue);
1291 case Intrinsic::amdgcn_interp_p2: {
1292 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(5));
1293 SDValue Glue = SDValue(M0.getNode(), 1);
1294 return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, Op.getOperand(1),
1295 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4),
1299 return AMDGPUTargetLowering::LowerOperation(Op, DAG);
1303 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
1304 SelectionDAG &DAG) const {
1305 MachineFunction &MF = DAG.getMachineFunction();
1307 SDValue Chain = Op.getOperand(0);
1308 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1310 switch (IntrinsicID) {
1311 case AMDGPUIntrinsic::SI_sendmsg: {
1312 Chain = copyToM0(DAG, Chain, DL, Op.getOperand(3));
1313 SDValue Glue = Chain.getValue(1);
1314 return DAG.getNode(AMDGPUISD::SENDMSG, DL, MVT::Other, Chain,
1315 Op.getOperand(2), Glue);
1317 case AMDGPUIntrinsic::SI_tbuffer_store: {
1335 EVT VT = Op.getOperand(3).getValueType();
1337 MachineMemOperand *MMO = MF.getMachineMemOperand(
1338 MachinePointerInfo(),
1339 MachineMemOperand::MOStore,
1340 VT.getStoreSize(), 4);
1341 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
1342 Op->getVTList(), Ops, VT, MMO);
1349 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1351 LoadSDNode *Load = cast<LoadSDNode>(Op);
1353 if (Op.getValueType().isVector()) {
1354 assert(Op.getValueType().getVectorElementType() == MVT::i32 &&
1355 "Custom lowering for non-i32 vectors hasn't been implemented.");
1356 unsigned NumElements = Op.getValueType().getVectorNumElements();
1357 assert(NumElements != 2 && "v2 loads are supported for all address spaces.");
1359 switch (Load->getAddressSpace()) {
1361 case AMDGPUAS::CONSTANT_ADDRESS:
1362 if (isMemOpUniform(Load))
1364 // Non-uniform loads will be selected to MUBUF instructions, so they
1365 // have the same legalization requires ments as global and private
1369 case AMDGPUAS::GLOBAL_ADDRESS:
1370 case AMDGPUAS::PRIVATE_ADDRESS:
1371 if (NumElements >= 8)
1372 return SplitVectorLoad(Op, DAG);
1374 // v4 loads are supported for private and global memory.
1375 if (NumElements <= 4)
1378 case AMDGPUAS::LOCAL_ADDRESS:
1379 // If properly aligned, if we split we might be able to use ds_read_b64.
1380 return SplitVectorLoad(Op, DAG);
1384 return AMDGPUTargetLowering::LowerLOAD(Op, DAG);
1387 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
1389 SelectionDAG &DAG) const {
1390 return DAG.getNode(Opcode, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
1396 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
1397 if (Op.getValueType() != MVT::i64)
1401 SDValue Cond = Op.getOperand(0);
1403 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
1404 SDValue One = DAG.getConstant(1, DL, MVT::i32);
1406 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
1407 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
1409 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
1410 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
1412 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
1414 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
1415 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
1417 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
1419 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
1420 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
1423 // Catch division cases where we can use shortcuts with rcp and rsq
1425 SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
1427 SDValue LHS = Op.getOperand(0);
1428 SDValue RHS = Op.getOperand(1);
1429 EVT VT = Op.getValueType();
1430 bool Unsafe = DAG.getTarget().Options.UnsafeFPMath;
1432 if (const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(LHS)) {
1433 if ((Unsafe || (VT == MVT::f32 && !Subtarget->hasFP32Denormals())) &&
1434 CLHS->isExactlyValue(1.0)) {
1435 // v_rcp_f32 and v_rsq_f32 do not support denormals, and according to
1436 // the CI documentation has a worst case error of 1 ulp.
1437 // OpenCL requires <= 2.5 ulp for 1.0 / x, so it should always be OK to
1438 // use it as long as we aren't trying to use denormals.
1440 // 1.0 / sqrt(x) -> rsq(x)
1442 // XXX - Is UnsafeFPMath sufficient to do this for f64? The maximum ULP
1443 // error seems really high at 2^29 ULP.
1444 if (RHS.getOpcode() == ISD::FSQRT)
1445 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0));
1447 // 1.0 / x -> rcp(x)
1448 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1453 // Turn into multiply by the reciprocal.
1454 // x / y -> x * (1.0 / y)
1456 Flags.setUnsafeAlgebra(true);
1457 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1458 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip, &Flags);
1464 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
1465 SDValue FastLowered = LowerFastFDIV(Op, DAG);
1466 if (FastLowered.getNode())
1469 // This uses v_rcp_f32 which does not handle denormals. Let this hit a
1470 // selection error for now rather than do something incorrect.
1471 if (Subtarget->hasFP32Denormals())
1475 SDValue LHS = Op.getOperand(0);
1476 SDValue RHS = Op.getOperand(1);
1478 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
1480 const APFloat K0Val(BitsToFloat(0x6f800000));
1481 const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32);
1483 const APFloat K1Val(BitsToFloat(0x2f800000));
1484 const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32);
1486 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
1489 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
1491 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
1493 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
1495 // TODO: Should this propagate fast-math-flags?
1497 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
1499 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
1501 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
1503 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
1506 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
1507 if (DAG.getTarget().Options.UnsafeFPMath)
1508 return LowerFastFDIV(Op, DAG);
1511 SDValue X = Op.getOperand(0);
1512 SDValue Y = Op.getOperand(1);
1514 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1516 SDVTList ScaleVT = DAG.getVTList(MVT::f64, MVT::i1);
1518 SDValue DivScale0 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, Y, Y, X);
1520 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0);
1522 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0);
1524 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One);
1526 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp);
1528 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One);
1530 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X);
1532 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1);
1533 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3);
1535 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64,
1536 NegDivScale0, Mul, DivScale1);
1540 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
1541 // Workaround a hardware bug on SI where the condition output from div_scale
1544 const SDValue Hi = DAG.getConstant(1, SL, MVT::i32);
1546 // Figure out if the scale to use for div_fmas.
1547 SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
1548 SDValue DenBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Y);
1549 SDValue Scale0BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale0);
1550 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1);
1552 SDValue NumHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, NumBC, Hi);
1553 SDValue DenHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, DenBC, Hi);
1556 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale0BC, Hi);
1558 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale1BC, Hi);
1560 SDValue CmpDen = DAG.getSetCC(SL, MVT::i1, DenHi, Scale0Hi, ISD::SETEQ);
1561 SDValue CmpNum = DAG.getSetCC(SL, MVT::i1, NumHi, Scale1Hi, ISD::SETEQ);
1562 Scale = DAG.getNode(ISD::XOR, SL, MVT::i1, CmpNum, CmpDen);
1564 Scale = DivScale1.getValue(1);
1567 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f64,
1568 Fma4, Fma3, Mul, Scale);
1570 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f64, Fmas, Y, X);
1573 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
1574 EVT VT = Op.getValueType();
1577 return LowerFDIV32(Op, DAG);
1580 return LowerFDIV64(Op, DAG);
1582 llvm_unreachable("Unexpected type for fdiv");
1585 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1587 StoreSDNode *Store = cast<StoreSDNode>(Op);
1588 EVT VT = Store->getMemoryVT();
1590 // These stores are legal.
1591 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
1592 if (VT.isVector() && VT.getVectorNumElements() > 4)
1593 return ScalarizeVectorStore(Op, DAG);
1597 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1601 if (VT.isVector() && VT.getVectorNumElements() >= 8)
1602 return SplitVectorStore(Op, DAG);
1605 return DAG.getTruncStore(Store->getChain(), DL,
1606 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
1607 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
1612 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
1614 EVT VT = Op.getValueType();
1615 SDValue Arg = Op.getOperand(0);
1616 // TODO: Should this propagate fast-math-flags?
1617 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT,
1618 DAG.getNode(ISD::FMUL, DL, VT, Arg,
1619 DAG.getConstantFP(0.5/M_PI, DL,
1622 switch (Op.getOpcode()) {
1624 return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, FractPart);
1626 return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, FractPart);
1628 llvm_unreachable("Wrong trig opcode");
1632 //===----------------------------------------------------------------------===//
1633 // Custom DAG optimizations
1634 //===----------------------------------------------------------------------===//
1636 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
1637 DAGCombinerInfo &DCI) const {
1638 EVT VT = N->getValueType(0);
1639 EVT ScalarVT = VT.getScalarType();
1640 if (ScalarVT != MVT::f32)
1643 SelectionDAG &DAG = DCI.DAG;
1646 SDValue Src = N->getOperand(0);
1647 EVT SrcVT = Src.getValueType();
1649 // TODO: We could try to match extracting the higher bytes, which would be
1650 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
1651 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
1652 // about in practice.
1653 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
1654 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
1655 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
1656 DCI.AddToWorklist(Cvt.getNode());
1661 // We are primarily trying to catch operations on illegal vector types
1662 // before they are expanded.
1663 // For scalars, we can use the more flexible method of checking masked bits
1664 // after legalization.
1665 if (!DCI.isBeforeLegalize() ||
1666 !SrcVT.isVector() ||
1667 SrcVT.getVectorElementType() != MVT::i8) {
1671 assert(DCI.isBeforeLegalize() && "Unexpected legal type");
1673 // Weird sized vectors are a pain to handle, but we know 3 is really the same
1675 unsigned NElts = SrcVT.getVectorNumElements();
1676 if (!SrcVT.isSimple() && NElts != 3)
1679 // Handle v4i8 -> v4f32 extload. Replace the v4i8 with a legal i32 load to
1680 // prevent a mess from expanding to v4i32 and repacking.
1681 if (ISD::isNormalLoad(Src.getNode()) && Src.hasOneUse()) {
1682 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT);
1683 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT);
1684 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f32, NElts);
1685 LoadSDNode *Load = cast<LoadSDNode>(Src);
1687 unsigned AS = Load->getAddressSpace();
1688 unsigned Align = Load->getAlignment();
1689 Type *Ty = LoadVT.getTypeForEVT(*DAG.getContext());
1690 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
1692 // Don't try to replace the load if we have to expand it due to alignment
1693 // problems. Otherwise we will end up scalarizing the load, and trying to
1694 // repack into the vector for no real reason.
1695 if (Align < ABIAlignment &&
1696 !allowsMisalignedMemoryAccesses(LoadVT, AS, Align, nullptr)) {
1700 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT,
1704 Load->getMemOperand());
1706 // Make sure successors of the original load stay after it by updating
1707 // them to use the new Chain.
1708 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), NewLoad.getValue(1));
1710 SmallVector<SDValue, 4> Elts;
1711 if (RegVT.isVector())
1712 DAG.ExtractVectorElements(NewLoad, Elts);
1714 Elts.push_back(NewLoad);
1716 SmallVector<SDValue, 4> Ops;
1718 unsigned EltIdx = 0;
1719 for (SDValue Elt : Elts) {
1720 unsigned ComponentsInElt = std::min(4u, NElts - 4 * EltIdx);
1721 for (unsigned I = 0; I < ComponentsInElt; ++I) {
1722 unsigned Opc = AMDGPUISD::CVT_F32_UBYTE0 + I;
1723 SDValue Cvt = DAG.getNode(Opc, DL, MVT::f32, Elt);
1724 DCI.AddToWorklist(Cvt.getNode());
1731 assert(Ops.size() == NElts);
1733 return DAG.getNode(ISD::BUILD_VECTOR, DL, FloatVT, Ops);
1739 /// \brief Return true if the given offset Size in bytes can be folded into
1740 /// the immediate offsets of a memory instruction for the given address space.
1741 static bool canFoldOffset(unsigned OffsetSize, unsigned AS,
1742 const AMDGPUSubtarget &STI) {
1744 case AMDGPUAS::GLOBAL_ADDRESS: {
1745 // MUBUF instructions a 12-bit offset in bytes.
1746 return isUInt<12>(OffsetSize);
1748 case AMDGPUAS::CONSTANT_ADDRESS: {
1749 // SMRD instructions have an 8-bit offset in dwords on SI and
1750 // a 20-bit offset in bytes on VI.
1751 if (STI.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1752 return isUInt<20>(OffsetSize);
1754 return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4);
1756 case AMDGPUAS::LOCAL_ADDRESS:
1757 case AMDGPUAS::REGION_ADDRESS: {
1758 // The single offset versions have a 16-bit offset in bytes.
1759 return isUInt<16>(OffsetSize);
1761 case AMDGPUAS::PRIVATE_ADDRESS:
1762 // Indirect register addressing does not use any offsets.
1768 // (shl (add x, c1), c2) -> add (shl x, c2), (shl c1, c2)
1770 // This is a variant of
1771 // (mul (add x, c1), c2) -> add (mul x, c2), (mul c1, c2),
1773 // The normal DAG combiner will do this, but only if the add has one use since
1774 // that would increase the number of instructions.
1776 // This prevents us from seeing a constant offset that can be folded into a
1777 // memory instruction's addressing mode. If we know the resulting add offset of
1778 // a pointer can be folded into an addressing offset, we can replace the pointer
1779 // operand with the add of new constant offset. This eliminates one of the uses,
1780 // and may allow the remaining use to also be simplified.
1782 SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
1784 DAGCombinerInfo &DCI) const {
1785 SDValue N0 = N->getOperand(0);
1786 SDValue N1 = N->getOperand(1);
1788 if (N0.getOpcode() != ISD::ADD)
1791 const ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(N1);
1795 const ConstantSDNode *CAdd = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1799 // If the resulting offset is too large, we can't fold it into the addressing
1801 APInt Offset = CAdd->getAPIntValue() << CN1->getAPIntValue();
1802 if (!canFoldOffset(Offset.getZExtValue(), AddrSpace, *Subtarget))
1805 SelectionDAG &DAG = DCI.DAG;
1807 EVT VT = N->getValueType(0);
1809 SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1);
1810 SDValue COffset = DAG.getConstant(Offset, SL, MVT::i32);
1812 return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset);
1815 SDValue SITargetLowering::performAndCombine(SDNode *N,
1816 DAGCombinerInfo &DCI) const {
1817 if (DCI.isBeforeLegalize())
1820 SelectionDAG &DAG = DCI.DAG;
1822 // (and (fcmp ord x, x), (fcmp une (fabs x), inf)) ->
1823 // fp_class x, ~(s_nan | q_nan | n_infinity | p_infinity)
1824 SDValue LHS = N->getOperand(0);
1825 SDValue RHS = N->getOperand(1);
1827 if (LHS.getOpcode() == ISD::SETCC &&
1828 RHS.getOpcode() == ISD::SETCC) {
1829 ISD::CondCode LCC = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
1830 ISD::CondCode RCC = cast<CondCodeSDNode>(RHS.getOperand(2))->get();
1832 SDValue X = LHS.getOperand(0);
1833 SDValue Y = RHS.getOperand(0);
1834 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X)
1837 if (LCC == ISD::SETO) {
1838 if (X != LHS.getOperand(1))
1841 if (RCC == ISD::SETUNE) {
1842 const ConstantFPSDNode *C1 = dyn_cast<ConstantFPSDNode>(RHS.getOperand(1));
1843 if (!C1 || !C1->isInfinity() || C1->isNegative())
1846 const uint32_t Mask = SIInstrFlags::N_NORMAL |
1847 SIInstrFlags::N_SUBNORMAL |
1848 SIInstrFlags::N_ZERO |
1849 SIInstrFlags::P_ZERO |
1850 SIInstrFlags::P_SUBNORMAL |
1851 SIInstrFlags::P_NORMAL;
1853 static_assert(((~(SIInstrFlags::S_NAN |
1854 SIInstrFlags::Q_NAN |
1855 SIInstrFlags::N_INFINITY |
1856 SIInstrFlags::P_INFINITY)) & 0x3ff) == Mask,
1860 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
1861 X, DAG.getConstant(Mask, DL, MVT::i32));
1869 SDValue SITargetLowering::performOrCombine(SDNode *N,
1870 DAGCombinerInfo &DCI) const {
1871 SelectionDAG &DAG = DCI.DAG;
1872 SDValue LHS = N->getOperand(0);
1873 SDValue RHS = N->getOperand(1);
1875 // or (fp_class x, c1), (fp_class x, c2) -> fp_class x, (c1 | c2)
1876 if (LHS.getOpcode() == AMDGPUISD::FP_CLASS &&
1877 RHS.getOpcode() == AMDGPUISD::FP_CLASS) {
1878 SDValue Src = LHS.getOperand(0);
1879 if (Src != RHS.getOperand(0))
1882 const ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
1883 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
1887 // Only 10 bits are used.
1888 static const uint32_t MaxMask = 0x3ff;
1890 uint32_t NewMask = (CLHS->getZExtValue() | CRHS->getZExtValue()) & MaxMask;
1892 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
1893 Src, DAG.getConstant(NewMask, DL, MVT::i32));
1899 SDValue SITargetLowering::performClassCombine(SDNode *N,
1900 DAGCombinerInfo &DCI) const {
1901 SelectionDAG &DAG = DCI.DAG;
1902 SDValue Mask = N->getOperand(1);
1904 // fp_class x, 0 -> false
1905 if (const ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Mask)) {
1906 if (CMask->isNullValue())
1907 return DAG.getConstant(0, SDLoc(N), MVT::i1);
1913 static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
1916 return AMDGPUISD::FMAX3;
1918 return AMDGPUISD::SMAX3;
1920 return AMDGPUISD::UMAX3;
1922 return AMDGPUISD::FMIN3;
1924 return AMDGPUISD::SMIN3;
1926 return AMDGPUISD::UMIN3;
1928 llvm_unreachable("Not a min/max opcode");
1932 SDValue SITargetLowering::performMin3Max3Combine(SDNode *N,
1933 DAGCombinerInfo &DCI) const {
1934 SelectionDAG &DAG = DCI.DAG;
1936 unsigned Opc = N->getOpcode();
1937 SDValue Op0 = N->getOperand(0);
1938 SDValue Op1 = N->getOperand(1);
1940 // Only do this if the inner op has one use since this will just increases
1941 // register pressure for no benefit.
1943 // max(max(a, b), c)
1944 if (Op0.getOpcode() == Opc && Op0.hasOneUse()) {
1946 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
1954 // max(a, max(b, c))
1955 if (Op1.getOpcode() == Opc && Op1.hasOneUse()) {
1957 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
1968 SDValue SITargetLowering::performSetCCCombine(SDNode *N,
1969 DAGCombinerInfo &DCI) const {
1970 SelectionDAG &DAG = DCI.DAG;
1973 SDValue LHS = N->getOperand(0);
1974 SDValue RHS = N->getOperand(1);
1975 EVT VT = LHS.getValueType();
1977 if (VT != MVT::f32 && VT != MVT::f64)
1980 // Match isinf pattern
1981 // (fcmp oeq (fabs x), inf) -> (fp_class x, (p_infinity | n_infinity))
1982 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
1983 if (CC == ISD::SETOEQ && LHS.getOpcode() == ISD::FABS) {
1984 const ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
1988 const APFloat &APF = CRHS->getValueAPF();
1989 if (APF.isInfinity() && !APF.isNegative()) {
1990 unsigned Mask = SIInstrFlags::P_INFINITY | SIInstrFlags::N_INFINITY;
1991 return DAG.getNode(AMDGPUISD::FP_CLASS, SL, MVT::i1, LHS.getOperand(0),
1992 DAG.getConstant(Mask, SL, MVT::i32));
1999 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
2000 DAGCombinerInfo &DCI) const {
2001 SelectionDAG &DAG = DCI.DAG;
2004 switch (N->getOpcode()) {
2006 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
2008 return performSetCCCombine(N, DCI);
2009 case ISD::FMAXNUM: // TODO: What about fmax_legacy?
2015 if (DCI.getDAGCombineLevel() >= AfterLegalizeDAG &&
2016 N->getValueType(0) != MVT::f64 &&
2017 getTargetMachine().getOptLevel() > CodeGenOpt::None)
2018 return performMin3Max3Combine(N, DCI);
2022 case AMDGPUISD::CVT_F32_UBYTE0:
2023 case AMDGPUISD::CVT_F32_UBYTE1:
2024 case AMDGPUISD::CVT_F32_UBYTE2:
2025 case AMDGPUISD::CVT_F32_UBYTE3: {
2026 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
2028 SDValue Src = N->getOperand(0);
2029 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
2031 APInt KnownZero, KnownOne;
2032 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2033 !DCI.isBeforeLegalizeOps());
2034 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2035 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
2036 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
2037 DCI.CommitTargetLoweringOpt(TLO);
2043 case ISD::UINT_TO_FP: {
2044 return performUCharToFloatCombine(N, DCI);
2047 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2050 EVT VT = N->getValueType(0);
2054 // Only do this if we are not trying to support denormals. v_mad_f32 does
2055 // not support denormals ever.
2056 if (Subtarget->hasFP32Denormals())
2059 SDValue LHS = N->getOperand(0);
2060 SDValue RHS = N->getOperand(1);
2062 // These should really be instruction patterns, but writing patterns with
2063 // source modiifiers is a pain.
2065 // fadd (fadd (a, a), b) -> mad 2.0, a, b
2066 if (LHS.getOpcode() == ISD::FADD) {
2067 SDValue A = LHS.getOperand(0);
2068 if (A == LHS.getOperand(1)) {
2069 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
2070 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, RHS);
2074 // fadd (b, fadd (a, a)) -> mad 2.0, a, b
2075 if (RHS.getOpcode() == ISD::FADD) {
2076 SDValue A = RHS.getOperand(0);
2077 if (A == RHS.getOperand(1)) {
2078 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
2079 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, LHS);
2086 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2089 EVT VT = N->getValueType(0);
2091 // Try to get the fneg to fold into the source modifier. This undoes generic
2092 // DAG combines and folds them into the mad.
2094 // Only do this if we are not trying to support denormals. v_mad_f32 does
2095 // not support denormals ever.
2096 if (VT == MVT::f32 &&
2097 !Subtarget->hasFP32Denormals()) {
2098 SDValue LHS = N->getOperand(0);
2099 SDValue RHS = N->getOperand(1);
2100 if (LHS.getOpcode() == ISD::FADD) {
2101 // (fsub (fadd a, a), c) -> mad 2.0, a, (fneg c)
2103 SDValue A = LHS.getOperand(0);
2104 if (A == LHS.getOperand(1)) {
2105 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
2106 SDValue NegRHS = DAG.getNode(ISD::FNEG, DL, VT, RHS);
2108 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, NegRHS);
2112 if (RHS.getOpcode() == ISD::FADD) {
2113 // (fsub c, (fadd a, a)) -> mad -2.0, a, c
2115 SDValue A = RHS.getOperand(0);
2116 if (A == RHS.getOperand(1)) {
2117 const SDValue NegTwo = DAG.getConstantFP(-2.0, DL, MVT::f32);
2118 return DAG.getNode(ISD::FMAD, DL, VT, NegTwo, A, LHS);
2129 case ISD::ATOMIC_LOAD:
2130 case ISD::ATOMIC_STORE:
2131 case ISD::ATOMIC_CMP_SWAP:
2132 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
2133 case ISD::ATOMIC_SWAP:
2134 case ISD::ATOMIC_LOAD_ADD:
2135 case ISD::ATOMIC_LOAD_SUB:
2136 case ISD::ATOMIC_LOAD_AND:
2137 case ISD::ATOMIC_LOAD_OR:
2138 case ISD::ATOMIC_LOAD_XOR:
2139 case ISD::ATOMIC_LOAD_NAND:
2140 case ISD::ATOMIC_LOAD_MIN:
2141 case ISD::ATOMIC_LOAD_MAX:
2142 case ISD::ATOMIC_LOAD_UMIN:
2143 case ISD::ATOMIC_LOAD_UMAX: { // TODO: Target mem intrinsics.
2144 if (DCI.isBeforeLegalize())
2147 MemSDNode *MemNode = cast<MemSDNode>(N);
2148 SDValue Ptr = MemNode->getBasePtr();
2150 // TODO: We could also do this for multiplies.
2151 unsigned AS = MemNode->getAddressSpace();
2152 if (Ptr.getOpcode() == ISD::SHL && AS != AMDGPUAS::PRIVATE_ADDRESS) {
2153 SDValue NewPtr = performSHLPtrCombine(Ptr.getNode(), AS, DCI);
2155 SmallVector<SDValue, 8> NewOps(MemNode->op_begin(), MemNode->op_end());
2157 NewOps[N->getOpcode() == ISD::STORE ? 2 : 1] = NewPtr;
2158 return SDValue(DAG.UpdateNodeOperands(MemNode, NewOps), 0);
2164 return performAndCombine(N, DCI);
2166 return performOrCombine(N, DCI);
2167 case AMDGPUISD::FP_CLASS:
2168 return performClassCombine(N, DCI);
2170 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
2173 /// \brief Analyze the possible immediate value Op
2175 /// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
2176 /// and the immediate value if it's a literal immediate
2177 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
2179 const SIInstrInfo *TII =
2180 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2182 if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
2183 if (TII->isInlineConstant(Node->getAPIntValue()))
2186 uint64_t Val = Node->getZExtValue();
2187 return isUInt<32>(Val) ? Val : -1;
2190 if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
2191 if (TII->isInlineConstant(Node->getValueAPF().bitcastToAPInt()))
2194 if (Node->getValueType(0) == MVT::f32)
2195 return FloatToBits(Node->getValueAPF().convertToFloat());
2203 /// \brief Helper function for adjustWritemask
2204 static unsigned SubIdx2Lane(unsigned Idx) {
2207 case AMDGPU::sub0: return 0;
2208 case AMDGPU::sub1: return 1;
2209 case AMDGPU::sub2: return 2;
2210 case AMDGPU::sub3: return 3;
2214 /// \brief Adjust the writemask of MIMG instructions
2215 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
2216 SelectionDAG &DAG) const {
2217 SDNode *Users[4] = { };
2219 unsigned OldDmask = Node->getConstantOperandVal(0);
2220 unsigned NewDmask = 0;
2222 // Try to figure out the used register components
2223 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
2226 // Abort if we can't understand the usage
2227 if (!I->isMachineOpcode() ||
2228 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
2231 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
2232 // Note that subregs are packed, i.e. Lane==0 is the first bit set
2233 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
2235 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
2237 // Set which texture component corresponds to the lane.
2239 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
2241 Comp = countTrailingZeros(Dmask);
2242 Dmask &= ~(1 << Comp);
2245 // Abort if we have more than one user per component
2250 NewDmask |= 1 << Comp;
2253 // Abort if there's no change
2254 if (NewDmask == OldDmask)
2257 // Adjust the writemask in the node
2258 std::vector<SDValue> Ops;
2259 Ops.push_back(DAG.getTargetConstant(NewDmask, SDLoc(Node), MVT::i32));
2260 Ops.insert(Ops.end(), Node->op_begin() + 1, Node->op_end());
2261 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
2263 // If we only got one lane, replace it with a copy
2264 // (if NewDmask has only one bit set...)
2265 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
2266 SDValue RC = DAG.getTargetConstant(AMDGPU::VGPR_32RegClassID, SDLoc(),
2268 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
2269 SDLoc(), Users[Lane]->getValueType(0),
2270 SDValue(Node, 0), RC);
2271 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
2275 // Update the users of the node with the new indices
2276 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
2278 SDNode *User = Users[i];
2282 SDValue Op = DAG.getTargetConstant(Idx, SDLoc(User), MVT::i32);
2283 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
2287 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
2288 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
2289 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
2294 static bool isFrameIndexOp(SDValue Op) {
2295 if (Op.getOpcode() == ISD::AssertZext)
2296 Op = Op.getOperand(0);
2298 return isa<FrameIndexSDNode>(Op);
2301 /// \brief Legalize target independent instructions (e.g. INSERT_SUBREG)
2302 /// with frame index operands.
2303 /// LLVM assumes that inputs are to these instructions are registers.
2304 void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
2305 SelectionDAG &DAG) const {
2307 SmallVector<SDValue, 8> Ops;
2308 for (unsigned i = 0; i < Node->getNumOperands(); ++i) {
2309 if (!isFrameIndexOp(Node->getOperand(i))) {
2310 Ops.push_back(Node->getOperand(i));
2315 Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
2316 Node->getOperand(i).getValueType(),
2317 Node->getOperand(i)), 0));
2320 DAG.UpdateNodeOperands(Node, Ops);
2323 /// \brief Fold the instructions after selecting them.
2324 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
2325 SelectionDAG &DAG) const {
2326 const SIInstrInfo *TII =
2327 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2329 if (TII->isMIMG(Node->getMachineOpcode()))
2330 adjustWritemask(Node, DAG);
2332 if (Node->getMachineOpcode() == AMDGPU::INSERT_SUBREG ||
2333 Node->getMachineOpcode() == AMDGPU::REG_SEQUENCE) {
2334 legalizeTargetIndependentNode(Node, DAG);
2340 /// \brief Assign the register class depending on the number of
2341 /// bits set in the writemask
2342 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
2343 SDNode *Node) const {
2344 const SIInstrInfo *TII =
2345 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2347 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2349 if (TII->isVOP3(MI->getOpcode())) {
2350 // Make sure constant bus requirements are respected.
2351 TII->legalizeOperandsVOP3(MRI, MI);
2355 if (TII->isMIMG(*MI)) {
2356 unsigned VReg = MI->getOperand(0).getReg();
2357 unsigned Writemask = MI->getOperand(1).getImm();
2358 unsigned BitsSet = 0;
2359 for (unsigned i = 0; i < 4; ++i)
2360 BitsSet += Writemask & (1 << i) ? 1 : 0;
2362 const TargetRegisterClass *RC;
2365 case 1: RC = &AMDGPU::VGPR_32RegClass; break;
2366 case 2: RC = &AMDGPU::VReg_64RegClass; break;
2367 case 3: RC = &AMDGPU::VReg_96RegClass; break;
2370 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
2371 MI->setDesc(TII->get(NewOpcode));
2372 MRI.setRegClass(VReg, RC);
2376 // Replace unused atomics with the no return version.
2377 int NoRetAtomicOp = AMDGPU::getAtomicNoRetOp(MI->getOpcode());
2378 if (NoRetAtomicOp != -1) {
2379 if (!Node->hasAnyUseOfValue(0)) {
2380 MI->setDesc(TII->get(NoRetAtomicOp));
2381 MI->RemoveOperand(0);
2388 static SDValue buildSMovImm32(SelectionDAG &DAG, SDLoc DL, uint64_t Val) {
2389 SDValue K = DAG.getTargetConstant(Val, DL, MVT::i32);
2390 return SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0);
2393 MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
2395 SDValue Ptr) const {
2396 const SIInstrInfo *TII =
2397 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
2399 // Build the half of the subregister with the constants before building the
2400 // full 128-bit register. If we are building multiple resource descriptors,
2401 // this will allow CSEing of the 2-component register.
2402 const SDValue Ops0[] = {
2403 DAG.getTargetConstant(AMDGPU::SGPR_64RegClassID, DL, MVT::i32),
2404 buildSMovImm32(DAG, DL, 0),
2405 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
2406 buildSMovImm32(DAG, DL, TII->getDefaultRsrcDataFormat() >> 32),
2407 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
2410 SDValue SubRegHi = SDValue(DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL,
2411 MVT::v2i32, Ops0), 0);
2413 // Combine the constants and the pointer.
2414 const SDValue Ops1[] = {
2415 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
2417 DAG.getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32),
2419 DAG.getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32)
2422 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1);
2425 /// \brief Return a resource descriptor with the 'Add TID' bit enabled
2426 /// The TID (Thread ID) is multiplied by the stride value (bits [61:48]
2427 /// of the resource descriptor) to create an offset, which is added to
2428 /// the resource pointer.
2429 MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG,
2432 uint32_t RsrcDword1,
2433 uint64_t RsrcDword2And3) const {
2434 SDValue PtrLo = DAG.getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr);
2435 SDValue PtrHi = DAG.getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
2437 PtrHi = SDValue(DAG.getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,
2438 DAG.getConstant(RsrcDword1, DL, MVT::i32)),
2442 SDValue DataLo = buildSMovImm32(DAG, DL,
2443 RsrcDword2And3 & UINT64_C(0xFFFFFFFF));
2444 SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32);
2446 const SDValue Ops[] = {
2447 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
2449 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
2451 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32),
2453 DAG.getTargetConstant(AMDGPU::sub2, DL, MVT::i32),
2455 DAG.getTargetConstant(AMDGPU::sub3, DL, MVT::i32)
2458 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
2461 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2462 const TargetRegisterClass *RC,
2463 unsigned Reg, EVT VT) const {
2464 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
2466 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
2467 cast<RegisterSDNode>(VReg)->getReg(), VT);
2470 //===----------------------------------------------------------------------===//
2471 // SI Inline Assembly Support
2472 //===----------------------------------------------------------------------===//
2474 std::pair<unsigned, const TargetRegisterClass *>
2475 SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2476 StringRef Constraint,
2479 if (Constraint.size() == 1) {
2480 switch (Constraint[0]) {
2483 switch (VT.getSizeInBits()) {
2485 return std::make_pair(0U, nullptr);
2487 return std::make_pair(0U, &AMDGPU::SGPR_32RegClass);
2489 return std::make_pair(0U, &AMDGPU::SGPR_64RegClass);
2491 return std::make_pair(0U, &AMDGPU::SReg_128RegClass);
2493 return std::make_pair(0U, &AMDGPU::SReg_256RegClass);
2497 switch (VT.getSizeInBits()) {
2499 return std::make_pair(0U, nullptr);
2501 return std::make_pair(0U, &AMDGPU::VGPR_32RegClass);
2503 return std::make_pair(0U, &AMDGPU::VReg_64RegClass);
2505 return std::make_pair(0U, &AMDGPU::VReg_96RegClass);
2507 return std::make_pair(0U, &AMDGPU::VReg_128RegClass);
2509 return std::make_pair(0U, &AMDGPU::VReg_256RegClass);
2511 return std::make_pair(0U, &AMDGPU::VReg_512RegClass);
2516 if (Constraint.size() > 1) {
2517 const TargetRegisterClass *RC = nullptr;
2518 if (Constraint[1] == 'v') {
2519 RC = &AMDGPU::VGPR_32RegClass;
2520 } else if (Constraint[1] == 's') {
2521 RC = &AMDGPU::SGPR_32RegClass;
2526 bool Failed = Constraint.substr(2).getAsInteger(10, Idx);
2527 if (!Failed && Idx < RC->getNumRegs())
2528 return std::make_pair(RC->getRegister(Idx), RC);
2531 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2534 SITargetLowering::ConstraintType
2535 SITargetLowering::getConstraintType(StringRef Constraint) const {
2536 if (Constraint.size() == 1) {
2537 switch (Constraint[0]) {
2541 return C_RegisterClass;
2544 return TargetLowering::getConstraintType(Constraint);