1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SI Instruction format definitions.
12 //===----------------------------------------------------------------------===//
14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
17 field bits<1> VM_CNT = 0;
18 field bits<1> EXP_CNT = 0;
19 field bits<1> LGKM_CNT = 0;
21 field bits<1> SALU = 0;
22 field bits<1> VALU = 0;
24 field bits<1> SOP1 = 0;
25 field bits<1> SOP2 = 0;
26 field bits<1> SOPC = 0;
27 field bits<1> SOPK = 0;
28 field bits<1> SOPP = 0;
30 field bits<1> VOP1 = 0;
31 field bits<1> VOP2 = 0;
32 field bits<1> VOP3 = 0;
33 field bits<1> VOPC = 0;
35 field bits<1> MUBUF = 0;
36 field bits<1> MTBUF = 0;
37 field bits<1> SMRD = 0;
39 field bits<1> MIMG = 0;
40 field bits<1> FLAT = 0;
41 field bits<1> WQM = 0;
42 field bits<1> VGPRSpill = 0;
44 // These need to be kept in sync with the enum in SIInstrFlags.
45 let TSFlags{0} = VM_CNT;
46 let TSFlags{1} = EXP_CNT;
47 let TSFlags{2} = LGKM_CNT;
49 let TSFlags{3} = SALU;
50 let TSFlags{4} = VALU;
52 let TSFlags{5} = SOP1;
53 let TSFlags{6} = SOP2;
54 let TSFlags{7} = SOPC;
55 let TSFlags{8} = SOPK;
56 let TSFlags{9} = SOPP;
58 let TSFlags{10} = VOP1;
59 let TSFlags{11} = VOP2;
60 let TSFlags{12} = VOP3;
61 let TSFlags{13} = VOPC;
63 let TSFlags{14} = MUBUF;
64 let TSFlags{15} = MTBUF;
65 let TSFlags{16} = SMRD;
67 let TSFlags{18} = MIMG;
68 let TSFlags{19} = FLAT;
69 let TSFlags{20} = WQM;
70 let TSFlags{21} = VGPRSpill;
72 // Most instructions require adjustments after selection to satisfy
73 // operand requirements.
74 let hasPostISelHook = 1;
75 let SchedRW = [Write32Bit];
88 class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
90 let Uses = [EXEC] in {
92 class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
93 InstSI <outs, ins, asm, pattern> {
97 let hasSideEffects = 0;
98 let UseNamedOperandTable = 1;
102 class VOPCCommon <dag ins, string asm, list<dag> pattern> :
103 VOPAnyCommon <(outs), ins, asm, pattern> {
110 class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
111 VOPAnyCommon <outs, ins, asm, pattern> {
117 class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> :
118 VOPAnyCommon <outs, ins, asm, pattern> {
124 class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
125 VOPAnyCommon <outs, ins, asm, pattern> {
127 // Using complex patterns gives VOP3 patterns a very high complexity rating,
128 // but standalone patterns are almost always prefered, so we need to adjust the
129 // priority lower. The goal is to use a high number to reduce complexity to
130 // zero (or less than zero).
131 let AddedComplexity = -1000;
136 let AsmMatchConverter = "cvtVOP3";
137 let isCodeGenOnly = 0;
142 } // End Uses = [EXEC]
144 //===----------------------------------------------------------------------===//
146 //===----------------------------------------------------------------------===//
148 class SOP1e <bits<8> op> : Enc32 {
152 let Inst{7-0} = ssrc0;
154 let Inst{22-16} = sdst;
155 let Inst{31-23} = 0x17d; //encoding;
158 class SOP2e <bits<7> op> : Enc32 {
163 let Inst{7-0} = ssrc0;
164 let Inst{15-8} = ssrc1;
165 let Inst{22-16} = sdst;
166 let Inst{29-23} = op;
167 let Inst{31-30} = 0x2; // encoding
170 class SOPCe <bits<7> op> : Enc32 {
174 let Inst{7-0} = ssrc0;
175 let Inst{15-8} = ssrc1;
176 let Inst{22-16} = op;
177 let Inst{31-23} = 0x17e;
180 class SOPKe <bits<5> op> : Enc32 {
184 let Inst{15-0} = simm16;
185 let Inst{22-16} = sdst;
186 let Inst{27-23} = op;
187 let Inst{31-28} = 0xb; //encoding
190 class SOPK64e <bits<5> op> : Enc64 {
195 let Inst{15-0} = simm16;
196 let Inst{22-16} = sdst;
197 let Inst{27-23} = op;
198 let Inst{31-28} = 0xb;
200 let Inst{63-32} = imm;
203 class SOPPe <bits<7> op> : Enc32 {
206 let Inst{15-0} = simm16;
207 let Inst{22-16} = op;
208 let Inst{31-23} = 0x17f; // encoding
211 class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
216 let Inst{7-0} = offset;
218 let Inst{14-9} = sbase{6-1};
219 let Inst{21-15} = sdst;
220 let Inst{26-22} = op;
221 let Inst{31-27} = 0x18; //encoding
224 class SMRD_IMMe_ci <bits<5> op> : Enc64 {
229 let Inst{7-0} = 0xff;
231 let Inst{14-9} = sbase{6-1};
232 let Inst{21-15} = sdst;
233 let Inst{26-22} = op;
234 let Inst{31-27} = 0x18; //encoding
235 let Inst{63-32} = offset;
238 let SchedRW = [WriteSALU] in {
239 class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
240 InstSI<outs, ins, asm, pattern> {
243 let hasSideEffects = 0;
244 let isCodeGenOnly = 0;
249 class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> :
250 InstSI <outs, ins, asm, pattern> {
254 let hasSideEffects = 0;
255 let isCodeGenOnly = 0;
259 let UseNamedOperandTable = 1;
262 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
263 InstSI<outs, ins, asm, pattern>, SOPCe <op> {
267 let hasSideEffects = 0;
270 let isCodeGenOnly = 0;
273 let UseNamedOperandTable = 1;
276 class SOPK <dag outs, dag ins, string asm, list<dag> pattern> :
277 InstSI <outs, ins , asm, pattern> {
281 let hasSideEffects = 0;
285 let UseNamedOperandTable = 1;
288 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
289 InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
293 let hasSideEffects = 0;
297 let UseNamedOperandTable = 1;
300 } // let SchedRW = [WriteSALU]
302 class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
303 InstSI<outs, ins, asm, pattern> {
309 let hasSideEffects = 0;
310 let UseNamedOperandTable = 1;
311 let SchedRW = [WriteSMEM];
314 //===----------------------------------------------------------------------===//
315 // Vector ALU operations
316 //===----------------------------------------------------------------------===//
318 class VOP1e <bits<8> op> : Enc32 {
322 let Inst{8-0} = src0;
324 let Inst{24-17} = vdst;
325 let Inst{31-25} = 0x3f; //encoding
328 class VOP2e <bits<6> op> : Enc32 {
333 let Inst{8-0} = src0;
334 let Inst{16-9} = src1;
335 let Inst{24-17} = vdst;
336 let Inst{30-25} = op;
337 let Inst{31} = 0x0; //encoding
340 class VOP2_MADKe <bits<6> op> : Enc64 {
347 let Inst{8-0} = src0;
348 let Inst{16-9} = vsrc1;
349 let Inst{24-17} = vdst;
350 let Inst{30-25} = op;
351 let Inst{31} = 0x0; // encoding
352 let Inst{63-32} = src2;
355 class VOP3e <bits<9> op> : Enc64 {
357 bits<2> src0_modifiers;
359 bits<2> src1_modifiers;
361 bits<2> src2_modifiers;
366 let Inst{7-0} = vdst;
367 let Inst{8} = src0_modifiers{1};
368 let Inst{9} = src1_modifiers{1};
369 let Inst{10} = src2_modifiers{1};
370 let Inst{11} = clamp;
371 let Inst{25-17} = op;
372 let Inst{31-26} = 0x34; //encoding
373 let Inst{40-32} = src0;
374 let Inst{49-41} = src1;
375 let Inst{58-50} = src2;
376 let Inst{60-59} = omod;
377 let Inst{61} = src0_modifiers{0};
378 let Inst{62} = src1_modifiers{0};
379 let Inst{63} = src2_modifiers{0};
382 class VOP3be <bits<9> op> : Enc64 {
384 bits<2> src0_modifiers;
386 bits<2> src1_modifiers;
388 bits<2> src2_modifiers;
393 let Inst{7-0} = vdst;
394 let Inst{14-8} = sdst;
395 let Inst{25-17} = op;
396 let Inst{31-26} = 0x34; //encoding
397 let Inst{40-32} = src0;
398 let Inst{49-41} = src1;
399 let Inst{58-50} = src2;
400 let Inst{60-59} = omod;
401 let Inst{61} = src0_modifiers{0};
402 let Inst{62} = src1_modifiers{0};
403 let Inst{63} = src2_modifiers{0};
406 class VOPCe <bits<8> op> : Enc32 {
410 let Inst{8-0} = src0;
411 let Inst{16-9} = vsrc1;
412 let Inst{24-17} = op;
413 let Inst{31-25} = 0x3e;
416 class VINTRPe <bits<2> op> : Enc32 {
422 let Inst{7-0} = vsrc;
423 let Inst{9-8} = attrchan;
424 let Inst{15-10} = attr;
425 let Inst{17-16} = op;
426 let Inst{25-18} = vdst;
427 let Inst{31-26} = 0x32; // encoding
430 class DSe <bits<8> op> : Enc64 {
439 let Inst{7-0} = offset0;
440 let Inst{15-8} = offset1;
442 let Inst{25-18} = op;
443 let Inst{31-26} = 0x36; //encoding
444 let Inst{39-32} = addr;
445 let Inst{47-40} = data0;
446 let Inst{55-48} = data1;
447 let Inst{63-56} = vdst;
450 class MUBUFe <bits<7> op> : Enc64 {
464 let Inst{11-0} = offset;
465 let Inst{12} = offen;
466 let Inst{13} = idxen;
468 let Inst{15} = addr64;
470 let Inst{24-18} = op;
471 let Inst{31-26} = 0x38; //encoding
472 let Inst{39-32} = vaddr;
473 let Inst{47-40} = vdata;
474 let Inst{52-48} = srsrc{6-2};
477 let Inst{63-56} = soffset;
480 class MTBUFe <bits<3> op> : Enc64 {
495 let Inst{11-0} = offset;
496 let Inst{12} = offen;
497 let Inst{13} = idxen;
499 let Inst{15} = addr64;
500 let Inst{18-16} = op;
501 let Inst{22-19} = dfmt;
502 let Inst{25-23} = nfmt;
503 let Inst{31-26} = 0x3a; //encoding
504 let Inst{39-32} = vaddr;
505 let Inst{47-40} = vdata;
506 let Inst{52-48} = srsrc{6-2};
509 let Inst{63-56} = soffset;
512 class MIMGe <bits<7> op> : Enc64 {
526 let Inst{11-8} = dmask;
527 let Inst{12} = unorm;
533 let Inst{24-18} = op;
535 let Inst{31-26} = 0x3c;
536 let Inst{39-32} = vaddr;
537 let Inst{47-40} = vdata;
538 let Inst{52-48} = srsrc{6-2};
539 let Inst{57-53} = ssamp{6-2};
542 class FLATe<bits<7> op> : Enc64 {
553 let Inst{24-18} = op;
554 let Inst{31-26} = 0x37; // Encoding.
555 let Inst{39-32} = addr;
556 let Inst{47-40} = data;
557 // 54-48 is reserved.
559 let Inst{63-56} = vdst;
575 let Inst{10} = compr;
578 let Inst{31-26} = 0x3e;
579 let Inst{39-32} = vsrc0;
580 let Inst{47-40} = vsrc1;
581 let Inst{55-48} = vsrc2;
582 let Inst{63-56} = vsrc3;
585 let Uses = [EXEC] in {
587 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
588 VOP1Common <outs, ins, asm, pattern>,
590 let isCodeGenOnly = 0;
593 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
594 VOP2Common <outs, ins, asm, pattern>, VOP2e<op> {
595 let isCodeGenOnly = 0;
598 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
599 VOPCCommon <ins, asm, pattern>, VOPCe <op>;
601 class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
602 InstSI <outs, ins, asm, pattern> {
605 let hasSideEffects = 0;
608 } // End Uses = [EXEC]
610 //===----------------------------------------------------------------------===//
611 // Vector I/O operations
612 //===----------------------------------------------------------------------===//
614 class DS <dag outs, dag ins, string asm, list<dag> pattern> :
615 InstSI <outs, ins, asm, pattern> {
619 let UseNamedOperandTable = 1;
620 let Uses = [M0, EXEC];
622 // Most instruction load and store data, so set this as the default.
626 let hasSideEffects = 0;
627 let AsmMatchConverter = "cvtDS";
628 let SchedRW = [WriteLDS];
631 class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
632 InstSI<outs, ins, asm, pattern> {
639 let hasSideEffects = 0;
640 let UseNamedOperandTable = 1;
641 let AsmMatchConverter = "cvtMubuf";
642 let SchedRW = [WriteVMEM];
645 class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> :
646 InstSI<outs, ins, asm, pattern> {
653 let hasSideEffects = 0;
654 let UseNamedOperandTable = 1;
655 let SchedRW = [WriteVMEM];
658 class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
659 InstSI<outs, ins, asm, pattern>, FLATe <op> {
661 // Internally, FLAT instruction are executed as both an LDS and a
662 // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
663 // and are not considered done until both have been decremented.
667 let Uses = [EXEC, FLAT_SCR]; // M0
669 let UseNamedOperandTable = 1;
670 let hasSideEffects = 0;
671 let AsmMatchConverter = "cvtFlat";
672 let SchedRW = [WriteVMEM];
675 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
676 InstSI <outs, ins, asm, pattern>, MIMGe <op> {
683 let hasSideEffects = 0; // XXX ????