1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/Support/Debug.h"
30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
31 : AMDGPUInstrInfo(st), RI() {}
33 //===----------------------------------------------------------------------===//
34 // TargetInstrInfo callbacks
35 //===----------------------------------------------------------------------===//
37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
38 unsigned N = Node->getNumOperands();
39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
44 static SDValue findChainOperand(SDNode *Load) {
45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
50 /// \brief Returns true if both nodes have the same value for the given
51 /// operand \p Op, or if both nodes do not have this operand.
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
53 unsigned Opc0 = N0->getMachineOpcode();
54 unsigned Opc1 = N1->getMachineOpcode();
56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59 if (Op0Idx == -1 && Op1Idx == -1)
63 if ((Op0Idx == -1 && Op1Idx != -1) ||
64 (Op1Idx == -1 && Op0Idx != -1))
67 // getNamedOperandIdx returns the index for the MachineInstr's operands,
68 // which includes the result as the first operand. We are indexing into the
69 // MachineSDNode's operands, so we need to skip the result operand to get
74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
77 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
78 AliasAnalysis *AA) const {
79 // TODO: The generic check fails for VALU instructions that should be
80 // rematerializable due to implicit reads of exec. We really want all of the
81 // generic logic for this except for this.
82 switch (MI->getOpcode()) {
83 case AMDGPU::V_MOV_B32_e32:
84 case AMDGPU::V_MOV_B32_e64:
85 case AMDGPU::V_MOV_B64_PSEUDO:
92 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
94 int64_t &Offset1) const {
95 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
98 unsigned Opc0 = Load0->getMachineOpcode();
99 unsigned Opc1 = Load1->getMachineOpcode();
101 // Make sure both are actually loads.
102 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
105 if (isDS(Opc0) && isDS(Opc1)) {
107 // FIXME: Handle this case:
108 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
112 if (Load0->getOperand(1) != Load1->getOperand(1))
116 if (findChainOperand(Load0) != findChainOperand(Load1))
119 // Skip read2 / write2 variants for simplicity.
120 // TODO: We should report true if the used offsets are adjacent (excluded
122 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
123 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
126 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
127 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
131 if (isSMRD(Opc0) && isSMRD(Opc1)) {
132 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
135 if (Load0->getOperand(0) != Load1->getOperand(0))
138 const ConstantSDNode *Load0Offset =
139 dyn_cast<ConstantSDNode>(Load0->getOperand(1));
140 const ConstantSDNode *Load1Offset =
141 dyn_cast<ConstantSDNode>(Load1->getOperand(1));
143 if (!Load0Offset || !Load1Offset)
147 if (findChainOperand(Load0) != findChainOperand(Load1))
150 Offset0 = Load0Offset->getZExtValue();
151 Offset1 = Load1Offset->getZExtValue();
155 // MUBUF and MTBUF can access the same addresses.
156 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
158 // MUBUF and MTBUF have vaddr at different indices.
159 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
160 findChainOperand(Load0) != findChainOperand(Load1) ||
161 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
162 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
165 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
166 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
168 if (OffIdx0 == -1 || OffIdx1 == -1)
171 // getNamedOperandIdx returns the index for MachineInstrs. Since they
172 // inlcude the output in the operand list, but SDNodes don't, we need to
173 // subtract the index by one.
177 SDValue Off0 = Load0->getOperand(OffIdx0);
178 SDValue Off1 = Load1->getOperand(OffIdx1);
180 // The offset might be a FrameIndexSDNode.
181 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
184 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
185 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
192 static bool isStride64(unsigned Opc) {
194 case AMDGPU::DS_READ2ST64_B32:
195 case AMDGPU::DS_READ2ST64_B64:
196 case AMDGPU::DS_WRITE2ST64_B32:
197 case AMDGPU::DS_WRITE2ST64_B64:
204 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
206 const TargetRegisterInfo *TRI) const {
207 unsigned Opc = LdSt->getOpcode();
210 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
211 AMDGPU::OpName::offset);
213 // Normal, single offset LDS instruction.
214 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
215 AMDGPU::OpName::addr);
217 BaseReg = AddrReg->getReg();
218 Offset = OffsetImm->getImm();
222 // The 2 offset instructions use offset0 and offset1 instead. We can treat
223 // these as a load with a single offset if the 2 offsets are consecutive. We
224 // will use this for some partially aligned loads.
225 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
226 AMDGPU::OpName::offset0);
227 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
228 AMDGPU::OpName::offset1);
230 uint8_t Offset0 = Offset0Imm->getImm();
231 uint8_t Offset1 = Offset1Imm->getImm();
233 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
234 // Each of these offsets is in element sized units, so we need to convert
235 // to bytes of the individual reads.
239 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
241 assert(LdSt->mayStore());
242 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
243 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
249 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
250 AMDGPU::OpName::addr);
251 BaseReg = AddrReg->getReg();
252 Offset = EltSize * Offset0;
259 if (isMUBUF(*LdSt) || isMTBUF(*LdSt)) {
260 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
263 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
264 AMDGPU::OpName::vaddr);
268 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
269 AMDGPU::OpName::offset);
270 BaseReg = AddrReg->getReg();
271 Offset = OffsetImm->getImm();
276 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
277 AMDGPU::OpName::offset);
281 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
282 AMDGPU::OpName::sbase);
283 BaseReg = SBaseReg->getReg();
284 Offset = OffsetImm->getImm();
291 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
292 MachineInstr *SecondLdSt,
293 unsigned NumLoads) const {
294 // TODO: This needs finer tuning
298 if (isDS(*FirstLdSt) && isDS(*SecondLdSt))
301 if (isSMRD(*FirstLdSt) && isSMRD(*SecondLdSt))
304 if ((isMUBUF(*FirstLdSt) || isMTBUF(*FirstLdSt)) &&
305 (isMUBUF(*SecondLdSt) || isMTBUF(*SecondLdSt)))
312 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
313 MachineBasicBlock::iterator MI, DebugLoc DL,
314 unsigned DestReg, unsigned SrcReg,
315 bool KillSrc) const {
317 // If we are trying to copy to or from SCC, there is a bug somewhere else in
318 // the backend. While it may be theoretically possible to do this, it should
319 // never be necessary.
320 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
322 static const int16_t Sub0_15[] = {
323 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
324 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
325 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
326 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
329 static const int16_t Sub0_7[] = {
330 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
331 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
334 static const int16_t Sub0_3[] = {
335 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
338 static const int16_t Sub0_2[] = {
339 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
342 static const int16_t Sub0_1[] = {
343 AMDGPU::sub0, AMDGPU::sub1, 0
347 const int16_t *SubIndices;
349 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
350 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
351 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
352 .addReg(SrcReg, getKillRegState(KillSrc));
355 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
356 if (DestReg == AMDGPU::VCC) {
357 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
358 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
359 .addReg(SrcReg, getKillRegState(KillSrc));
361 // FIXME: Hack until VReg_1 removed.
362 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
363 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32))
365 .addReg(SrcReg, getKillRegState(KillSrc));
371 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
372 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
373 .addReg(SrcReg, getKillRegState(KillSrc));
376 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
377 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
378 Opcode = AMDGPU::S_MOV_B32;
381 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
382 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
383 Opcode = AMDGPU::S_MOV_B32;
386 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
387 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
388 Opcode = AMDGPU::S_MOV_B32;
389 SubIndices = Sub0_15;
391 } else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) {
392 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
393 AMDGPU::SReg_32RegClass.contains(SrcReg));
394 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
395 .addReg(SrcReg, getKillRegState(KillSrc));
398 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
399 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
400 AMDGPU::SReg_64RegClass.contains(SrcReg));
401 Opcode = AMDGPU::V_MOV_B32_e32;
404 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
405 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
406 Opcode = AMDGPU::V_MOV_B32_e32;
409 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
410 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
411 AMDGPU::SReg_128RegClass.contains(SrcReg));
412 Opcode = AMDGPU::V_MOV_B32_e32;
415 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
416 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
417 AMDGPU::SReg_256RegClass.contains(SrcReg));
418 Opcode = AMDGPU::V_MOV_B32_e32;
421 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
422 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
423 AMDGPU::SReg_512RegClass.contains(SrcReg));
424 Opcode = AMDGPU::V_MOV_B32_e32;
425 SubIndices = Sub0_15;
428 llvm_unreachable("Can't copy register!");
431 while (unsigned SubIdx = *SubIndices++) {
432 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
433 get(Opcode), RI.getSubReg(DestReg, SubIdx));
435 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
438 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
442 int SIInstrInfo::commuteOpcode(const MachineInstr &MI) const {
443 const unsigned Opcode = MI.getOpcode();
447 // Try to map original to commuted opcode
448 NewOpc = AMDGPU::getCommuteRev(Opcode);
450 // Check if the commuted (REV) opcode exists on the target.
451 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
453 // Try to map commuted to original opcode
454 NewOpc = AMDGPU::getCommuteOrig(Opcode);
456 // Check if the original (non-REV) opcode exists on the target.
457 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
462 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
464 if (DstRC->getSize() == 4) {
465 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
466 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
467 return AMDGPU::S_MOV_B64;
468 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
469 return AMDGPU::V_MOV_B64_PSEUDO;
474 static unsigned getSGPRSpillSaveOpcode(unsigned Size) {
477 return AMDGPU::SI_SPILL_S32_SAVE;
479 return AMDGPU::SI_SPILL_S64_SAVE;
481 return AMDGPU::SI_SPILL_S128_SAVE;
483 return AMDGPU::SI_SPILL_S256_SAVE;
485 return AMDGPU::SI_SPILL_S512_SAVE;
487 llvm_unreachable("unknown register size");
491 static unsigned getVGPRSpillSaveOpcode(unsigned Size) {
494 return AMDGPU::SI_SPILL_V32_SAVE;
496 return AMDGPU::SI_SPILL_V64_SAVE;
498 return AMDGPU::SI_SPILL_V128_SAVE;
500 return AMDGPU::SI_SPILL_V256_SAVE;
502 return AMDGPU::SI_SPILL_V512_SAVE;
504 llvm_unreachable("unknown register size");
508 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
509 MachineBasicBlock::iterator MI,
510 unsigned SrcReg, bool isKill,
512 const TargetRegisterClass *RC,
513 const TargetRegisterInfo *TRI) const {
514 MachineFunction *MF = MBB.getParent();
515 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
516 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
517 DebugLoc DL = MBB.findDebugLoc(MI);
519 unsigned Size = FrameInfo->getObjectSize(FrameIndex);
520 unsigned Align = FrameInfo->getObjectAlignment(FrameIndex);
521 MachinePointerInfo PtrInfo
522 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
523 MachineMemOperand *MMO
524 = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
527 if (RI.isSGPRClass(RC)) {
528 MFI->setHasSpilledSGPRs();
530 // We are only allowed to create one new instruction when spilling
531 // registers, so we need to use pseudo instruction for spilling
533 unsigned Opcode = getSGPRSpillSaveOpcode(RC->getSize());
534 BuildMI(MBB, MI, DL, get(Opcode))
535 .addReg(SrcReg) // src
536 .addFrameIndex(FrameIndex) // frame_idx
542 if (!ST.isVGPRSpillingEnabled(MFI)) {
543 LLVMContext &Ctx = MF->getFunction()->getContext();
544 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
546 BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
552 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
554 unsigned ScratchOffsetPreloadReg = RI.getPreloadedValue(
555 *MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
557 unsigned Opcode = getVGPRSpillSaveOpcode(RC->getSize());
558 MFI->setHasSpilledVGPRs();
559 BuildMI(MBB, MI, DL, get(Opcode))
560 .addReg(SrcReg) // src
561 .addFrameIndex(FrameIndex) // frame_idx
562 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
563 .addReg(ScratchOffsetPreloadReg) // scratch_offset
567 static unsigned getSGPRSpillRestoreOpcode(unsigned Size) {
570 return AMDGPU::SI_SPILL_S32_RESTORE;
572 return AMDGPU::SI_SPILL_S64_RESTORE;
574 return AMDGPU::SI_SPILL_S128_RESTORE;
576 return AMDGPU::SI_SPILL_S256_RESTORE;
578 return AMDGPU::SI_SPILL_S512_RESTORE;
580 llvm_unreachable("unknown register size");
584 static unsigned getVGPRSpillRestoreOpcode(unsigned Size) {
587 return AMDGPU::SI_SPILL_V32_RESTORE;
589 return AMDGPU::SI_SPILL_V64_RESTORE;
591 return AMDGPU::SI_SPILL_V128_RESTORE;
593 return AMDGPU::SI_SPILL_V256_RESTORE;
595 return AMDGPU::SI_SPILL_V512_RESTORE;
597 llvm_unreachable("unknown register size");
601 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
602 MachineBasicBlock::iterator MI,
603 unsigned DestReg, int FrameIndex,
604 const TargetRegisterClass *RC,
605 const TargetRegisterInfo *TRI) const {
606 MachineFunction *MF = MBB.getParent();
607 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
608 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
609 DebugLoc DL = MBB.findDebugLoc(MI);
610 unsigned Align = FrameInfo->getObjectAlignment(FrameIndex);
611 unsigned Size = FrameInfo->getObjectSize(FrameIndex);
613 MachinePointerInfo PtrInfo
614 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
616 MachineMemOperand *MMO = MF->getMachineMemOperand(
617 PtrInfo, MachineMemOperand::MOLoad, Size, Align);
619 if (RI.isSGPRClass(RC)) {
620 // FIXME: Maybe this should not include a memoperand because it will be
621 // lowered to non-memory instructions.
622 unsigned Opcode = getSGPRSpillRestoreOpcode(RC->getSize());
623 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
624 .addFrameIndex(FrameIndex) // frame_idx
630 if (!ST.isVGPRSpillingEnabled(MFI)) {
631 LLVMContext &Ctx = MF->getFunction()->getContext();
632 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
633 " restore register");
634 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
639 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
641 unsigned ScratchOffsetPreloadReg = RI.getPreloadedValue(
642 *MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
644 unsigned Opcode = getVGPRSpillRestoreOpcode(RC->getSize());
645 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
646 .addFrameIndex(FrameIndex) // frame_idx
647 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
648 .addReg(ScratchOffsetPreloadReg) // scratch_offset
652 /// \param @Offset Offset in bytes of the FrameIndex being spilled
653 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
654 MachineBasicBlock::iterator MI,
655 RegScavenger *RS, unsigned TmpReg,
656 unsigned FrameOffset,
657 unsigned Size) const {
658 MachineFunction *MF = MBB.getParent();
659 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
660 const AMDGPUSubtarget &ST = MF->getSubtarget<AMDGPUSubtarget>();
661 const SIRegisterInfo *TRI =
662 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
663 DebugLoc DL = MBB.findDebugLoc(MI);
664 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
665 unsigned WavefrontSize = ST.getWavefrontSize();
667 unsigned TIDReg = MFI->getTIDReg();
668 if (!MFI->hasCalculatedTID()) {
669 MachineBasicBlock &Entry = MBB.getParent()->front();
670 MachineBasicBlock::iterator Insert = Entry.front();
671 DebugLoc DL = Insert->getDebugLoc();
673 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
674 if (TIDReg == AMDGPU::NoRegister)
678 if (MFI->getShaderType() == ShaderType::COMPUTE &&
679 WorkGroupSize > WavefrontSize) {
682 = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_X);
684 = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_Y);
686 = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_Z);
687 unsigned InputPtrReg =
688 TRI->getPreloadedValue(*MF, SIRegisterInfo::KERNARG_SEGMENT_PTR);
689 for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) {
690 if (!Entry.isLiveIn(Reg))
691 Entry.addLiveIn(Reg);
694 RS->enterBasicBlock(&Entry);
695 // FIXME: Can we scavenge an SReg_64 and access the subregs?
696 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
697 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
698 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
700 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
701 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
703 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
705 // NGROUPS.X * NGROUPS.Y
706 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
709 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
710 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
713 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
714 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
718 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
719 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
724 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
729 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
735 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
739 MFI->setTIDReg(TIDReg);
742 // Add FrameIndex to LDS offset
743 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
744 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
751 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
760 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
765 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
766 MachineBasicBlock &MBB = *MI->getParent();
767 DebugLoc DL = MBB.findDebugLoc(MI);
768 switch (MI->getOpcode()) {
769 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
771 case AMDGPU::SI_CONSTDATA_PTR: {
772 unsigned Reg = MI->getOperand(0).getReg();
773 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
774 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
776 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
778 // Add 32-bit offset from this instruction to the start of the constant data.
779 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo)
781 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
782 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
783 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
786 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
787 .addReg(AMDGPU::SCC, RegState::Implicit);
788 MI->eraseFromParent();
791 case AMDGPU::SGPR_USE:
792 // This is just a placeholder for register allocation.
793 MI->eraseFromParent();
796 case AMDGPU::V_MOV_B64_PSEUDO: {
797 unsigned Dst = MI->getOperand(0).getReg();
798 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
799 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
801 const MachineOperand &SrcOp = MI->getOperand(1);
802 // FIXME: Will this work for 64-bit floating point immediates?
803 assert(!SrcOp.isFPImm());
805 APInt Imm(64, SrcOp.getImm());
806 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
807 .addImm(Imm.getLoBits(32).getZExtValue())
808 .addReg(Dst, RegState::Implicit);
809 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
810 .addImm(Imm.getHiBits(32).getZExtValue())
811 .addReg(Dst, RegState::Implicit);
813 assert(SrcOp.isReg());
814 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
815 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
816 .addReg(Dst, RegState::Implicit);
817 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
818 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
819 .addReg(Dst, RegState::Implicit);
821 MI->eraseFromParent();
825 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
826 unsigned Dst = MI->getOperand(0).getReg();
827 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
828 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
829 unsigned Src0 = MI->getOperand(1).getReg();
830 unsigned Src1 = MI->getOperand(2).getReg();
831 const MachineOperand &SrcCond = MI->getOperand(3);
833 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
834 .addReg(RI.getSubReg(Src0, AMDGPU::sub0))
835 .addReg(RI.getSubReg(Src1, AMDGPU::sub0))
836 .addOperand(SrcCond);
837 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
838 .addReg(RI.getSubReg(Src0, AMDGPU::sub1))
839 .addReg(RI.getSubReg(Src1, AMDGPU::sub1))
840 .addOperand(SrcCond);
841 MI->eraseFromParent();
848 /// Commutes the operands in the given instruction.
849 /// The commutable operands are specified by their indices OpIdx0 and OpIdx1.
851 /// Do not call this method for a non-commutable instruction or for
852 /// non-commutable pair of operand indices OpIdx0 and OpIdx1.
853 /// Even though the instruction is commutable, the method may still
854 /// fail to commute the operands, null pointer is returned in such cases.
855 MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr *MI,
858 unsigned OpIdx1) const {
859 int CommutedOpcode = commuteOpcode(*MI);
860 if (CommutedOpcode == -1)
863 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
864 AMDGPU::OpName::src0);
865 MachineOperand &Src0 = MI->getOperand(Src0Idx);
869 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
870 AMDGPU::OpName::src1);
872 if ((OpIdx0 != static_cast<unsigned>(Src0Idx) ||
873 OpIdx1 != static_cast<unsigned>(Src1Idx)) &&
874 (OpIdx0 != static_cast<unsigned>(Src1Idx) ||
875 OpIdx1 != static_cast<unsigned>(Src0Idx)))
878 MachineOperand &Src1 = MI->getOperand(Src1Idx);
880 // Make sure it's legal to commute operands for VOP2.
882 (!isOperandLegal(MI, Src0Idx, &Src1) ||
883 !isOperandLegal(MI, Src1Idx, &Src0))) {
888 // Allow commuting instructions with Imm operands.
889 if (NewMI || !Src1.isImm() ||
890 (!isVOP2(*MI) && !isVOP3(*MI))) {
894 // Be sure to copy the source modifiers to the right place.
895 if (MachineOperand *Src0Mods
896 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
897 MachineOperand *Src1Mods
898 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers);
900 int Src0ModsVal = Src0Mods->getImm();
901 if (!Src1Mods && Src0ModsVal != 0)
904 // XXX - This assert might be a lie. It might be useful to have a neg
905 // modifier with 0.0.
906 int Src1ModsVal = Src1Mods->getImm();
907 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates");
909 Src1Mods->setImm(Src0ModsVal);
910 Src0Mods->setImm(Src1ModsVal);
913 unsigned Reg = Src0.getReg();
914 unsigned SubReg = Src0.getSubReg();
916 Src0.ChangeToImmediate(Src1.getImm());
918 llvm_unreachable("Should only have immediates");
920 Src1.ChangeToRegister(Reg, false);
921 Src1.setSubReg(SubReg);
923 MI = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx0, OpIdx1);
927 MI->setDesc(get(CommutedOpcode));
932 // This needs to be implemented because the source modifiers may be inserted
933 // between the true commutable operands, and the base
934 // TargetInstrInfo::commuteInstruction uses it.
935 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
937 unsigned &SrcOpIdx1) const {
938 const MCInstrDesc &MCID = MI->getDesc();
939 if (!MCID.isCommutable())
942 unsigned Opc = MI->getOpcode();
943 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
947 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on
948 // immediate. Also, immediate src0 operand is not handled in
949 // SIInstrInfo::commuteInstruction();
950 if (!MI->getOperand(Src0Idx).isReg())
953 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
957 MachineOperand &Src1 = MI->getOperand(Src1Idx);
959 // SIInstrInfo::commuteInstruction() does support commuting the immediate
960 // operand src1 in 2 and 3 operand instructions.
961 if (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))
963 } else if (Src1.isReg()) {
964 // If any source modifiers are set, the generic instruction commuting won't
965 // understand how to copy the source modifiers.
966 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) ||
967 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers))
972 return fixCommutedOpIndices(SrcOpIdx0, SrcOpIdx1, Src0Idx, Src1Idx);
975 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
976 MachineBasicBlock::iterator I,
978 unsigned SrcReg) const {
979 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
980 DstReg) .addReg(SrcReg);
983 bool SIInstrInfo::isMov(unsigned Opcode) const {
985 default: return false;
986 case AMDGPU::S_MOV_B32:
987 case AMDGPU::S_MOV_B64:
988 case AMDGPU::V_MOV_B32_e32:
989 case AMDGPU::V_MOV_B32_e64:
994 static void removeModOperands(MachineInstr &MI) {
995 unsigned Opc = MI.getOpcode();
996 int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc,
997 AMDGPU::OpName::src0_modifiers);
998 int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc,
999 AMDGPU::OpName::src1_modifiers);
1000 int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
1001 AMDGPU::OpName::src2_modifiers);
1003 MI.RemoveOperand(Src2ModIdx);
1004 MI.RemoveOperand(Src1ModIdx);
1005 MI.RemoveOperand(Src0ModIdx);
1008 bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
1009 unsigned Reg, MachineRegisterInfo *MRI) const {
1010 if (!MRI->hasOneNonDBGUse(Reg))
1013 unsigned Opc = UseMI->getOpcode();
1014 if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64) {
1015 // Don't fold if we are using source modifiers. The new VOP2 instructions
1017 if (hasModifiersSet(*UseMI, AMDGPU::OpName::src0_modifiers) ||
1018 hasModifiersSet(*UseMI, AMDGPU::OpName::src1_modifiers) ||
1019 hasModifiersSet(*UseMI, AMDGPU::OpName::src2_modifiers)) {
1023 MachineOperand *Src0 = getNamedOperand(*UseMI, AMDGPU::OpName::src0);
1024 MachineOperand *Src1 = getNamedOperand(*UseMI, AMDGPU::OpName::src1);
1025 MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2);
1027 // Multiplied part is the constant: Use v_madmk_f32
1028 // We should only expect these to be on src0 due to canonicalizations.
1029 if (Src0->isReg() && Src0->getReg() == Reg) {
1030 if (!Src1->isReg() ||
1031 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
1034 if (!Src2->isReg() ||
1035 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))))
1038 // We need to do some weird looking operand shuffling since the madmk
1039 // operands are out of the normal expected order with the multiplied
1040 // constant as the last operand.
1042 // v_mad_f32 src0, src1, src2 -> v_madmk_f32 src0 * src2K + src1
1047 const int64_t Imm = DefMI->getOperand(1).getImm();
1049 // FIXME: This would be a lot easier if we could return a new instruction
1050 // instead of having to modify in place.
1052 // Remove these first since they are at the end.
1053 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1054 AMDGPU::OpName::omod));
1055 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1056 AMDGPU::OpName::clamp));
1058 unsigned Src1Reg = Src1->getReg();
1059 unsigned Src1SubReg = Src1->getSubReg();
1060 unsigned Src2Reg = Src2->getReg();
1061 unsigned Src2SubReg = Src2->getSubReg();
1062 Src0->setReg(Src1Reg);
1063 Src0->setSubReg(Src1SubReg);
1064 Src0->setIsKill(Src1->isKill());
1066 Src1->setReg(Src2Reg);
1067 Src1->setSubReg(Src2SubReg);
1068 Src1->setIsKill(Src2->isKill());
1070 if (Opc == AMDGPU::V_MAC_F32_e64) {
1071 UseMI->untieRegOperand(
1072 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
1075 Src2->ChangeToImmediate(Imm);
1077 removeModOperands(*UseMI);
1078 UseMI->setDesc(get(AMDGPU::V_MADMK_F32));
1080 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1082 DefMI->eraseFromParent();
1087 // Added part is the constant: Use v_madak_f32
1088 if (Src2->isReg() && Src2->getReg() == Reg) {
1089 // Not allowed to use constant bus for another operand.
1090 // We can however allow an inline immediate as src0.
1091 if (!Src0->isImm() &&
1092 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))
1095 if (!Src1->isReg() ||
1096 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
1099 const int64_t Imm = DefMI->getOperand(1).getImm();
1101 // FIXME: This would be a lot easier if we could return a new instruction
1102 // instead of having to modify in place.
1104 // Remove these first since they are at the end.
1105 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1106 AMDGPU::OpName::omod));
1107 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1108 AMDGPU::OpName::clamp));
1110 if (Opc == AMDGPU::V_MAC_F32_e64) {
1111 UseMI->untieRegOperand(
1112 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
1115 // ChangingToImmediate adds Src2 back to the instruction.
1116 Src2->ChangeToImmediate(Imm);
1118 // These come before src2.
1119 removeModOperands(*UseMI);
1120 UseMI->setDesc(get(AMDGPU::V_MADAK_F32));
1122 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1124 DefMI->eraseFromParent();
1133 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
1134 int WidthB, int OffsetB) {
1135 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1136 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1137 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1138 return LowOffset + LowWidth <= HighOffset;
1141 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
1142 MachineInstr *MIb) const {
1143 unsigned BaseReg0, Offset0;
1144 unsigned BaseReg1, Offset1;
1146 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) &&
1147 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) {
1148 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() &&
1149 "read2 / write2 not expected here yet");
1150 unsigned Width0 = (*MIa->memoperands_begin())->getSize();
1151 unsigned Width1 = (*MIb->memoperands_begin())->getSize();
1152 if (BaseReg0 == BaseReg1 &&
1153 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
1161 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
1163 AliasAnalysis *AA) const {
1164 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1165 "MIa must load from or modify a memory location");
1166 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
1167 "MIb must load from or modify a memory location");
1169 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects())
1172 // XXX - Can we relax this between address spaces?
1173 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
1176 // TODO: Should we check the address space from the MachineMemOperand? That
1177 // would allow us to distinguish objects we know don't alias based on the
1178 // underlying address space, even if it was lowered to a different one,
1179 // e.g. private accesses lowered to use MUBUF instructions on a scratch
1183 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1185 return !isFLAT(*MIb);
1188 if (isMUBUF(*MIa) || isMTBUF(*MIa)) {
1189 if (isMUBUF(*MIb) || isMTBUF(*MIb))
1190 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1192 return !isFLAT(*MIb) && !isSMRD(*MIb);
1197 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1199 return !isFLAT(*MIb) && !isMUBUF(*MIa) && !isMTBUF(*MIa);
1204 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1212 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
1213 MachineBasicBlock::iterator &MI,
1214 LiveVariables *LV) const {
1216 switch (MI->getOpcode()) {
1217 default: return nullptr;
1218 case AMDGPU::V_MAC_F32_e64: break;
1219 case AMDGPU::V_MAC_F32_e32: {
1220 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1221 if (Src0->isImm() && !isInlineConstant(*Src0, 4))
1227 const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::dst);
1228 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1229 const MachineOperand *Src1 = getNamedOperand(*MI, AMDGPU::OpName::src1);
1230 const MachineOperand *Src2 = getNamedOperand(*MI, AMDGPU::OpName::src2);
1232 return BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_MAD_F32))
1234 .addImm(0) // Src0 mods
1236 .addImm(0) // Src1 mods
1238 .addImm(0) // Src mods
1244 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
1245 int64_t SVal = Imm.getSExtValue();
1246 if (SVal >= -16 && SVal <= 64)
1249 if (Imm.getBitWidth() == 64) {
1250 uint64_t Val = Imm.getZExtValue();
1251 return (DoubleToBits(0.0) == Val) ||
1252 (DoubleToBits(1.0) == Val) ||
1253 (DoubleToBits(-1.0) == Val) ||
1254 (DoubleToBits(0.5) == Val) ||
1255 (DoubleToBits(-0.5) == Val) ||
1256 (DoubleToBits(2.0) == Val) ||
1257 (DoubleToBits(-2.0) == Val) ||
1258 (DoubleToBits(4.0) == Val) ||
1259 (DoubleToBits(-4.0) == Val);
1262 // The actual type of the operand does not seem to matter as long
1263 // as the bits match one of the inline immediate values. For example:
1265 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
1266 // so it is a legal inline immediate.
1268 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
1269 // floating-point, so it is a legal inline immediate.
1270 uint32_t Val = Imm.getZExtValue();
1272 return (FloatToBits(0.0f) == Val) ||
1273 (FloatToBits(1.0f) == Val) ||
1274 (FloatToBits(-1.0f) == Val) ||
1275 (FloatToBits(0.5f) == Val) ||
1276 (FloatToBits(-0.5f) == Val) ||
1277 (FloatToBits(2.0f) == Val) ||
1278 (FloatToBits(-2.0f) == Val) ||
1279 (FloatToBits(4.0f) == Val) ||
1280 (FloatToBits(-4.0f) == Val);
1283 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
1284 unsigned OpSize) const {
1286 // MachineOperand provides no way to tell the true operand size, since it
1287 // only records a 64-bit value. We need to know the size to determine if a
1288 // 32-bit floating point immediate bit pattern is legal for an integer
1289 // immediate. It would be for any 32-bit integer operand, but would not be
1290 // for a 64-bit one.
1292 unsigned BitSize = 8 * OpSize;
1293 return isInlineConstant(APInt(BitSize, MO.getImm(), true));
1299 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO,
1300 unsigned OpSize) const {
1301 return MO.isImm() && !isInlineConstant(MO, OpSize);
1304 static bool compareMachineOp(const MachineOperand &Op0,
1305 const MachineOperand &Op1) {
1306 if (Op0.getType() != Op1.getType())
1309 switch (Op0.getType()) {
1310 case MachineOperand::MO_Register:
1311 return Op0.getReg() == Op1.getReg();
1312 case MachineOperand::MO_Immediate:
1313 return Op0.getImm() == Op1.getImm();
1315 llvm_unreachable("Didn't expect to be comparing these operand types");
1319 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
1320 const MachineOperand &MO) const {
1321 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1323 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
1325 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
1328 if (OpInfo.RegClass < 0)
1331 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize();
1332 if (isLiteralConstant(MO, OpSize))
1333 return RI.opCanUseLiteralConstant(OpInfo.OperandType);
1335 return RI.opCanUseInlineConstant(OpInfo.OperandType);
1338 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1339 int Op32 = AMDGPU::getVOPe32(Opcode);
1343 return pseudoToMCOpcode(Op32) != -1;
1346 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
1347 // The src0_modifier operand is present on all instructions
1348 // that have modifiers.
1350 return AMDGPU::getNamedOperandIdx(Opcode,
1351 AMDGPU::OpName::src0_modifiers) != -1;
1354 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
1355 unsigned OpName) const {
1356 const MachineOperand *Mods = getNamedOperand(MI, OpName);
1357 return Mods && Mods->getImm();
1360 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
1361 const MachineOperand &MO,
1362 unsigned OpSize) const {
1363 // Literal constants use the constant bus.
1364 if (isLiteralConstant(MO, OpSize))
1367 if (!MO.isReg() || !MO.isUse())
1370 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1371 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
1373 // FLAT_SCR is just an SGPR pair.
1374 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
1377 // EXEC register uses the constant bus.
1378 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
1381 // SGPRs use the constant bus
1382 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
1383 (!MO.isImplicit() &&
1384 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
1385 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
1392 static unsigned findImplicitSGPRRead(const MachineInstr &MI) {
1393 for (const MachineOperand &MO : MI.implicit_operands()) {
1394 // We only care about reads.
1398 switch (MO.getReg()) {
1401 case AMDGPU::FLAT_SCR:
1409 return AMDGPU::NoRegister;
1412 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1413 StringRef &ErrInfo) const {
1414 uint16_t Opcode = MI->getOpcode();
1415 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1416 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1417 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
1418 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
1420 // Make sure the number of operands is correct.
1421 const MCInstrDesc &Desc = get(Opcode);
1422 if (!Desc.isVariadic() &&
1423 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
1424 ErrInfo = "Instruction has wrong number of operands.";
1428 // Make sure the register classes are correct
1429 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
1430 if (MI->getOperand(i).isFPImm()) {
1431 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
1432 "all fp values to integers.";
1436 int RegClass = Desc.OpInfo[i].RegClass;
1438 switch (Desc.OpInfo[i].OperandType) {
1439 case MCOI::OPERAND_REGISTER:
1440 if (MI->getOperand(i).isImm()) {
1441 ErrInfo = "Illegal immediate value for operand.";
1445 case AMDGPU::OPERAND_REG_IMM32:
1447 case AMDGPU::OPERAND_REG_INLINE_C:
1448 if (isLiteralConstant(MI->getOperand(i),
1449 RI.getRegClass(RegClass)->getSize())) {
1450 ErrInfo = "Illegal immediate value for operand.";
1454 case MCOI::OPERAND_IMMEDIATE:
1455 // Check if this operand is an immediate.
1456 // FrameIndex operands will be replaced by immediates, so they are
1458 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFI()) {
1459 ErrInfo = "Expected immediate, but got non-immediate";
1467 if (!MI->getOperand(i).isReg())
1470 if (RegClass != -1) {
1471 unsigned Reg = MI->getOperand(i).getReg();
1472 if (TargetRegisterInfo::isVirtualRegister(Reg))
1475 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1476 if (!RC->contains(Reg)) {
1477 ErrInfo = "Operand has incorrect register class.";
1485 if (isVOP1(*MI) || isVOP2(*MI) || isVOP3(*MI) || isVOPC(*MI)) {
1486 // Only look at the true operands. Only a real operand can use the constant
1487 // bus, and we don't want to check pseudo-operands like the source modifier
1489 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
1491 unsigned ConstantBusCount = 0;
1492 unsigned SGPRUsed = findImplicitSGPRRead(*MI);
1493 if (SGPRUsed != AMDGPU::NoRegister)
1496 for (int OpIdx : OpIndices) {
1499 const MachineOperand &MO = MI->getOperand(OpIdx);
1500 if (usesConstantBus(MRI, MO, getOpSize(Opcode, OpIdx))) {
1502 if (MO.getReg() != SGPRUsed)
1504 SGPRUsed = MO.getReg();
1510 if (ConstantBusCount > 1) {
1511 ErrInfo = "VOP* instruction uses the constant bus more than once";
1516 // Verify misc. restrictions on specific instructions.
1517 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1518 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1519 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1520 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1521 const MachineOperand &Src2 = MI->getOperand(Src2Idx);
1522 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1523 if (!compareMachineOp(Src0, Src1) &&
1524 !compareMachineOp(Src0, Src2)) {
1525 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1531 // Make sure we aren't losing exec uses in the td files. This mostly requires
1532 // being careful when using let Uses to try to add other use registers.
1533 if (!isGenericOpcode(Opcode) && !isSALU(Opcode) && !isSMRD(Opcode)) {
1534 const MachineOperand *Exec = MI->findRegisterUseOperand(AMDGPU::EXEC);
1535 if (!Exec || !Exec->isImplicit()) {
1536 ErrInfo = "VALU instruction does not implicitly read exec mask";
1544 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1545 switch (MI.getOpcode()) {
1546 default: return AMDGPU::INSTRUCTION_LIST_END;
1547 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1548 case AMDGPU::COPY: return AMDGPU::COPY;
1549 case AMDGPU::PHI: return AMDGPU::PHI;
1550 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1551 case AMDGPU::S_MOV_B32:
1552 return MI.getOperand(1).isReg() ?
1553 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1554 case AMDGPU::S_ADD_I32:
1555 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1556 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1557 case AMDGPU::S_SUB_I32:
1558 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1559 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1560 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1561 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1562 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1563 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1564 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1565 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1566 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1567 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1568 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1569 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1570 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1571 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1572 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1573 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1574 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1575 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1576 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1577 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1578 case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64;
1579 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1580 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1581 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1582 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1583 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1584 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1585 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1586 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1587 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1588 case AMDGPU::S_LOAD_DWORD_IMM:
1589 case AMDGPU::S_LOAD_DWORD_SGPR:
1590 case AMDGPU::S_LOAD_DWORD_IMM_ci:
1591 return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1592 case AMDGPU::S_LOAD_DWORDX2_IMM:
1593 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1594 case AMDGPU::S_LOAD_DWORDX2_IMM_ci:
1595 return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1596 case AMDGPU::S_LOAD_DWORDX4_IMM:
1597 case AMDGPU::S_LOAD_DWORDX4_SGPR:
1598 case AMDGPU::S_LOAD_DWORDX4_IMM_ci:
1599 return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1600 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
1601 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1602 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1603 case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
1607 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1608 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1611 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1612 unsigned OpNo) const {
1613 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1614 const MCInstrDesc &Desc = get(MI.getOpcode());
1615 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1616 Desc.OpInfo[OpNo].RegClass == -1) {
1617 unsigned Reg = MI.getOperand(OpNo).getReg();
1619 if (TargetRegisterInfo::isVirtualRegister(Reg))
1620 return MRI.getRegClass(Reg);
1621 return RI.getPhysRegClass(Reg);
1624 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1625 return RI.getRegClass(RCID);
1628 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1629 switch (MI.getOpcode()) {
1631 case AMDGPU::REG_SEQUENCE:
1633 case AMDGPU::INSERT_SUBREG:
1634 return RI.hasVGPRs(getOpRegClass(MI, 0));
1636 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1640 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1641 MachineBasicBlock::iterator I = MI;
1642 MachineBasicBlock *MBB = MI->getParent();
1643 MachineOperand &MO = MI->getOperand(OpIdx);
1644 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1645 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1646 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1647 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1649 Opcode = AMDGPU::COPY;
1650 else if (RI.isSGPRClass(RC))
1651 Opcode = AMDGPU::S_MOV_B32;
1654 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1655 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
1656 VRC = &AMDGPU::VReg_64RegClass;
1658 VRC = &AMDGPU::VGPR_32RegClass;
1660 unsigned Reg = MRI.createVirtualRegister(VRC);
1661 DebugLoc DL = MBB->findDebugLoc(I);
1662 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
1664 MO.ChangeToRegister(Reg, false);
1667 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1668 MachineRegisterInfo &MRI,
1669 MachineOperand &SuperReg,
1670 const TargetRegisterClass *SuperRC,
1672 const TargetRegisterClass *SubRC)
1674 MachineBasicBlock *MBB = MI->getParent();
1675 DebugLoc DL = MI->getDebugLoc();
1676 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1678 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) {
1679 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1680 .addReg(SuperReg.getReg(), 0, SubIdx);
1684 // Just in case the super register is itself a sub-register, copy it to a new
1685 // value so we don't need to worry about merging its subreg index with the
1686 // SubIdx passed to this function. The register coalescer should be able to
1687 // eliminate this extra copy.
1688 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1690 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
1691 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
1693 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1694 .addReg(NewSuperReg, 0, SubIdx);
1699 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1700 MachineBasicBlock::iterator MII,
1701 MachineRegisterInfo &MRI,
1703 const TargetRegisterClass *SuperRC,
1705 const TargetRegisterClass *SubRC) const {
1707 // XXX - Is there a better way to do this?
1708 if (SubIdx == AMDGPU::sub0)
1709 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1710 if (SubIdx == AMDGPU::sub1)
1711 return MachineOperand::CreateImm(Op.getImm() >> 32);
1713 llvm_unreachable("Unhandled register index for immediate");
1716 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1718 return MachineOperand::CreateReg(SubReg, false);
1721 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
1722 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {
1723 assert(Inst->getNumExplicitOperands() == 3);
1724 MachineOperand Op1 = Inst->getOperand(1);
1725 Inst->RemoveOperand(1);
1726 Inst->addOperand(Op1);
1729 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1730 const MachineOperand *MO) const {
1731 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1732 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1733 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1734 const TargetRegisterClass *DefinedRC =
1735 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1737 MO = &MI->getOperand(OpIdx);
1740 usesConstantBus(MRI, *MO, DefinedRC->getSize())) {
1742 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1743 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1746 const MachineOperand &Op = MI->getOperand(i);
1747 if (Op.isReg() && Op.getReg() != SGPRUsed &&
1748 usesConstantBus(MRI, Op, getOpSize(*MI, i))) {
1756 const TargetRegisterClass *RC =
1757 TargetRegisterInfo::isVirtualRegister(MO->getReg()) ?
1758 MRI.getRegClass(MO->getReg()) :
1759 RI.getPhysRegClass(MO->getReg());
1761 // In order to be legal, the common sub-class must be equal to the
1762 // class of the current operand. For example:
1764 // v_mov_b32 s0 ; Operand defined as vsrc_32
1765 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL
1767 // s_sendmsg 0, s0 ; Operand defined as m0reg
1768 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
1770 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
1774 // Handle non-register types that are treated like immediates.
1775 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
1778 // This operand expects an immediate.
1782 return isImmOperandLegal(MI, OpIdx, *MO);
1785 // Legalize VOP3 operands. Because all operand types are supported for any
1786 // operand, and since literal constants are not allowed and should never be
1787 // seen, we only need to worry about inserting copies if we use multiple SGPR
1789 void SIInstrInfo::legalizeOperandsVOP3(
1790 MachineRegisterInfo &MRI,
1791 MachineInstr *MI) const {
1792 unsigned Opc = MI->getOpcode();
1795 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0),
1796 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1),
1797 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)
1800 // Find the one SGPR operand we are allowed to use.
1801 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
1803 for (unsigned i = 0; i < 3; ++i) {
1804 int Idx = VOP3Idx[i];
1807 MachineOperand &MO = MI->getOperand(Idx);
1809 // We should never see a VOP3 instruction with an illegal immediate operand.
1813 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1814 continue; // VGPRs are legal
1816 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1817 SGPRReg = MO.getReg();
1818 // We can use one SGPR in each VOP3 instruction.
1822 // If we make it this far, then the operand is not legal and we must
1824 legalizeOpWithMove(MI, Idx);
1828 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1829 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1830 unsigned Opc = MI->getOpcode();
1834 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
1835 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
1838 if (!isOperandLegal(MI, Src0Idx))
1839 legalizeOpWithMove(MI, Src0Idx);
1842 if (isOperandLegal(MI, Src1Idx))
1845 // Usually src0 of VOP2 instructions allow more types of inputs
1846 // than src1, so try to commute the instruction to decrease our
1847 // chances of having to insert a MOV instruction to legalize src1.
1848 if (MI->isCommutable()) {
1849 if (commuteInstruction(MI))
1850 // If we are successful in commuting, then we know MI is legal, so
1855 legalizeOpWithMove(MI, Src1Idx);
1861 legalizeOperandsVOP3(MRI, MI);
1865 // Legalize REG_SEQUENCE and PHI
1866 // The register class of the operands much be the same type as the register
1867 // class of the output.
1868 if (MI->getOpcode() == AMDGPU::PHI) {
1869 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1870 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1871 if (!MI->getOperand(i).isReg() ||
1872 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1874 const TargetRegisterClass *OpRC =
1875 MRI.getRegClass(MI->getOperand(i).getReg());
1876 if (RI.hasVGPRs(OpRC)) {
1883 // If any of the operands are VGPR registers, then they all most be
1884 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1886 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1889 VRC = RI.getEquivalentVGPRClass(SRC);
1896 // Update all the operands so they have the same type.
1897 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
1898 MachineOperand &Op = MI->getOperand(I);
1899 if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))
1901 unsigned DstReg = MRI.createVirtualRegister(RC);
1903 // MI is a PHI instruction.
1904 MachineBasicBlock *InsertBB = MI->getOperand(I + 1).getMBB();
1905 MachineBasicBlock::iterator Insert = InsertBB->getFirstTerminator();
1907 BuildMI(*InsertBB, Insert, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg)
1913 // REG_SEQUENCE doesn't really require operand legalization, but if one has a
1914 // VGPR dest type and SGPR sources, insert copies so all operands are
1915 // VGPRs. This seems to help operand folding / the register coalescer.
1916 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1917 MachineBasicBlock *MBB = MI->getParent();
1918 const TargetRegisterClass *DstRC = getOpRegClass(*MI, 0);
1919 if (RI.hasVGPRs(DstRC)) {
1920 // Update all the operands so they are VGPR register classes. These may
1921 // not be the same register class because REG_SEQUENCE supports mixing
1922 // subregister index types e.g. sub0_sub1 + sub2 + sub3
1923 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
1924 MachineOperand &Op = MI->getOperand(I);
1925 if (!Op.isReg() || !TargetRegisterInfo::isVirtualRegister(Op.getReg()))
1928 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());
1929 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC);
1933 unsigned DstReg = MRI.createVirtualRegister(VRC);
1935 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), DstReg)
1946 // Legalize INSERT_SUBREG
1947 // src0 must have the same register class as dst
1948 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1949 unsigned Dst = MI->getOperand(0).getReg();
1950 unsigned Src0 = MI->getOperand(1).getReg();
1951 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1952 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1953 if (DstRC != Src0RC) {
1954 MachineBasicBlock &MBB = *MI->getParent();
1955 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1956 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1958 MI->getOperand(1).setReg(NewSrc0);
1963 // Legalize MUBUF* instructions
1964 // FIXME: If we start using the non-addr64 instructions for compute, we
1965 // may need to legalize them here.
1967 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1968 if (SRsrcIdx != -1) {
1969 // We have an MUBUF instruction
1970 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1971 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1972 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1973 RI.getRegClass(SRsrcRC))) {
1974 // The operands are legal.
1975 // FIXME: We may need to legalize operands besided srsrc.
1979 MachineBasicBlock &MBB = *MI->getParent();
1981 // Extract the ptr from the resource descriptor.
1982 unsigned SRsrcPtr = buildExtractSubReg(MI, MRI, *SRsrc,
1983 &AMDGPU::VReg_128RegClass, AMDGPU::sub0_sub1, &AMDGPU::VReg_64RegClass);
1985 // Create an empty resource descriptor
1986 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1987 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1988 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1989 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1990 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1993 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1997 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1998 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2000 .addImm(RsrcDataFormat & 0xFFFFFFFF);
2002 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
2003 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2005 .addImm(RsrcDataFormat >> 32);
2007 // NewSRsrc = {Zero64, SRsrcFormat}
2008 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewSRsrc)
2010 .addImm(AMDGPU::sub0_sub1)
2011 .addReg(SRsrcFormatLo)
2012 .addImm(AMDGPU::sub2)
2013 .addReg(SRsrcFormatHi)
2014 .addImm(AMDGPU::sub3);
2016 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
2017 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2019 // This is already an ADDR64 instruction so we need to add the pointer
2020 // extracted from the resource descriptor to the current value of VAddr.
2021 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2022 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2024 // NewVaddrLo = SRsrcPtr:sub0 + VAddr:sub0
2025 DebugLoc DL = MI->getDebugLoc();
2026 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), NewVAddrLo)
2027 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
2028 .addReg(VAddr->getReg(), 0, AMDGPU::sub0);
2030 // NewVaddrHi = SRsrcPtr:sub1 + VAddr:sub1
2031 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e32), NewVAddrHi)
2032 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
2033 .addReg(VAddr->getReg(), 0, AMDGPU::sub1);
2035 // NewVaddr = {NewVaddrHi, NewVaddrLo}
2036 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
2038 .addImm(AMDGPU::sub0)
2040 .addImm(AMDGPU::sub1);
2042 // This instructions is the _OFFSET variant, so we need to convert it to
2044 assert(MBB.getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration()
2045 < AMDGPUSubtarget::VOLCANIC_ISLANDS &&
2046 "FIXME: Need to emit flat atomics here");
2048 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
2049 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
2050 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
2051 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
2053 // Atomics rith return have have an additional tied operand and are
2054 // missing some of the special bits.
2055 MachineOperand *VDataIn = getNamedOperand(*MI, AMDGPU::OpName::vdata_in);
2056 MachineInstr *Addr64;
2059 // Regular buffer load / store.
2060 MachineInstrBuilder MIB
2061 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
2063 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
2064 // This will be replaced later
2065 // with the new value of vaddr.
2067 .addOperand(*SOffset)
2068 .addOperand(*Offset);
2070 // Atomics do not have this operand.
2071 if (const MachineOperand *GLC
2072 = getNamedOperand(*MI, AMDGPU::OpName::glc)) {
2073 MIB.addImm(GLC->getImm());
2076 MIB.addImm(getNamedImmOperand(*MI, AMDGPU::OpName::slc));
2078 if (const MachineOperand *TFE
2079 = getNamedOperand(*MI, AMDGPU::OpName::tfe)) {
2080 MIB.addImm(TFE->getImm());
2083 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2086 // Atomics with return.
2087 Addr64 = BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
2089 .addOperand(*VDataIn)
2090 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
2091 // This will be replaced later
2092 // with the new value of vaddr.
2094 .addOperand(*SOffset)
2095 .addOperand(*Offset)
2096 .addImm(getNamedImmOperand(*MI, AMDGPU::OpName::slc))
2097 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2100 MI->removeFromParent();
2103 // NewVaddr = {NewVaddrHi, NewVaddrLo}
2104 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
2105 .addReg(SRsrcPtr, 0, AMDGPU::sub0)
2106 .addImm(AMDGPU::sub0)
2107 .addReg(SRsrcPtr, 0, AMDGPU::sub1)
2108 .addImm(AMDGPU::sub1);
2110 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
2111 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
2114 // Update the instruction to use NewVaddr
2115 VAddr->setReg(NewVAddr);
2116 // Update the instruction to use NewSRsrc
2117 SRsrc->setReg(NewSRsrc);
2121 void SIInstrInfo::splitSMRD(MachineInstr *MI,
2122 const TargetRegisterClass *HalfRC,
2123 unsigned HalfImmOp, unsigned HalfSGPROp,
2124 MachineInstr *&Lo, MachineInstr *&Hi) const {
2126 DebugLoc DL = MI->getDebugLoc();
2127 MachineBasicBlock *MBB = MI->getParent();
2128 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2129 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
2130 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
2131 unsigned HalfSize = HalfRC->getSize();
2132 const MachineOperand *OffOp =
2133 getNamedOperand(*MI, AMDGPU::OpName::offset);
2134 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
2136 // The SMRD has an 8-bit offset in dwords on SI and a 20-bit offset in bytes
2139 bool IsKill = SBase->isKill();
2142 MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() >=
2143 AMDGPUSubtarget::VOLCANIC_ISLANDS;
2144 unsigned OffScale = isVI ? 1 : 4;
2145 // Handle the _IMM variant
2146 unsigned LoOffset = OffOp->getImm() * OffScale;
2147 unsigned HiOffset = LoOffset + HalfSize;
2148 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
2149 // Use addReg instead of addOperand
2150 // to make sure kill flag is cleared.
2151 .addReg(SBase->getReg(), 0, SBase->getSubReg())
2152 .addImm(LoOffset / OffScale);
2154 if (!isUInt<20>(HiOffset) || (!isVI && !isUInt<8>(HiOffset / OffScale))) {
2155 unsigned OffsetSGPR =
2156 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2157 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
2158 .addImm(HiOffset); // The offset in register is in bytes.
2159 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
2160 .addReg(SBase->getReg(), getKillRegState(IsKill),
2162 .addReg(OffsetSGPR);
2164 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
2165 .addReg(SBase->getReg(), getKillRegState(IsKill),
2167 .addImm(HiOffset / OffScale);
2170 // Handle the _SGPR variant
2171 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
2172 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
2173 .addReg(SBase->getReg(), 0, SBase->getSubReg())
2175 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2176 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
2177 .addReg(SOff->getReg(), 0, SOff->getSubReg())
2179 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
2180 .addReg(SBase->getReg(), getKillRegState(IsKill),
2182 .addReg(OffsetSGPR);
2185 unsigned SubLo, SubHi;
2186 const TargetRegisterClass *NewDstRC;
2189 SubLo = AMDGPU::sub0;
2190 SubHi = AMDGPU::sub1;
2191 NewDstRC = &AMDGPU::VReg_64RegClass;
2194 SubLo = AMDGPU::sub0_sub1;
2195 SubHi = AMDGPU::sub2_sub3;
2196 NewDstRC = &AMDGPU::VReg_128RegClass;
2199 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
2200 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
2201 NewDstRC = &AMDGPU::VReg_256RegClass;
2204 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
2205 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
2206 NewDstRC = &AMDGPU::VReg_512RegClass;
2209 llvm_unreachable("Unhandled HalfSize");
2212 unsigned OldDst = MI->getOperand(0).getReg();
2213 unsigned NewDst = MRI.createVirtualRegister(NewDstRC);
2215 MRI.replaceRegWith(OldDst, NewDst);
2217 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), NewDst)
2224 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI,
2225 MachineRegisterInfo &MRI,
2226 SmallVectorImpl<MachineInstr *> &Worklist) const {
2227 MachineBasicBlock *MBB = MI->getParent();
2228 int DstIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
2229 assert(DstIdx != -1);
2230 unsigned DstRCID = get(MI->getOpcode()).OpInfo[DstIdx].RegClass;
2231 switch(RI.getRegClass(DstRCID)->getSize()) {
2235 unsigned NewOpcode = getVALUOp(*MI);
2239 if (MI->getOperand(2).isReg()) {
2240 RegOffset = MI->getOperand(2).getReg();
2243 assert(MI->getOperand(2).isImm());
2244 // SMRD instructions take a dword offsets on SI and byte offset on VI
2245 // and MUBUF instructions always take a byte offset.
2246 ImmOffset = MI->getOperand(2).getImm();
2247 if (MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() <=
2248 AMDGPUSubtarget::SEA_ISLANDS)
2250 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2252 if (isUInt<12>(ImmOffset)) {
2253 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2257 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2264 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
2265 unsigned DWord0 = RegOffset;
2266 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2267 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2268 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2269 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
2271 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
2273 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
2274 .addImm(RsrcDataFormat & 0xFFFFFFFF);
2275 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
2276 .addImm(RsrcDataFormat >> 32);
2277 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
2279 .addImm(AMDGPU::sub0)
2281 .addImm(AMDGPU::sub1)
2283 .addImm(AMDGPU::sub2)
2285 .addImm(AMDGPU::sub3);
2287 const MCInstrDesc &NewInstDesc = get(NewOpcode);
2288 const TargetRegisterClass *NewDstRC
2289 = RI.getRegClass(NewInstDesc.OpInfo[0].RegClass);
2290 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2291 unsigned DstReg = MI->getOperand(0).getReg();
2292 MRI.replaceRegWith(DstReg, NewDstReg);
2294 MachineInstr *NewInst =
2295 BuildMI(*MBB, MI, MI->getDebugLoc(), NewInstDesc, NewDstReg)
2296 .addOperand(MI->getOperand(1)) // sbase
2303 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
2304 MI->eraseFromParent();
2306 legalizeOperands(NewInst);
2307 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
2311 MachineInstr *Lo, *Hi;
2312 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
2313 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
2314 MI->eraseFromParent();
2315 moveSMRDToVALU(Lo, MRI, Worklist);
2316 moveSMRDToVALU(Hi, MRI, Worklist);
2321 MachineInstr *Lo, *Hi;
2322 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
2323 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
2324 MI->eraseFromParent();
2325 moveSMRDToVALU(Lo, MRI, Worklist);
2326 moveSMRDToVALU(Hi, MRI, Worklist);
2332 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
2333 SmallVector<MachineInstr *, 128> Worklist;
2334 Worklist.push_back(&TopInst);
2336 while (!Worklist.empty()) {
2337 MachineInstr *Inst = Worklist.pop_back_val();
2338 MachineBasicBlock *MBB = Inst->getParent();
2339 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2341 unsigned Opcode = Inst->getOpcode();
2342 unsigned NewOpcode = getVALUOp(*Inst);
2344 // Handle some special cases
2347 if (isSMRD(*Inst)) {
2348 moveSMRDToVALU(Inst, MRI, Worklist);
2352 case AMDGPU::S_AND_B64:
2353 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_AND_B32_e64);
2354 Inst->eraseFromParent();
2357 case AMDGPU::S_OR_B64:
2358 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_OR_B32_e64);
2359 Inst->eraseFromParent();
2362 case AMDGPU::S_XOR_B64:
2363 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::V_XOR_B32_e64);
2364 Inst->eraseFromParent();
2367 case AMDGPU::S_NOT_B64:
2368 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::V_NOT_B32_e32);
2369 Inst->eraseFromParent();
2372 case AMDGPU::S_BCNT1_I32_B64:
2373 splitScalar64BitBCNT(Worklist, Inst);
2374 Inst->eraseFromParent();
2377 case AMDGPU::S_BFE_I64: {
2378 splitScalar64BitBFE(Worklist, Inst);
2379 Inst->eraseFromParent();
2383 case AMDGPU::S_LSHL_B32:
2384 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2385 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
2389 case AMDGPU::S_ASHR_I32:
2390 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2391 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
2395 case AMDGPU::S_LSHR_B32:
2396 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2397 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
2401 case AMDGPU::S_LSHL_B64:
2402 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2403 NewOpcode = AMDGPU::V_LSHLREV_B64;
2407 case AMDGPU::S_ASHR_I64:
2408 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2409 NewOpcode = AMDGPU::V_ASHRREV_I64;
2413 case AMDGPU::S_LSHR_B64:
2414 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2415 NewOpcode = AMDGPU::V_LSHRREV_B64;
2420 case AMDGPU::S_ABS_I32:
2421 lowerScalarAbs(Worklist, Inst);
2422 Inst->eraseFromParent();
2425 case AMDGPU::S_BFE_U64:
2426 case AMDGPU::S_BFM_B64:
2427 llvm_unreachable("Moving this op to VALU not implemented");
2430 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
2431 // We cannot move this instruction to the VALU, so we should try to
2432 // legalize its operands instead.
2433 legalizeOperands(Inst);
2437 // Use the new VALU Opcode.
2438 const MCInstrDesc &NewDesc = get(NewOpcode);
2439 Inst->setDesc(NewDesc);
2441 // Remove any references to SCC. Vector instructions can't read from it, and
2442 // We're just about to add the implicit use / defs of VCC, and we don't want
2444 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
2445 MachineOperand &Op = Inst->getOperand(i);
2446 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
2447 Inst->RemoveOperand(i);
2450 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
2451 // We are converting these to a BFE, so we need to add the missing
2452 // operands for the size and offset.
2453 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
2454 Inst->addOperand(MachineOperand::CreateImm(0));
2455 Inst->addOperand(MachineOperand::CreateImm(Size));
2457 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
2458 // The VALU version adds the second operand to the result, so insert an
2460 Inst->addOperand(MachineOperand::CreateImm(0));
2463 Inst->addImplicitDefUseOperands(*Inst->getParent()->getParent());
2465 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
2466 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
2467 // If we need to move this to VGPRs, we need to unpack the second operand
2468 // back into the 2 separate ones for bit offset and width.
2469 assert(OffsetWidthOp.isImm() &&
2470 "Scalar BFE is only implemented for constant width and offset");
2471 uint32_t Imm = OffsetWidthOp.getImm();
2473 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2474 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2475 Inst->RemoveOperand(2); // Remove old immediate.
2476 Inst->addOperand(MachineOperand::CreateImm(Offset));
2477 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
2480 // Update the destination register class.
2481 const TargetRegisterClass *NewDstRC = getDestEquivalentVGPRClass(*Inst);
2485 unsigned DstReg = Inst->getOperand(0).getReg();
2486 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2487 MRI.replaceRegWith(DstReg, NewDstReg);
2489 // Legalize the operands
2490 legalizeOperands(Inst);
2492 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
2496 //===----------------------------------------------------------------------===//
2497 // Indirect addressing callbacks
2498 //===----------------------------------------------------------------------===//
2500 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2501 unsigned Channel) const {
2502 assert(Channel == 0);
2506 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2507 return &AMDGPU::VGPR_32RegClass;
2510 void SIInstrInfo::lowerScalarAbs(SmallVectorImpl<MachineInstr *> &Worklist,
2511 MachineInstr *Inst) const {
2512 MachineBasicBlock &MBB = *Inst->getParent();
2513 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2514 MachineBasicBlock::iterator MII = Inst;
2515 DebugLoc DL = Inst->getDebugLoc();
2517 MachineOperand &Dest = Inst->getOperand(0);
2518 MachineOperand &Src = Inst->getOperand(1);
2519 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2520 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2522 BuildMI(MBB, MII, DL, get(AMDGPU::V_SUB_I32_e32), TmpReg)
2524 .addReg(Src.getReg());
2526 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg)
2527 .addReg(Src.getReg())
2530 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2531 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2534 void SIInstrInfo::splitScalar64BitUnaryOp(
2535 SmallVectorImpl<MachineInstr *> &Worklist,
2537 unsigned Opcode) const {
2538 MachineBasicBlock &MBB = *Inst->getParent();
2539 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2541 MachineOperand &Dest = Inst->getOperand(0);
2542 MachineOperand &Src0 = Inst->getOperand(1);
2543 DebugLoc DL = Inst->getDebugLoc();
2545 MachineBasicBlock::iterator MII = Inst;
2547 const MCInstrDesc &InstDesc = get(Opcode);
2548 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2549 MRI.getRegClass(Src0.getReg()) :
2550 &AMDGPU::SGPR_32RegClass;
2552 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2554 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2555 AMDGPU::sub0, Src0SubRC);
2557 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2558 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
2559 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
2561 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
2562 BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2563 .addOperand(SrcReg0Sub0);
2565 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2566 AMDGPU::sub1, Src0SubRC);
2568 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
2569 BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2570 .addOperand(SrcReg0Sub1);
2572 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
2573 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2575 .addImm(AMDGPU::sub0)
2577 .addImm(AMDGPU::sub1);
2579 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2581 // We don't need to legalizeOperands here because for a single operand, src0
2582 // will support any kind of input.
2584 // Move all users of this moved value.
2585 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
2588 void SIInstrInfo::splitScalar64BitBinaryOp(
2589 SmallVectorImpl<MachineInstr *> &Worklist,
2591 unsigned Opcode) const {
2592 MachineBasicBlock &MBB = *Inst->getParent();
2593 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2595 MachineOperand &Dest = Inst->getOperand(0);
2596 MachineOperand &Src0 = Inst->getOperand(1);
2597 MachineOperand &Src1 = Inst->getOperand(2);
2598 DebugLoc DL = Inst->getDebugLoc();
2600 MachineBasicBlock::iterator MII = Inst;
2602 const MCInstrDesc &InstDesc = get(Opcode);
2603 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2604 MRI.getRegClass(Src0.getReg()) :
2605 &AMDGPU::SGPR_32RegClass;
2607 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2608 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2609 MRI.getRegClass(Src1.getReg()) :
2610 &AMDGPU::SGPR_32RegClass;
2612 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2614 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2615 AMDGPU::sub0, Src0SubRC);
2616 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2617 AMDGPU::sub0, Src1SubRC);
2619 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2620 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
2621 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
2623 unsigned DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
2624 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2625 .addOperand(SrcReg0Sub0)
2626 .addOperand(SrcReg1Sub0);
2628 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2629 AMDGPU::sub1, Src0SubRC);
2630 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2631 AMDGPU::sub1, Src1SubRC);
2633 unsigned DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
2634 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2635 .addOperand(SrcReg0Sub1)
2636 .addOperand(SrcReg1Sub1);
2638 unsigned FullDestReg = MRI.createVirtualRegister(NewDestRC);
2639 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2641 .addImm(AMDGPU::sub0)
2643 .addImm(AMDGPU::sub1);
2645 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2647 // Try to legalize the operands in case we need to swap the order to keep it
2649 legalizeOperands(LoHalf);
2650 legalizeOperands(HiHalf);
2652 // Move all users of this moved vlaue.
2653 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
2656 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2657 MachineInstr *Inst) const {
2658 MachineBasicBlock &MBB = *Inst->getParent();
2659 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2661 MachineBasicBlock::iterator MII = Inst;
2662 DebugLoc DL = Inst->getDebugLoc();
2664 MachineOperand &Dest = Inst->getOperand(0);
2665 MachineOperand &Src = Inst->getOperand(1);
2667 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
2668 const TargetRegisterClass *SrcRC = Src.isReg() ?
2669 MRI.getRegClass(Src.getReg()) :
2670 &AMDGPU::SGPR_32RegClass;
2672 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2673 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2675 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2677 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2678 AMDGPU::sub0, SrcSubRC);
2679 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2680 AMDGPU::sub1, SrcSubRC);
2682 BuildMI(MBB, MII, DL, InstDesc, MidReg)
2683 .addOperand(SrcRegSub0)
2686 BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2687 .addOperand(SrcRegSub1)
2690 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2692 // We don't need to legalize operands here. src0 for etiher instruction can be
2693 // an SGPR, and the second input is unused or determined here.
2694 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2697 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
2698 MachineInstr *Inst) const {
2699 MachineBasicBlock &MBB = *Inst->getParent();
2700 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2701 MachineBasicBlock::iterator MII = Inst;
2702 DebugLoc DL = Inst->getDebugLoc();
2704 MachineOperand &Dest = Inst->getOperand(0);
2705 uint32_t Imm = Inst->getOperand(2).getImm();
2706 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2707 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2711 // Only sext_inreg cases handled.
2712 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 &&
2717 if (BitWidth < 32) {
2718 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2719 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2720 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2722 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
2723 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0)
2727 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
2731 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2733 .addImm(AMDGPU::sub0)
2735 .addImm(AMDGPU::sub1);
2737 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2738 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2742 MachineOperand &Src = Inst->getOperand(1);
2743 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2744 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2746 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
2748 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2750 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2751 .addReg(Src.getReg(), 0, AMDGPU::sub0)
2752 .addImm(AMDGPU::sub0)
2754 .addImm(AMDGPU::sub1);
2756 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2757 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
2760 void SIInstrInfo::addUsersToMoveToVALUWorklist(
2762 MachineRegisterInfo &MRI,
2763 SmallVectorImpl<MachineInstr *> &Worklist) const {
2764 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg),
2765 E = MRI.use_end(); I != E; ++I) {
2766 MachineInstr &UseMI = *I->getParent();
2767 if (!canReadVGPR(UseMI, I.getOperandNo())) {
2768 Worklist.push_back(&UseMI);
2773 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(
2774 const MachineInstr &Inst) const {
2775 const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0);
2777 switch (Inst.getOpcode()) {
2778 // For target instructions, getOpRegClass just returns the virtual register
2779 // class associated with the operand, so we need to find an equivalent VGPR
2780 // register class in order to move the instruction to the VALU.
2783 case AMDGPU::REG_SEQUENCE:
2784 case AMDGPU::INSERT_SUBREG:
2785 if (RI.hasVGPRs(NewDstRC))
2788 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
2797 // Find the one SGPR operand we are allowed to use.
2798 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2799 int OpIndices[3]) const {
2800 const MCInstrDesc &Desc = MI->getDesc();
2802 // Find the one SGPR operand we are allowed to use.
2804 // First we need to consider the instruction's operand requirements before
2805 // legalizing. Some operands are required to be SGPRs, such as implicit uses
2806 // of VCC, but we are still bound by the constant bus requirement to only use
2809 // If the operand's class is an SGPR, we can never move it.
2811 unsigned SGPRReg = findImplicitSGPRRead(*MI);
2812 if (SGPRReg != AMDGPU::NoRegister)
2815 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
2816 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2818 for (unsigned i = 0; i < 3; ++i) {
2819 int Idx = OpIndices[i];
2823 const MachineOperand &MO = MI->getOperand(Idx);
2827 // Is this operand statically required to be an SGPR based on the operand
2829 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
2830 bool IsRequiredSGPR = RI.isSGPRClass(OpRC);
2834 // If this could be a VGPR or an SGPR, Check the dynamic register class.
2835 unsigned Reg = MO.getReg();
2836 const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
2837 if (RI.isSGPRClass(RegRC))
2841 // We don't have a required SGPR operand, so we have a bit more freedom in
2842 // selecting operands to move.
2844 // Try to select the most used SGPR. If an SGPR is equal to one of the
2845 // others, we choose that.
2848 // V_FMA_F32 v0, s0, s0, s0 -> No moves
2849 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
2851 // TODO: If some of the operands are 64-bit SGPRs and some 32, we should
2854 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
2855 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
2856 SGPRReg = UsedSGPRs[0];
2859 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
2860 if (UsedSGPRs[1] == UsedSGPRs[2])
2861 SGPRReg = UsedSGPRs[1];
2867 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2868 MachineBasicBlock *MBB,
2869 MachineBasicBlock::iterator I,
2871 unsigned Address, unsigned OffsetReg) const {
2872 const DebugLoc &DL = MBB->findDebugLoc(I);
2873 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2874 getIndirectIndexBegin(*MBB->getParent()));
2876 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2877 .addReg(IndirectBaseReg, RegState::Define)
2878 .addOperand(I->getOperand(0))
2879 .addReg(IndirectBaseReg)
2885 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2886 MachineBasicBlock *MBB,
2887 MachineBasicBlock::iterator I,
2889 unsigned Address, unsigned OffsetReg) const {
2890 const DebugLoc &DL = MBB->findDebugLoc(I);
2891 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2892 getIndirectIndexBegin(*MBB->getParent()));
2894 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC_V1))
2895 .addOperand(I->getOperand(0))
2896 .addOperand(I->getOperand(1))
2897 .addReg(IndirectBaseReg)
2903 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2904 const MachineFunction &MF) const {
2905 int End = getIndirectIndexEnd(MF);
2906 int Begin = getIndirectIndexBegin(MF);
2912 for (int Index = Begin; Index <= End; ++Index)
2913 Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index));
2915 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2916 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
2918 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
2919 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
2921 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
2922 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
2924 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
2925 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
2927 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
2928 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
2931 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
2932 unsigned OperandName) const {
2933 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
2937 return &MI.getOperand(Idx);
2940 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
2941 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
2942 if (ST.isAmdHsaOS()) {
2943 RsrcDataFormat |= (1ULL << 56);
2945 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2947 RsrcDataFormat |= (2ULL << 59);
2950 return RsrcDataFormat;
2953 uint64_t SIInstrInfo::getScratchRsrcWords23() const {
2954 uint64_t Rsrc23 = getDefaultRsrcDataFormat() |
2955 AMDGPU::RSRC_TID_ENABLE |
2956 0xffffffff; // Size;
2958 // If TID_ENABLE is set, DATA_FORMAT specifies stride bits [14:17].
2959 // Clear them unless we want a huge stride.
2960 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2961 Rsrc23 &= ~AMDGPU::RSRC_DATA_FORMAT;