1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
26 #include "llvm/Support/Debug.h"
30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
31 : AMDGPUInstrInfo(st), RI() {}
33 //===----------------------------------------------------------------------===//
34 // TargetInstrInfo callbacks
35 //===----------------------------------------------------------------------===//
37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
38 unsigned N = Node->getNumOperands();
39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
44 static SDValue findChainOperand(SDNode *Load) {
45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
50 /// \brief Returns true if both nodes have the same value for the given
51 /// operand \p Op, or if both nodes do not have this operand.
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
53 unsigned Opc0 = N0->getMachineOpcode();
54 unsigned Opc1 = N1->getMachineOpcode();
56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59 if (Op0Idx == -1 && Op1Idx == -1)
63 if ((Op0Idx == -1 && Op1Idx != -1) ||
64 (Op1Idx == -1 && Op0Idx != -1))
67 // getNamedOperandIdx returns the index for the MachineInstr's operands,
68 // which includes the result as the first operand. We are indexing into the
69 // MachineSDNode's operands, so we need to skip the result operand to get
74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
77 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
78 AliasAnalysis *AA) const {
79 // TODO: The generic check fails for VALU instructions that should be
80 // rematerializable due to implicit reads of exec. We really want all of the
81 // generic logic for this except for this.
82 switch (MI->getOpcode()) {
83 case AMDGPU::V_MOV_B32_e32:
84 case AMDGPU::V_MOV_B32_e64:
91 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
93 int64_t &Offset1) const {
94 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
97 unsigned Opc0 = Load0->getMachineOpcode();
98 unsigned Opc1 = Load1->getMachineOpcode();
100 // Make sure both are actually loads.
101 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
104 if (isDS(Opc0) && isDS(Opc1)) {
106 // FIXME: Handle this case:
107 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
111 if (Load0->getOperand(1) != Load1->getOperand(1))
115 if (findChainOperand(Load0) != findChainOperand(Load1))
118 // Skip read2 / write2 variants for simplicity.
119 // TODO: We should report true if the used offsets are adjacent (excluded
121 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
122 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
125 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
126 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
130 if (isSMRD(Opc0) && isSMRD(Opc1)) {
131 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
134 if (Load0->getOperand(0) != Load1->getOperand(0))
137 const ConstantSDNode *Load0Offset =
138 dyn_cast<ConstantSDNode>(Load0->getOperand(1));
139 const ConstantSDNode *Load1Offset =
140 dyn_cast<ConstantSDNode>(Load1->getOperand(1));
142 if (!Load0Offset || !Load1Offset)
146 if (findChainOperand(Load0) != findChainOperand(Load1))
149 Offset0 = Load0Offset->getZExtValue();
150 Offset1 = Load1Offset->getZExtValue();
154 // MUBUF and MTBUF can access the same addresses.
155 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
157 // MUBUF and MTBUF have vaddr at different indices.
158 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
159 findChainOperand(Load0) != findChainOperand(Load1) ||
160 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
161 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
164 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
165 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
167 if (OffIdx0 == -1 || OffIdx1 == -1)
170 // getNamedOperandIdx returns the index for MachineInstrs. Since they
171 // inlcude the output in the operand list, but SDNodes don't, we need to
172 // subtract the index by one.
176 SDValue Off0 = Load0->getOperand(OffIdx0);
177 SDValue Off1 = Load1->getOperand(OffIdx1);
179 // The offset might be a FrameIndexSDNode.
180 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
183 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
184 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
191 static bool isStride64(unsigned Opc) {
193 case AMDGPU::DS_READ2ST64_B32:
194 case AMDGPU::DS_READ2ST64_B64:
195 case AMDGPU::DS_WRITE2ST64_B32:
196 case AMDGPU::DS_WRITE2ST64_B64:
203 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
205 const TargetRegisterInfo *TRI) const {
206 unsigned Opc = LdSt->getOpcode();
208 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
209 AMDGPU::OpName::offset);
211 // Normal, single offset LDS instruction.
212 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
213 AMDGPU::OpName::addr);
215 BaseReg = AddrReg->getReg();
216 Offset = OffsetImm->getImm();
220 // The 2 offset instructions use offset0 and offset1 instead. We can treat
221 // these as a load with a single offset if the 2 offsets are consecutive. We
222 // will use this for some partially aligned loads.
223 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
224 AMDGPU::OpName::offset0);
225 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
226 AMDGPU::OpName::offset1);
228 uint8_t Offset0 = Offset0Imm->getImm();
229 uint8_t Offset1 = Offset1Imm->getImm();
231 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
232 // Each of these offsets is in element sized units, so we need to convert
233 // to bytes of the individual reads.
237 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
239 assert(LdSt->mayStore());
240 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
241 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
247 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
248 AMDGPU::OpName::addr);
249 BaseReg = AddrReg->getReg();
250 Offset = EltSize * Offset0;
257 if (isMUBUF(Opc) || isMTBUF(Opc)) {
258 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
261 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
262 AMDGPU::OpName::vaddr);
266 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
267 AMDGPU::OpName::offset);
268 BaseReg = AddrReg->getReg();
269 Offset = OffsetImm->getImm();
274 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
275 AMDGPU::OpName::offset);
279 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
280 AMDGPU::OpName::sbase);
281 BaseReg = SBaseReg->getReg();
282 Offset = OffsetImm->getImm();
289 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
290 MachineInstr *SecondLdSt,
291 unsigned NumLoads) const {
292 unsigned Opc0 = FirstLdSt->getOpcode();
293 unsigned Opc1 = SecondLdSt->getOpcode();
295 // TODO: This needs finer tuning
299 if (isDS(Opc0) && isDS(Opc1))
302 if (isSMRD(Opc0) && isSMRD(Opc1))
305 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1)))
312 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
313 MachineBasicBlock::iterator MI, DebugLoc DL,
314 unsigned DestReg, unsigned SrcReg,
315 bool KillSrc) const {
317 // If we are trying to copy to or from SCC, there is a bug somewhere else in
318 // the backend. While it may be theoretically possible to do this, it should
319 // never be necessary.
320 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
322 static const int16_t Sub0_15[] = {
323 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
324 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
325 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
326 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
329 static const int16_t Sub0_7[] = {
330 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
331 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
334 static const int16_t Sub0_3[] = {
335 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
338 static const int16_t Sub0_2[] = {
339 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
342 static const int16_t Sub0_1[] = {
343 AMDGPU::sub0, AMDGPU::sub1, 0
347 const int16_t *SubIndices;
349 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
350 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
351 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
352 .addReg(SrcReg, getKillRegState(KillSrc));
355 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
356 if (DestReg == AMDGPU::VCC) {
357 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
358 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
359 .addReg(SrcReg, getKillRegState(KillSrc));
361 // FIXME: Hack until VReg_1 removed.
362 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
363 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32), AMDGPU::VCC)
365 .addReg(SrcReg, getKillRegState(KillSrc));
371 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
372 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
373 .addReg(SrcReg, getKillRegState(KillSrc));
376 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
377 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
378 Opcode = AMDGPU::S_MOV_B32;
381 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
382 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
383 Opcode = AMDGPU::S_MOV_B32;
386 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
387 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
388 Opcode = AMDGPU::S_MOV_B32;
389 SubIndices = Sub0_15;
391 } else if (AMDGPU::VGPR_32RegClass.contains(DestReg)) {
392 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
393 AMDGPU::SReg_32RegClass.contains(SrcReg));
394 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
395 .addReg(SrcReg, getKillRegState(KillSrc));
398 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
399 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
400 AMDGPU::SReg_64RegClass.contains(SrcReg));
401 Opcode = AMDGPU::V_MOV_B32_e32;
404 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
405 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
406 Opcode = AMDGPU::V_MOV_B32_e32;
409 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
410 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
411 AMDGPU::SReg_128RegClass.contains(SrcReg));
412 Opcode = AMDGPU::V_MOV_B32_e32;
415 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
416 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
417 AMDGPU::SReg_256RegClass.contains(SrcReg));
418 Opcode = AMDGPU::V_MOV_B32_e32;
421 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
422 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
423 AMDGPU::SReg_512RegClass.contains(SrcReg));
424 Opcode = AMDGPU::V_MOV_B32_e32;
425 SubIndices = Sub0_15;
428 llvm_unreachable("Can't copy register!");
431 while (unsigned SubIdx = *SubIndices++) {
432 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
433 get(Opcode), RI.getSubReg(DestReg, SubIdx));
435 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
438 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
442 int SIInstrInfo::commuteOpcode(const MachineInstr &MI) const {
443 const unsigned Opcode = MI.getOpcode();
447 // Try to map original to commuted opcode
448 NewOpc = AMDGPU::getCommuteRev(Opcode);
450 // Check if the commuted (REV) opcode exists on the target.
451 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
453 // Try to map commuted to original opcode
454 NewOpc = AMDGPU::getCommuteOrig(Opcode);
456 // Check if the original (non-REV) opcode exists on the target.
457 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
462 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
464 if (DstRC->getSize() == 4) {
465 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
466 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
467 return AMDGPU::S_MOV_B64;
468 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
469 return AMDGPU::V_MOV_B64_PSEUDO;
474 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
475 MachineBasicBlock::iterator MI,
476 unsigned SrcReg, bool isKill,
478 const TargetRegisterClass *RC,
479 const TargetRegisterInfo *TRI) const {
480 MachineFunction *MF = MBB.getParent();
481 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
482 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
483 DebugLoc DL = MBB.findDebugLoc(MI);
486 if (RI.isSGPRClass(RC)) {
487 // We are only allowed to create one new instruction when spilling
488 // registers, so we need to use pseudo instruction for spilling
490 switch (RC->getSize() * 8) {
491 case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break;
492 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
493 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
494 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
495 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
497 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
498 MFI->setHasSpilledVGPRs();
500 switch(RC->getSize() * 8) {
501 case 32: Opcode = AMDGPU::SI_SPILL_V32_SAVE; break;
502 case 64: Opcode = AMDGPU::SI_SPILL_V64_SAVE; break;
503 case 96: Opcode = AMDGPU::SI_SPILL_V96_SAVE; break;
504 case 128: Opcode = AMDGPU::SI_SPILL_V128_SAVE; break;
505 case 256: Opcode = AMDGPU::SI_SPILL_V256_SAVE; break;
506 case 512: Opcode = AMDGPU::SI_SPILL_V512_SAVE; break;
511 FrameInfo->setObjectAlignment(FrameIndex, 4);
512 BuildMI(MBB, MI, DL, get(Opcode))
514 .addFrameIndex(FrameIndex)
515 // Place-holder registers, these will be filled in by
516 // SIPrepareScratchRegs.
517 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
518 .addReg(AMDGPU::SGPR0, RegState::Undef);
520 LLVMContext &Ctx = MF->getFunction()->getContext();
521 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
523 BuildMI(MBB, MI, DL, get(AMDGPU::KILL))
528 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
529 MachineBasicBlock::iterator MI,
530 unsigned DestReg, int FrameIndex,
531 const TargetRegisterClass *RC,
532 const TargetRegisterInfo *TRI) const {
533 MachineFunction *MF = MBB.getParent();
534 const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
535 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
536 DebugLoc DL = MBB.findDebugLoc(MI);
539 if (RI.isSGPRClass(RC)){
540 switch(RC->getSize() * 8) {
541 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
542 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
543 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
544 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
545 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
547 } else if(RI.hasVGPRs(RC) && ST.isVGPRSpillingEnabled(MFI)) {
548 switch(RC->getSize() * 8) {
549 case 32: Opcode = AMDGPU::SI_SPILL_V32_RESTORE; break;
550 case 64: Opcode = AMDGPU::SI_SPILL_V64_RESTORE; break;
551 case 96: Opcode = AMDGPU::SI_SPILL_V96_RESTORE; break;
552 case 128: Opcode = AMDGPU::SI_SPILL_V128_RESTORE; break;
553 case 256: Opcode = AMDGPU::SI_SPILL_V256_RESTORE; break;
554 case 512: Opcode = AMDGPU::SI_SPILL_V512_RESTORE; break;
559 FrameInfo->setObjectAlignment(FrameIndex, 4);
560 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
561 .addFrameIndex(FrameIndex)
562 // Place-holder registers, these will be filled in by
563 // SIPrepareScratchRegs.
564 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
565 .addReg(AMDGPU::SGPR0, RegState::Undef);
568 LLVMContext &Ctx = MF->getFunction()->getContext();
569 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
570 " restore register");
571 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg);
575 /// \param @Offset Offset in bytes of the FrameIndex being spilled
576 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
577 MachineBasicBlock::iterator MI,
578 RegScavenger *RS, unsigned TmpReg,
579 unsigned FrameOffset,
580 unsigned Size) const {
581 MachineFunction *MF = MBB.getParent();
582 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
583 const AMDGPUSubtarget &ST = MF->getSubtarget<AMDGPUSubtarget>();
584 const SIRegisterInfo *TRI =
585 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
586 DebugLoc DL = MBB.findDebugLoc(MI);
587 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
588 unsigned WavefrontSize = ST.getWavefrontSize();
590 unsigned TIDReg = MFI->getTIDReg();
591 if (!MFI->hasCalculatedTID()) {
592 MachineBasicBlock &Entry = MBB.getParent()->front();
593 MachineBasicBlock::iterator Insert = Entry.front();
594 DebugLoc DL = Insert->getDebugLoc();
596 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass);
597 if (TIDReg == AMDGPU::NoRegister)
601 if (MFI->getShaderType() == ShaderType::COMPUTE &&
602 WorkGroupSize > WavefrontSize) {
604 unsigned TIDIGXReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_X);
605 unsigned TIDIGYReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Y);
606 unsigned TIDIGZReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Z);
607 unsigned InputPtrReg =
608 TRI->getPreloadedValue(*MF, SIRegisterInfo::INPUT_PTR);
609 for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) {
610 if (!Entry.isLiveIn(Reg))
611 Entry.addLiveIn(Reg);
614 RS->enterBasicBlock(&Entry);
615 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
616 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
617 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
619 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
620 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
622 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
624 // NGROUPS.X * NGROUPS.Y
625 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
628 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
629 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
632 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
633 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
637 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
638 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
643 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
648 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
654 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
658 MFI->setTIDReg(TIDReg);
661 // Add FrameIndex to LDS offset
662 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
663 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
670 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
679 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
684 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
685 MachineBasicBlock &MBB = *MI->getParent();
686 DebugLoc DL = MBB.findDebugLoc(MI);
687 switch (MI->getOpcode()) {
688 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
690 case AMDGPU::SI_CONSTDATA_PTR: {
691 unsigned Reg = MI->getOperand(0).getReg();
692 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
693 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
695 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
697 // Add 32-bit offset from this instruction to the start of the constant data.
698 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo)
700 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
701 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
702 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
705 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
706 .addReg(AMDGPU::SCC, RegState::Implicit);
707 MI->eraseFromParent();
710 case AMDGPU::SGPR_USE:
711 // This is just a placeholder for register allocation.
712 MI->eraseFromParent();
715 case AMDGPU::V_MOV_B64_PSEUDO: {
716 unsigned Dst = MI->getOperand(0).getReg();
717 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
718 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
720 const MachineOperand &SrcOp = MI->getOperand(1);
721 // FIXME: Will this work for 64-bit floating point immediates?
722 assert(!SrcOp.isFPImm());
724 APInt Imm(64, SrcOp.getImm());
725 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
726 .addImm(Imm.getLoBits(32).getZExtValue())
727 .addReg(Dst, RegState::Implicit);
728 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
729 .addImm(Imm.getHiBits(32).getZExtValue())
730 .addReg(Dst, RegState::Implicit);
732 assert(SrcOp.isReg());
733 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
734 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
735 .addReg(Dst, RegState::Implicit);
736 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
737 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
738 .addReg(Dst, RegState::Implicit);
740 MI->eraseFromParent();
744 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
745 unsigned Dst = MI->getOperand(0).getReg();
746 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
747 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
748 unsigned Src0 = MI->getOperand(1).getReg();
749 unsigned Src1 = MI->getOperand(2).getReg();
750 const MachineOperand &SrcCond = MI->getOperand(3);
752 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
753 .addReg(RI.getSubReg(Src0, AMDGPU::sub0))
754 .addReg(RI.getSubReg(Src1, AMDGPU::sub0))
755 .addOperand(SrcCond);
756 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
757 .addReg(RI.getSubReg(Src0, AMDGPU::sub1))
758 .addReg(RI.getSubReg(Src1, AMDGPU::sub1))
759 .addOperand(SrcCond);
760 MI->eraseFromParent();
767 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
770 if (MI->getNumOperands() < 3)
773 int CommutedOpcode = commuteOpcode(*MI);
774 if (CommutedOpcode == -1)
777 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
778 AMDGPU::OpName::src0);
779 assert(Src0Idx != -1 && "Should always have src0 operand");
781 MachineOperand &Src0 = MI->getOperand(Src0Idx);
785 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
786 AMDGPU::OpName::src1);
790 MachineOperand &Src1 = MI->getOperand(Src1Idx);
792 // Make sure it's legal to commute operands for VOP2.
793 if (isVOP2(MI->getOpcode()) &&
794 (!isOperandLegal(MI, Src0Idx, &Src1) ||
795 !isOperandLegal(MI, Src1Idx, &Src0))) {
800 // Allow commuting instructions with Imm operands.
801 if (NewMI || !Src1.isImm() ||
802 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
806 // Be sure to copy the source modifiers to the right place.
807 if (MachineOperand *Src0Mods
808 = getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) {
809 MachineOperand *Src1Mods
810 = getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers);
812 int Src0ModsVal = Src0Mods->getImm();
813 if (!Src1Mods && Src0ModsVal != 0)
816 // XXX - This assert might be a lie. It might be useful to have a neg
817 // modifier with 0.0.
818 int Src1ModsVal = Src1Mods->getImm();
819 assert((Src1ModsVal == 0) && "Not expecting modifiers with immediates");
821 Src1Mods->setImm(Src0ModsVal);
822 Src0Mods->setImm(Src1ModsVal);
825 unsigned Reg = Src0.getReg();
826 unsigned SubReg = Src0.getSubReg();
828 Src0.ChangeToImmediate(Src1.getImm());
830 llvm_unreachable("Should only have immediates");
832 Src1.ChangeToRegister(Reg, false);
833 Src1.setSubReg(SubReg);
835 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
839 MI->setDesc(get(CommutedOpcode));
844 // This needs to be implemented because the source modifiers may be inserted
845 // between the true commutable operands, and the base
846 // TargetInstrInfo::commuteInstruction uses it.
847 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
849 unsigned &SrcOpIdx2) const {
850 const MCInstrDesc &MCID = MI->getDesc();
851 if (!MCID.isCommutable())
854 unsigned Opc = MI->getOpcode();
855 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
859 // FIXME: Workaround TargetInstrInfo::commuteInstruction asserting on
861 if (!MI->getOperand(Src0Idx).isReg())
864 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
868 if (!MI->getOperand(Src1Idx).isReg())
871 // If any source modifiers are set, the generic instruction commuting won't
872 // understand how to copy the source modifiers.
873 if (hasModifiersSet(*MI, AMDGPU::OpName::src0_modifiers) ||
874 hasModifiersSet(*MI, AMDGPU::OpName::src1_modifiers))
882 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
883 MachineBasicBlock::iterator I,
885 unsigned SrcReg) const {
886 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
887 DstReg) .addReg(SrcReg);
890 bool SIInstrInfo::isMov(unsigned Opcode) const {
892 default: return false;
893 case AMDGPU::S_MOV_B32:
894 case AMDGPU::S_MOV_B64:
895 case AMDGPU::V_MOV_B32_e32:
896 case AMDGPU::V_MOV_B32_e64:
901 static void removeModOperands(MachineInstr &MI) {
902 unsigned Opc = MI.getOpcode();
903 int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc,
904 AMDGPU::OpName::src0_modifiers);
905 int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc,
906 AMDGPU::OpName::src1_modifiers);
907 int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
908 AMDGPU::OpName::src2_modifiers);
910 MI.RemoveOperand(Src2ModIdx);
911 MI.RemoveOperand(Src1ModIdx);
912 MI.RemoveOperand(Src0ModIdx);
915 bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
916 unsigned Reg, MachineRegisterInfo *MRI) const {
917 if (!MRI->hasOneNonDBGUse(Reg))
920 unsigned Opc = UseMI->getOpcode();
921 if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64) {
922 // Don't fold if we are using source modifiers. The new VOP2 instructions
924 if (hasModifiersSet(*UseMI, AMDGPU::OpName::src0_modifiers) ||
925 hasModifiersSet(*UseMI, AMDGPU::OpName::src1_modifiers) ||
926 hasModifiersSet(*UseMI, AMDGPU::OpName::src2_modifiers)) {
930 MachineOperand *Src0 = getNamedOperand(*UseMI, AMDGPU::OpName::src0);
931 MachineOperand *Src1 = getNamedOperand(*UseMI, AMDGPU::OpName::src1);
932 MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2);
934 // Multiplied part is the constant: Use v_madmk_f32
935 // We should only expect these to be on src0 due to canonicalizations.
936 if (Src0->isReg() && Src0->getReg() == Reg) {
937 if (!Src1->isReg() ||
938 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
941 if (!Src2->isReg() ||
942 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))))
945 // We need to do some weird looking operand shuffling since the madmk
946 // operands are out of the normal expected order with the multiplied
947 // constant as the last operand.
949 // v_mad_f32 src0, src1, src2 -> v_madmk_f32 src0 * src2K + src1
954 const int64_t Imm = DefMI->getOperand(1).getImm();
956 // FIXME: This would be a lot easier if we could return a new instruction
957 // instead of having to modify in place.
959 // Remove these first since they are at the end.
960 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
961 AMDGPU::OpName::omod));
962 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
963 AMDGPU::OpName::clamp));
965 unsigned Src1Reg = Src1->getReg();
966 unsigned Src1SubReg = Src1->getSubReg();
967 unsigned Src2Reg = Src2->getReg();
968 unsigned Src2SubReg = Src2->getSubReg();
969 Src0->setReg(Src1Reg);
970 Src0->setSubReg(Src1SubReg);
971 Src0->setIsKill(Src1->isKill());
973 Src1->setReg(Src2Reg);
974 Src1->setSubReg(Src2SubReg);
975 Src1->setIsKill(Src2->isKill());
977 if (Opc == AMDGPU::V_MAC_F32_e64) {
978 UseMI->untieRegOperand(
979 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
982 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
983 AMDGPU::OpName::src2));
984 // ChangingToImmediate adds Src2 back to the instruction.
985 Src2->ChangeToImmediate(Imm);
987 removeModOperands(*UseMI);
988 UseMI->setDesc(get(AMDGPU::V_MADMK_F32));
990 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
992 DefMI->eraseFromParent();
997 // Added part is the constant: Use v_madak_f32
998 if (Src2->isReg() && Src2->getReg() == Reg) {
999 // Not allowed to use constant bus for another operand.
1000 // We can however allow an inline immediate as src0.
1001 if (!Src0->isImm() &&
1002 (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))
1005 if (!Src1->isReg() ||
1006 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
1009 const int64_t Imm = DefMI->getOperand(1).getImm();
1011 // FIXME: This would be a lot easier if we could return a new instruction
1012 // instead of having to modify in place.
1014 // Remove these first since they are at the end.
1015 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1016 AMDGPU::OpName::omod));
1017 UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc,
1018 AMDGPU::OpName::clamp));
1020 if (Opc == AMDGPU::V_MAC_F32_e64) {
1021 UseMI->untieRegOperand(
1022 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
1025 // ChangingToImmediate adds Src2 back to the instruction.
1026 Src2->ChangeToImmediate(Imm);
1028 // These come before src2.
1029 removeModOperands(*UseMI);
1030 UseMI->setDesc(get(AMDGPU::V_MADAK_F32));
1032 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1034 DefMI->eraseFromParent();
1043 static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
1044 int WidthB, int OffsetB) {
1045 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1046 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1047 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1048 return LowOffset + LowWidth <= HighOffset;
1051 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
1052 MachineInstr *MIb) const {
1053 unsigned BaseReg0, Offset0;
1054 unsigned BaseReg1, Offset1;
1056 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) &&
1057 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) {
1058 assert(MIa->hasOneMemOperand() && MIb->hasOneMemOperand() &&
1059 "read2 / write2 not expected here yet");
1060 unsigned Width0 = (*MIa->memoperands_begin())->getSize();
1061 unsigned Width1 = (*MIb->memoperands_begin())->getSize();
1062 if (BaseReg0 == BaseReg1 &&
1063 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
1071 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
1073 AliasAnalysis *AA) const {
1074 unsigned Opc0 = MIa->getOpcode();
1075 unsigned Opc1 = MIb->getOpcode();
1077 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1078 "MIa must load from or modify a memory location");
1079 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&
1080 "MIb must load from or modify a memory location");
1082 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects())
1085 // XXX - Can we relax this between address spaces?
1086 if (MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
1089 // TODO: Should we check the address space from the MachineMemOperand? That
1090 // would allow us to distinguish objects we know don't alias based on the
1091 // underlying addres space, even if it was lowered to a different one,
1092 // e.g. private accesses lowered to use MUBUF instructions on a scratch
1096 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1098 return !isFLAT(Opc1);
1101 if (isMUBUF(Opc0) || isMTBUF(Opc0)) {
1102 if (isMUBUF(Opc1) || isMTBUF(Opc1))
1103 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1105 return !isFLAT(Opc1) && !isSMRD(Opc1);
1110 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1112 return !isFLAT(Opc1) && !isMUBUF(Opc0) && !isMTBUF(Opc0);
1117 return checkInstOffsetsDoNotOverlap(MIa, MIb);
1125 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
1126 MachineBasicBlock::iterator &MI,
1127 LiveVariables *LV) const {
1129 switch (MI->getOpcode()) {
1130 default: return nullptr;
1131 case AMDGPU::V_MAC_F32_e64: break;
1132 case AMDGPU::V_MAC_F32_e32: {
1133 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1134 if (Src0->isImm() && !isInlineConstant(*Src0, 4))
1140 const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::dst);
1141 const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
1142 const MachineOperand *Src1 = getNamedOperand(*MI, AMDGPU::OpName::src1);
1143 const MachineOperand *Src2 = getNamedOperand(*MI, AMDGPU::OpName::src2);
1145 return BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_MAD_F32))
1147 .addImm(0) // Src0 mods
1149 .addImm(0) // Src1 mods
1151 .addImm(0) // Src mods
1157 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
1158 int64_t SVal = Imm.getSExtValue();
1159 if (SVal >= -16 && SVal <= 64)
1162 if (Imm.getBitWidth() == 64) {
1163 uint64_t Val = Imm.getZExtValue();
1164 return (DoubleToBits(0.0) == Val) ||
1165 (DoubleToBits(1.0) == Val) ||
1166 (DoubleToBits(-1.0) == Val) ||
1167 (DoubleToBits(0.5) == Val) ||
1168 (DoubleToBits(-0.5) == Val) ||
1169 (DoubleToBits(2.0) == Val) ||
1170 (DoubleToBits(-2.0) == Val) ||
1171 (DoubleToBits(4.0) == Val) ||
1172 (DoubleToBits(-4.0) == Val);
1175 // The actual type of the operand does not seem to matter as long
1176 // as the bits match one of the inline immediate values. For example:
1178 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
1179 // so it is a legal inline immediate.
1181 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
1182 // floating-point, so it is a legal inline immediate.
1183 uint32_t Val = Imm.getZExtValue();
1185 return (FloatToBits(0.0f) == Val) ||
1186 (FloatToBits(1.0f) == Val) ||
1187 (FloatToBits(-1.0f) == Val) ||
1188 (FloatToBits(0.5f) == Val) ||
1189 (FloatToBits(-0.5f) == Val) ||
1190 (FloatToBits(2.0f) == Val) ||
1191 (FloatToBits(-2.0f) == Val) ||
1192 (FloatToBits(4.0f) == Val) ||
1193 (FloatToBits(-4.0f) == Val);
1196 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
1197 unsigned OpSize) const {
1199 // MachineOperand provides no way to tell the true operand size, since it
1200 // only records a 64-bit value. We need to know the size to determine if a
1201 // 32-bit floating point immediate bit pattern is legal for an integer
1202 // immediate. It would be for any 32-bit integer operand, but would not be
1203 // for a 64-bit one.
1205 unsigned BitSize = 8 * OpSize;
1206 return isInlineConstant(APInt(BitSize, MO.getImm(), true));
1212 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO,
1213 unsigned OpSize) const {
1214 return MO.isImm() && !isInlineConstant(MO, OpSize);
1217 static bool compareMachineOp(const MachineOperand &Op0,
1218 const MachineOperand &Op1) {
1219 if (Op0.getType() != Op1.getType())
1222 switch (Op0.getType()) {
1223 case MachineOperand::MO_Register:
1224 return Op0.getReg() == Op1.getReg();
1225 case MachineOperand::MO_Immediate:
1226 return Op0.getImm() == Op1.getImm();
1228 llvm_unreachable("Didn't expect to be comparing these operand types");
1232 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
1233 const MachineOperand &MO) const {
1234 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
1236 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI());
1238 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
1241 if (OpInfo.RegClass < 0)
1244 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize();
1245 if (isLiteralConstant(MO, OpSize))
1246 return RI.opCanUseLiteralConstant(OpInfo.OperandType);
1248 return RI.opCanUseInlineConstant(OpInfo.OperandType);
1251 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1252 int Op32 = AMDGPU::getVOPe32(Opcode);
1256 return pseudoToMCOpcode(Op32) != -1;
1259 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
1260 // The src0_modifier operand is present on all instructions
1261 // that have modifiers.
1263 return AMDGPU::getNamedOperandIdx(Opcode,
1264 AMDGPU::OpName::src0_modifiers) != -1;
1267 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
1268 unsigned OpName) const {
1269 const MachineOperand *Mods = getNamedOperand(MI, OpName);
1270 return Mods && Mods->getImm();
1273 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
1274 const MachineOperand &MO,
1275 unsigned OpSize) const {
1276 // Literal constants use the constant bus.
1277 if (isLiteralConstant(MO, OpSize))
1280 if (!MO.isReg() || !MO.isUse())
1283 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1284 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
1286 // FLAT_SCR is just an SGPR pair.
1287 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
1290 // EXEC register uses the constant bus.
1291 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
1294 // SGPRs use the constant bus
1295 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
1296 (!MO.isImplicit() &&
1297 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
1298 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
1305 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1306 StringRef &ErrInfo) const {
1307 uint16_t Opcode = MI->getOpcode();
1308 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1309 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
1310 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
1311 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
1313 // Make sure the number of operands is correct.
1314 const MCInstrDesc &Desc = get(Opcode);
1315 if (!Desc.isVariadic() &&
1316 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
1317 ErrInfo = "Instruction has wrong number of operands.";
1321 // Make sure the register classes are correct
1322 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
1323 if (MI->getOperand(i).isFPImm()) {
1324 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
1325 "all fp values to integers.";
1329 int RegClass = Desc.OpInfo[i].RegClass;
1331 switch (Desc.OpInfo[i].OperandType) {
1332 case MCOI::OPERAND_REGISTER:
1333 if (MI->getOperand(i).isImm()) {
1334 ErrInfo = "Illegal immediate value for operand.";
1338 case AMDGPU::OPERAND_REG_IMM32:
1340 case AMDGPU::OPERAND_REG_INLINE_C:
1341 if (isLiteralConstant(MI->getOperand(i),
1342 RI.getRegClass(RegClass)->getSize())) {
1343 ErrInfo = "Illegal immediate value for operand.";
1347 case MCOI::OPERAND_IMMEDIATE:
1348 // Check if this operand is an immediate.
1349 // FrameIndex operands will be replaced by immediates, so they are
1351 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFI()) {
1352 ErrInfo = "Expected immediate, but got non-immediate";
1360 if (!MI->getOperand(i).isReg())
1363 if (RegClass != -1) {
1364 unsigned Reg = MI->getOperand(i).getReg();
1365 if (TargetRegisterInfo::isVirtualRegister(Reg))
1368 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1369 if (!RC->contains(Reg)) {
1370 ErrInfo = "Operand has incorrect register class.";
1378 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
1379 // Only look at the true operands. Only a real operand can use the constant
1380 // bus, and we don't want to check pseudo-operands like the source modifier
1382 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
1384 unsigned ConstantBusCount = 0;
1385 unsigned SGPRUsed = AMDGPU::NoRegister;
1386 for (int OpIdx : OpIndices) {
1389 const MachineOperand &MO = MI->getOperand(OpIdx);
1390 if (usesConstantBus(MRI, MO, getOpSize(Opcode, OpIdx))) {
1392 if (MO.getReg() != SGPRUsed)
1394 SGPRUsed = MO.getReg();
1400 if (ConstantBusCount > 1) {
1401 ErrInfo = "VOP* instruction uses the constant bus more than once";
1406 // Verify misc. restrictions on specific instructions.
1407 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1408 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1409 const MachineOperand &Src0 = MI->getOperand(Src0Idx);
1410 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1411 const MachineOperand &Src2 = MI->getOperand(Src2Idx);
1412 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1413 if (!compareMachineOp(Src0, Src1) &&
1414 !compareMachineOp(Src0, Src2)) {
1415 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1424 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1425 switch (MI.getOpcode()) {
1426 default: return AMDGPU::INSTRUCTION_LIST_END;
1427 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1428 case AMDGPU::COPY: return AMDGPU::COPY;
1429 case AMDGPU::PHI: return AMDGPU::PHI;
1430 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1431 case AMDGPU::S_MOV_B32:
1432 return MI.getOperand(1).isReg() ?
1433 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1434 case AMDGPU::S_ADD_I32:
1435 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1436 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1437 case AMDGPU::S_SUB_I32:
1438 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1439 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1440 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1441 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1442 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1443 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1444 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1445 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1446 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1447 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1448 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1449 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1450 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1451 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1452 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1453 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1454 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1455 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1456 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1457 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1458 case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64;
1459 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1460 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1461 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1462 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1463 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1464 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1465 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1466 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1467 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1468 case AMDGPU::S_LOAD_DWORD_IMM:
1469 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1470 case AMDGPU::S_LOAD_DWORDX2_IMM:
1471 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1472 case AMDGPU::S_LOAD_DWORDX4_IMM:
1473 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1474 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
1475 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1476 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1477 case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
1481 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1482 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1485 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1486 unsigned OpNo) const {
1487 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1488 const MCInstrDesc &Desc = get(MI.getOpcode());
1489 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1490 Desc.OpInfo[OpNo].RegClass == -1) {
1491 unsigned Reg = MI.getOperand(OpNo).getReg();
1493 if (TargetRegisterInfo::isVirtualRegister(Reg))
1494 return MRI.getRegClass(Reg);
1495 return RI.getPhysRegClass(Reg);
1498 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1499 return RI.getRegClass(RCID);
1502 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1503 switch (MI.getOpcode()) {
1505 case AMDGPU::REG_SEQUENCE:
1507 case AMDGPU::INSERT_SUBREG:
1508 return RI.hasVGPRs(getOpRegClass(MI, 0));
1510 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1514 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1515 MachineBasicBlock::iterator I = MI;
1516 MachineBasicBlock *MBB = MI->getParent();
1517 MachineOperand &MO = MI->getOperand(OpIdx);
1518 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1519 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1520 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1521 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1523 Opcode = AMDGPU::COPY;
1524 else if (RI.isSGPRClass(RC))
1525 Opcode = AMDGPU::S_MOV_B32;
1528 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1529 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
1530 VRC = &AMDGPU::VReg_64RegClass;
1532 VRC = &AMDGPU::VGPR_32RegClass;
1534 unsigned Reg = MRI.createVirtualRegister(VRC);
1535 DebugLoc DL = MBB->findDebugLoc(I);
1536 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
1538 MO.ChangeToRegister(Reg, false);
1541 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1542 MachineRegisterInfo &MRI,
1543 MachineOperand &SuperReg,
1544 const TargetRegisterClass *SuperRC,
1546 const TargetRegisterClass *SubRC)
1548 assert(SuperReg.isReg());
1550 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1551 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1553 // Just in case the super register is itself a sub-register, copy it to a new
1554 // value so we don't need to worry about merging its subreg index with the
1555 // SubIdx passed to this function. The register coalescer should be able to
1556 // eliminate this extra copy.
1557 MachineBasicBlock *MBB = MI->getParent();
1558 DebugLoc DL = MI->getDebugLoc();
1560 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
1561 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
1563 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
1564 .addReg(NewSuperReg, 0, SubIdx);
1569 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1570 MachineBasicBlock::iterator MII,
1571 MachineRegisterInfo &MRI,
1573 const TargetRegisterClass *SuperRC,
1575 const TargetRegisterClass *SubRC) const {
1577 // XXX - Is there a better way to do this?
1578 if (SubIdx == AMDGPU::sub0)
1579 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1580 if (SubIdx == AMDGPU::sub1)
1581 return MachineOperand::CreateImm(Op.getImm() >> 32);
1583 llvm_unreachable("Unhandled register index for immediate");
1586 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1588 return MachineOperand::CreateReg(SubReg, false);
1591 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
1592 MachineBasicBlock::iterator MI,
1593 MachineRegisterInfo &MRI,
1594 const TargetRegisterClass *RC,
1595 const MachineOperand &Op) const {
1596 MachineBasicBlock *MBB = MI->getParent();
1597 DebugLoc DL = MI->getDebugLoc();
1598 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1599 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1600 unsigned Dst = MRI.createVirtualRegister(RC);
1602 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1604 .addImm(Op.getImm() & 0xFFFFFFFF);
1605 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1607 .addImm(Op.getImm() >> 32);
1609 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
1611 .addImm(AMDGPU::sub0)
1613 .addImm(AMDGPU::sub1);
1615 Worklist.push_back(Lo);
1616 Worklist.push_back(Hi);
1621 // Change the order of operands from (0, 1, 2) to (0, 2, 1)
1622 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {
1623 assert(Inst->getNumExplicitOperands() == 3);
1624 MachineOperand Op1 = Inst->getOperand(1);
1625 Inst->RemoveOperand(1);
1626 Inst->addOperand(Op1);
1629 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1630 const MachineOperand *MO) const {
1631 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1632 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1633 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1634 const TargetRegisterClass *DefinedRC =
1635 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1637 MO = &MI->getOperand(OpIdx);
1639 if (isVALU(InstDesc.Opcode) &&
1640 usesConstantBus(MRI, *MO, DefinedRC->getSize())) {
1642 MO->isReg() ? MO->getReg() : (unsigned)AMDGPU::NoRegister;
1643 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1646 const MachineOperand &Op = MI->getOperand(i);
1647 if (Op.isReg() && Op.getReg() != SGPRUsed &&
1648 usesConstantBus(MRI, Op, getOpSize(*MI, i))) {
1656 const TargetRegisterClass *RC =
1657 TargetRegisterInfo::isVirtualRegister(MO->getReg()) ?
1658 MRI.getRegClass(MO->getReg()) :
1659 RI.getPhysRegClass(MO->getReg());
1661 // In order to be legal, the common sub-class must be equal to the
1662 // class of the current operand. For example:
1664 // v_mov_b32 s0 ; Operand defined as vsrc_32
1665 // ; RI.getCommonSubClass(s0,vsrc_32) = sgpr ; LEGAL
1667 // s_sendmsg 0, s0 ; Operand defined as m0reg
1668 // ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
1670 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
1674 // Handle non-register types that are treated like immediates.
1675 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
1678 // This operand expects an immediate.
1682 return isImmOperandLegal(MI, OpIdx, *MO);
1685 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1686 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1688 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1689 AMDGPU::OpName::src0);
1690 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1691 AMDGPU::OpName::src1);
1692 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1693 AMDGPU::OpName::src2);
1696 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1698 if (!isOperandLegal(MI, Src0Idx))
1699 legalizeOpWithMove(MI, Src0Idx);
1702 if (isOperandLegal(MI, Src1Idx))
1705 // Usually src0 of VOP2 instructions allow more types of inputs
1706 // than src1, so try to commute the instruction to decrease our
1707 // chances of having to insert a MOV instruction to legalize src1.
1708 if (MI->isCommutable()) {
1709 if (commuteInstruction(MI))
1710 // If we are successful in commuting, then we know MI is legal, so
1715 legalizeOpWithMove(MI, Src1Idx);
1719 // XXX - Do any VOP3 instructions read VCC?
1721 if (isVOP3(MI->getOpcode())) {
1722 int VOP3Idx[3] = { Src0Idx, Src1Idx, Src2Idx };
1724 // Find the one SGPR operand we are allowed to use.
1725 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
1727 for (unsigned i = 0; i < 3; ++i) {
1728 int Idx = VOP3Idx[i];
1731 MachineOperand &MO = MI->getOperand(Idx);
1734 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1735 continue; // VGPRs are legal
1737 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1739 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1740 SGPRReg = MO.getReg();
1741 // We can use one SGPR in each VOP3 instruction.
1744 } else if (!isLiteralConstant(MO, getOpSize(MI->getOpcode(), Idx))) {
1745 // If it is not a register and not a literal constant, then it must be
1746 // an inline constant which is always legal.
1749 // If we make it this far, then the operand is not legal and we must
1751 legalizeOpWithMove(MI, Idx);
1755 // Legalize REG_SEQUENCE and PHI
1756 // The register class of the operands much be the same type as the register
1757 // class of the output.
1758 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
1759 MI->getOpcode() == AMDGPU::PHI) {
1760 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1761 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1762 if (!MI->getOperand(i).isReg() ||
1763 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1765 const TargetRegisterClass *OpRC =
1766 MRI.getRegClass(MI->getOperand(i).getReg());
1767 if (RI.hasVGPRs(OpRC)) {
1774 // If any of the operands are VGPR registers, then they all most be
1775 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1777 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1780 VRC = RI.getEquivalentVGPRClass(SRC);
1787 // Update all the operands so they have the same type.
1788 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1789 if (!MI->getOperand(i).isReg() ||
1790 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1792 unsigned DstReg = MRI.createVirtualRegister(RC);
1793 MachineBasicBlock *InsertBB;
1794 MachineBasicBlock::iterator Insert;
1795 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1796 InsertBB = MI->getParent();
1799 // MI is a PHI instruction.
1800 InsertBB = MI->getOperand(i + 1).getMBB();
1801 Insert = InsertBB->getFirstTerminator();
1803 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1804 get(AMDGPU::COPY), DstReg)
1805 .addOperand(MI->getOperand(i));
1806 MI->getOperand(i).setReg(DstReg);
1810 // Legalize INSERT_SUBREG
1811 // src0 must have the same register class as dst
1812 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1813 unsigned Dst = MI->getOperand(0).getReg();
1814 unsigned Src0 = MI->getOperand(1).getReg();
1815 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1816 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1817 if (DstRC != Src0RC) {
1818 MachineBasicBlock &MBB = *MI->getParent();
1819 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1820 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1822 MI->getOperand(1).setReg(NewSrc0);
1827 // Legalize MUBUF* instructions
1828 // FIXME: If we start using the non-addr64 instructions for compute, we
1829 // may need to legalize them here.
1831 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1832 if (SRsrcIdx != -1) {
1833 // We have an MUBUF instruction
1834 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1835 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1836 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1837 RI.getRegClass(SRsrcRC))) {
1838 // The operands are legal.
1839 // FIXME: We may need to legalize operands besided srsrc.
1843 MachineBasicBlock &MBB = *MI->getParent();
1844 // Extract the ptr from the resource descriptor.
1846 // SRsrcPtrLo = srsrc:sub0
1847 unsigned SRsrcPtrLo = buildExtractSubReg(MI, MRI, *SRsrc,
1848 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VGPR_32RegClass);
1850 // SRsrcPtrHi = srsrc:sub1
1851 unsigned SRsrcPtrHi = buildExtractSubReg(MI, MRI, *SRsrc,
1852 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VGPR_32RegClass);
1854 // Create an empty resource descriptor
1855 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1856 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1857 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1858 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1859 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
1862 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1866 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1867 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1869 .addImm(RsrcDataFormat & 0xFFFFFFFF);
1871 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1872 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1874 .addImm(RsrcDataFormat >> 32);
1876 // NewSRsrc = {Zero64, SRsrcFormat}
1877 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1880 .addImm(AMDGPU::sub0_sub1)
1881 .addReg(SRsrcFormatLo)
1882 .addImm(AMDGPU::sub2)
1883 .addReg(SRsrcFormatHi)
1884 .addImm(AMDGPU::sub3);
1886 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1887 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1888 unsigned NewVAddrLo;
1889 unsigned NewVAddrHi;
1891 // This is already an ADDR64 instruction so we need to add the pointer
1892 // extracted from the resource descriptor to the current value of VAddr.
1893 NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1894 NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1896 // NewVaddrLo = SRsrcPtrLo + VAddr:sub0
1897 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
1900 .addReg(VAddr->getReg(), 0, AMDGPU::sub0)
1901 .addReg(AMDGPU::VCC, RegState::ImplicitDefine);
1903 // NewVaddrHi = SRsrcPtrHi + VAddr:sub1
1904 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
1907 .addReg(VAddr->getReg(), 0, AMDGPU::sub1)
1908 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
1909 .addReg(AMDGPU::VCC, RegState::Implicit);
1912 // This instructions is the _OFFSET variant, so we need to convert it to
1914 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
1915 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
1916 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
1918 // Create the new instruction.
1919 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
1920 MachineInstr *Addr64 =
1921 BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
1923 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
1924 // This will be replaced later
1925 // with the new value of vaddr.
1927 .addOperand(*SOffset)
1928 .addOperand(*Offset)
1933 MI->removeFromParent();
1936 NewVAddrLo = SRsrcPtrLo;
1937 NewVAddrHi = SRsrcPtrHi;
1938 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1939 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
1942 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1943 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1946 .addImm(AMDGPU::sub0)
1948 .addImm(AMDGPU::sub1);
1951 // Update the instruction to use NewVaddr
1952 VAddr->setReg(NewVAddr);
1953 // Update the instruction to use NewSRsrc
1954 SRsrc->setReg(NewSRsrc);
1958 void SIInstrInfo::splitSMRD(MachineInstr *MI,
1959 const TargetRegisterClass *HalfRC,
1960 unsigned HalfImmOp, unsigned HalfSGPROp,
1961 MachineInstr *&Lo, MachineInstr *&Hi) const {
1963 DebugLoc DL = MI->getDebugLoc();
1964 MachineBasicBlock *MBB = MI->getParent();
1965 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1966 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
1967 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
1968 unsigned HalfSize = HalfRC->getSize();
1969 const MachineOperand *OffOp =
1970 getNamedOperand(*MI, AMDGPU::OpName::offset);
1971 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
1973 // The SMRD has an 8-bit offset in dwords on SI and a 20-bit offset in bytes
1976 bool IsKill = SBase->isKill();
1979 MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() >=
1980 AMDGPUSubtarget::VOLCANIC_ISLANDS;
1981 unsigned OffScale = isVI ? 1 : 4;
1982 // Handle the _IMM variant
1983 unsigned LoOffset = OffOp->getImm() * OffScale;
1984 unsigned HiOffset = LoOffset + HalfSize;
1985 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
1986 // Use addReg instead of addOperand
1987 // to make sure kill flag is cleared.
1988 .addReg(SBase->getReg(), 0, SBase->getSubReg())
1989 .addImm(LoOffset / OffScale);
1991 if (!isUInt<20>(HiOffset) || (!isVI && !isUInt<8>(HiOffset / OffScale))) {
1992 unsigned OffsetSGPR =
1993 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1994 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
1995 .addImm(HiOffset); // The offset in register is in bytes.
1996 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
1997 .addReg(SBase->getReg(), getKillRegState(IsKill),
1999 .addReg(OffsetSGPR);
2001 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
2002 .addReg(SBase->getReg(), getKillRegState(IsKill),
2004 .addImm(HiOffset / OffScale);
2007 // Handle the _SGPR variant
2008 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
2009 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
2010 .addReg(SBase->getReg(), 0, SBase->getSubReg())
2012 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
2013 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
2016 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp))
2017 .addReg(SBase->getReg(), getKillRegState(IsKill),
2019 .addReg(OffsetSGPR);
2022 unsigned SubLo, SubHi;
2025 SubLo = AMDGPU::sub0;
2026 SubHi = AMDGPU::sub1;
2029 SubLo = AMDGPU::sub0_sub1;
2030 SubHi = AMDGPU::sub2_sub3;
2033 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
2034 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
2037 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
2038 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
2041 llvm_unreachable("Unhandled HalfSize");
2044 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE))
2045 .addOperand(MI->getOperand(0))
2052 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
2053 MachineBasicBlock *MBB = MI->getParent();
2054 int DstIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
2055 assert(DstIdx != -1);
2056 unsigned DstRCID = get(MI->getOpcode()).OpInfo[DstIdx].RegClass;
2057 switch(RI.getRegClass(DstRCID)->getSize()) {
2061 unsigned NewOpcode = getVALUOp(*MI);
2065 if (MI->getOperand(2).isReg()) {
2066 RegOffset = MI->getOperand(2).getReg();
2069 assert(MI->getOperand(2).isImm());
2070 // SMRD instructions take a dword offsets on SI and byte offset on VI
2071 // and MUBUF instructions always take a byte offset.
2072 ImmOffset = MI->getOperand(2).getImm();
2073 if (MBB->getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() <=
2074 AMDGPUSubtarget::SEA_ISLANDS)
2076 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2078 if (isUInt<12>(ImmOffset)) {
2079 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2083 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
2090 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
2091 unsigned DWord0 = RegOffset;
2092 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2093 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2094 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
2095 uint64_t RsrcDataFormat = getDefaultRsrcDataFormat();
2097 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
2099 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
2100 .addImm(RsrcDataFormat & 0xFFFFFFFF);
2101 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
2102 .addImm(RsrcDataFormat >> 32);
2103 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
2105 .addImm(AMDGPU::sub0)
2107 .addImm(AMDGPU::sub1)
2109 .addImm(AMDGPU::sub2)
2111 .addImm(AMDGPU::sub3);
2112 MI->setDesc(get(NewOpcode));
2113 if (MI->getOperand(2).isReg()) {
2114 MI->getOperand(2).setReg(SRsrc);
2116 MI->getOperand(2).ChangeToRegister(SRsrc, false);
2118 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0));
2119 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
2120 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // glc
2121 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // slc
2122 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(0)); // tfe
2124 const TargetRegisterClass *NewDstRC =
2125 RI.getRegClass(get(NewOpcode).OpInfo[0].RegClass);
2127 unsigned DstReg = MI->getOperand(0).getReg();
2128 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2129 MRI.replaceRegWith(DstReg, NewDstReg);
2133 MachineInstr *Lo, *Hi;
2134 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
2135 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
2136 MI->eraseFromParent();
2137 moveSMRDToVALU(Lo, MRI);
2138 moveSMRDToVALU(Hi, MRI);
2143 MachineInstr *Lo, *Hi;
2144 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
2145 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
2146 MI->eraseFromParent();
2147 moveSMRDToVALU(Lo, MRI);
2148 moveSMRDToVALU(Hi, MRI);
2154 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
2155 SmallVector<MachineInstr *, 128> Worklist;
2156 Worklist.push_back(&TopInst);
2158 while (!Worklist.empty()) {
2159 MachineInstr *Inst = Worklist.pop_back_val();
2160 MachineBasicBlock *MBB = Inst->getParent();
2161 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2163 unsigned Opcode = Inst->getOpcode();
2164 unsigned NewOpcode = getVALUOp(*Inst);
2166 // Handle some special cases
2169 if (isSMRD(Inst->getOpcode())) {
2170 moveSMRDToVALU(Inst, MRI);
2173 case AMDGPU::S_MOV_B64: {
2174 DebugLoc DL = Inst->getDebugLoc();
2176 // If the source operand is a register we can replace this with a
2178 if (Inst->getOperand(1).isReg()) {
2179 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
2180 .addOperand(Inst->getOperand(0))
2181 .addOperand(Inst->getOperand(1));
2182 Worklist.push_back(Copy);
2184 // Otherwise, we need to split this into two movs, because there is
2185 // no 64-bit VALU move instruction.
2186 unsigned Reg = Inst->getOperand(0).getReg();
2187 unsigned Dst = split64BitImm(Worklist,
2190 MRI.getRegClass(Reg),
2191 Inst->getOperand(1));
2192 MRI.replaceRegWith(Reg, Dst);
2194 Inst->eraseFromParent();
2197 case AMDGPU::S_AND_B64:
2198 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32);
2199 Inst->eraseFromParent();
2202 case AMDGPU::S_OR_B64:
2203 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32);
2204 Inst->eraseFromParent();
2207 case AMDGPU::S_XOR_B64:
2208 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32);
2209 Inst->eraseFromParent();
2212 case AMDGPU::S_NOT_B64:
2213 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
2214 Inst->eraseFromParent();
2217 case AMDGPU::S_BCNT1_I32_B64:
2218 splitScalar64BitBCNT(Worklist, Inst);
2219 Inst->eraseFromParent();
2222 case AMDGPU::S_BFE_I64: {
2223 splitScalar64BitBFE(Worklist, Inst);
2224 Inst->eraseFromParent();
2228 case AMDGPU::S_LSHL_B32:
2229 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2230 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
2234 case AMDGPU::S_ASHR_I32:
2235 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2236 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
2240 case AMDGPU::S_LSHR_B32:
2241 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2242 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
2246 case AMDGPU::S_LSHL_B64:
2247 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2248 NewOpcode = AMDGPU::V_LSHLREV_B64;
2252 case AMDGPU::S_ASHR_I64:
2253 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2254 NewOpcode = AMDGPU::V_ASHRREV_I64;
2258 case AMDGPU::S_LSHR_B64:
2259 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
2260 NewOpcode = AMDGPU::V_LSHRREV_B64;
2265 case AMDGPU::S_BFE_U64:
2266 case AMDGPU::S_BFM_B64:
2267 llvm_unreachable("Moving this op to VALU not implemented");
2270 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
2271 // We cannot move this instruction to the VALU, so we should try to
2272 // legalize its operands instead.
2273 legalizeOperands(Inst);
2277 // Use the new VALU Opcode.
2278 const MCInstrDesc &NewDesc = get(NewOpcode);
2279 Inst->setDesc(NewDesc);
2281 // Remove any references to SCC. Vector instructions can't read from it, and
2282 // We're just about to add the implicit use / defs of VCC, and we don't want
2284 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
2285 MachineOperand &Op = Inst->getOperand(i);
2286 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
2287 Inst->RemoveOperand(i);
2290 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
2291 // We are converting these to a BFE, so we need to add the missing
2292 // operands for the size and offset.
2293 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
2294 Inst->addOperand(MachineOperand::CreateImm(0));
2295 Inst->addOperand(MachineOperand::CreateImm(Size));
2297 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
2298 // The VALU version adds the second operand to the result, so insert an
2300 Inst->addOperand(MachineOperand::CreateImm(0));
2303 Inst->addImplicitDefUseOperands(*Inst->getParent()->getParent());
2305 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
2306 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
2307 // If we need to move this to VGPRs, we need to unpack the second operand
2308 // back into the 2 separate ones for bit offset and width.
2309 assert(OffsetWidthOp.isImm() &&
2310 "Scalar BFE is only implemented for constant width and offset");
2311 uint32_t Imm = OffsetWidthOp.getImm();
2313 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2314 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2315 Inst->RemoveOperand(2); // Remove old immediate.
2316 Inst->addOperand(MachineOperand::CreateImm(Offset));
2317 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
2320 // Update the destination register class.
2322 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
2325 // For target instructions, getOpRegClass just returns the virtual
2326 // register class associated with the operand, so we need to find an
2327 // equivalent VGPR register class in order to move the instruction to the
2331 case AMDGPU::REG_SEQUENCE:
2332 case AMDGPU::INSERT_SUBREG:
2333 if (RI.hasVGPRs(NewDstRC))
2335 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
2343 unsigned DstReg = Inst->getOperand(0).getReg();
2344 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
2345 MRI.replaceRegWith(DstReg, NewDstReg);
2347 // Legalize the operands
2348 legalizeOperands(Inst);
2350 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
2351 E = MRI.use_end(); I != E; ++I) {
2352 MachineInstr &UseMI = *I->getParent();
2353 if (!canReadVGPR(UseMI, I.getOperandNo())) {
2354 Worklist.push_back(&UseMI);
2360 //===----------------------------------------------------------------------===//
2361 // Indirect addressing callbacks
2362 //===----------------------------------------------------------------------===//
2364 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2365 unsigned Channel) const {
2366 assert(Channel == 0);
2370 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2371 return &AMDGPU::VGPR_32RegClass;
2374 void SIInstrInfo::splitScalar64BitUnaryOp(
2375 SmallVectorImpl<MachineInstr *> &Worklist,
2377 unsigned Opcode) const {
2378 MachineBasicBlock &MBB = *Inst->getParent();
2379 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2381 MachineOperand &Dest = Inst->getOperand(0);
2382 MachineOperand &Src0 = Inst->getOperand(1);
2383 DebugLoc DL = Inst->getDebugLoc();
2385 MachineBasicBlock::iterator MII = Inst;
2387 const MCInstrDesc &InstDesc = get(Opcode);
2388 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2389 MRI.getRegClass(Src0.getReg()) :
2390 &AMDGPU::SGPR_32RegClass;
2392 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2394 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2395 AMDGPU::sub0, Src0SubRC);
2397 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2398 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2400 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2401 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2402 .addOperand(SrcReg0Sub0);
2404 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2405 AMDGPU::sub1, Src0SubRC);
2407 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2408 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2409 .addOperand(SrcReg0Sub1);
2411 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2412 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2414 .addImm(AMDGPU::sub0)
2416 .addImm(AMDGPU::sub1);
2418 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2420 // Try to legalize the operands in case we need to swap the order to keep it
2422 Worklist.push_back(LoHalf);
2423 Worklist.push_back(HiHalf);
2426 void SIInstrInfo::splitScalar64BitBinaryOp(
2427 SmallVectorImpl<MachineInstr *> &Worklist,
2429 unsigned Opcode) const {
2430 MachineBasicBlock &MBB = *Inst->getParent();
2431 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2433 MachineOperand &Dest = Inst->getOperand(0);
2434 MachineOperand &Src0 = Inst->getOperand(1);
2435 MachineOperand &Src1 = Inst->getOperand(2);
2436 DebugLoc DL = Inst->getDebugLoc();
2438 MachineBasicBlock::iterator MII = Inst;
2440 const MCInstrDesc &InstDesc = get(Opcode);
2441 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2442 MRI.getRegClass(Src0.getReg()) :
2443 &AMDGPU::SGPR_32RegClass;
2445 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2446 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2447 MRI.getRegClass(Src1.getReg()) :
2448 &AMDGPU::SGPR_32RegClass;
2450 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2452 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2453 AMDGPU::sub0, Src0SubRC);
2454 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2455 AMDGPU::sub0, Src1SubRC);
2457 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2458 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2460 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2461 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2462 .addOperand(SrcReg0Sub0)
2463 .addOperand(SrcReg1Sub0);
2465 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2466 AMDGPU::sub1, Src0SubRC);
2467 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2468 AMDGPU::sub1, Src1SubRC);
2470 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2471 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2472 .addOperand(SrcReg0Sub1)
2473 .addOperand(SrcReg1Sub1);
2475 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2476 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2478 .addImm(AMDGPU::sub0)
2480 .addImm(AMDGPU::sub1);
2482 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2484 // Try to legalize the operands in case we need to swap the order to keep it
2486 Worklist.push_back(LoHalf);
2487 Worklist.push_back(HiHalf);
2490 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2491 MachineInstr *Inst) const {
2492 MachineBasicBlock &MBB = *Inst->getParent();
2493 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2495 MachineBasicBlock::iterator MII = Inst;
2496 DebugLoc DL = Inst->getDebugLoc();
2498 MachineOperand &Dest = Inst->getOperand(0);
2499 MachineOperand &Src = Inst->getOperand(1);
2501 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
2502 const TargetRegisterClass *SrcRC = Src.isReg() ?
2503 MRI.getRegClass(Src.getReg()) :
2504 &AMDGPU::SGPR_32RegClass;
2506 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2507 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2509 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2511 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2512 AMDGPU::sub0, SrcSubRC);
2513 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2514 AMDGPU::sub1, SrcSubRC);
2516 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg)
2517 .addOperand(SrcRegSub0)
2520 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2521 .addOperand(SrcRegSub1)
2524 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2526 Worklist.push_back(First);
2527 Worklist.push_back(Second);
2530 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
2531 MachineInstr *Inst) const {
2532 MachineBasicBlock &MBB = *Inst->getParent();
2533 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2534 MachineBasicBlock::iterator MII = Inst;
2535 DebugLoc DL = Inst->getDebugLoc();
2537 MachineOperand &Dest = Inst->getOperand(0);
2538 uint32_t Imm = Inst->getOperand(2).getImm();
2539 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
2540 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
2544 // Only sext_inreg cases handled.
2545 assert(Inst->getOpcode() == AMDGPU::S_BFE_I64 &&
2550 if (BitWidth < 32) {
2551 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2552 unsigned MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2553 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2555 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
2556 .addReg(Inst->getOperand(1).getReg(), 0, AMDGPU::sub0)
2560 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
2564 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2566 .addImm(AMDGPU::sub0)
2568 .addImm(AMDGPU::sub1);
2570 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2574 MachineOperand &Src = Inst->getOperand(1);
2575 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2576 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
2578 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
2580 .addReg(Src.getReg(), 0, AMDGPU::sub0);
2582 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
2583 .addReg(Src.getReg(), 0, AMDGPU::sub0)
2584 .addImm(AMDGPU::sub0)
2586 .addImm(AMDGPU::sub1);
2588 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2591 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2592 int OpIndices[3]) const {
2593 const MCInstrDesc &Desc = get(MI->getOpcode());
2595 // Find the one SGPR operand we are allowed to use.
2596 unsigned SGPRReg = AMDGPU::NoRegister;
2598 // First we need to consider the instruction's operand requirements before
2599 // legalizing. Some operands are required to be SGPRs, such as implicit uses
2600 // of VCC, but we are still bound by the constant bus requirement to only use
2603 // If the operand's class is an SGPR, we can never move it.
2605 for (const MachineOperand &MO : MI->implicit_operands()) {
2606 // We only care about reads.
2610 if (MO.getReg() == AMDGPU::VCC)
2613 if (MO.getReg() == AMDGPU::FLAT_SCR)
2614 return AMDGPU::FLAT_SCR;
2617 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
2618 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
2620 for (unsigned i = 0; i < 3; ++i) {
2621 int Idx = OpIndices[i];
2625 const MachineOperand &MO = MI->getOperand(Idx);
2626 if (RI.isSGPRClassID(Desc.OpInfo[Idx].RegClass))
2627 SGPRReg = MO.getReg();
2629 if (MO.isReg() && RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
2630 UsedSGPRs[i] = MO.getReg();
2633 if (SGPRReg != AMDGPU::NoRegister)
2636 // We don't have a required SGPR operand, so we have a bit more freedom in
2637 // selecting operands to move.
2639 // Try to select the most used SGPR. If an SGPR is equal to one of the
2640 // others, we choose that.
2643 // V_FMA_F32 v0, s0, s0, s0 -> No moves
2644 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
2646 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
2647 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
2648 SGPRReg = UsedSGPRs[0];
2651 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
2652 if (UsedSGPRs[1] == UsedSGPRs[2])
2653 SGPRReg = UsedSGPRs[1];
2659 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2660 MachineBasicBlock *MBB,
2661 MachineBasicBlock::iterator I,
2663 unsigned Address, unsigned OffsetReg) const {
2664 const DebugLoc &DL = MBB->findDebugLoc(I);
2665 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2666 getIndirectIndexBegin(*MBB->getParent()));
2668 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2669 .addReg(IndirectBaseReg, RegState::Define)
2670 .addOperand(I->getOperand(0))
2671 .addReg(IndirectBaseReg)
2677 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2678 MachineBasicBlock *MBB,
2679 MachineBasicBlock::iterator I,
2681 unsigned Address, unsigned OffsetReg) const {
2682 const DebugLoc &DL = MBB->findDebugLoc(I);
2683 unsigned IndirectBaseReg = AMDGPU::VGPR_32RegClass.getRegister(
2684 getIndirectIndexBegin(*MBB->getParent()));
2686 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
2687 .addOperand(I->getOperand(0))
2688 .addOperand(I->getOperand(1))
2689 .addReg(IndirectBaseReg)
2695 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2696 const MachineFunction &MF) const {
2697 int End = getIndirectIndexEnd(MF);
2698 int Begin = getIndirectIndexBegin(MF);
2704 for (int Index = Begin; Index <= End; ++Index)
2705 Reserved.set(AMDGPU::VGPR_32RegClass.getRegister(Index));
2707 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2708 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
2710 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
2711 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
2713 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
2714 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
2716 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
2717 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
2719 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
2720 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
2723 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
2724 unsigned OperandName) const {
2725 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
2729 return &MI.getOperand(Idx);
2732 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
2733 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
2734 if (ST.isAmdHsaOS()) {
2735 RsrcDataFormat |= (1ULL << 56);
2737 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2739 RsrcDataFormat |= (2ULL << 59);
2742 return RsrcDataFormat;